Paper Title: FPGA based PCI Express Gen4 NVMe SSD Platform

Paper Abstract: NVMe is creating a unique opportunity for developing solutions targeting differentiated data center storage and acceleration applications. While SOC based standard SSD controller solutions are more prevalent in consumer applications, many enterprise customers are looking at FPGA based SSD solutions for differentiation as well as ease of maintenance. The FPGA can be programmed with SSD IP blocks with enough spare gates to program unique algorithms aimed at solving specific requirements. The FTL is implemented in the embedded ARM CPU in the FPGA. Such a flexible SSD platform could be used to accelerate NVMe SSD product development. This presentation will describe the IP blocks, HW/SW partitioning, and pros and cons of an FPGA based approach.

Paper Author: Amit Saxena, VP Engineering, Mobiveil

Author Bio: Amit Saxena, VP Engineering Digital IP Business Unit, leads the strategy and development of high speed interconnect IP at Mobiveil. He has over 21 years of engineering and management experience in the semiconductor, IP, and systems industries. He was previously Director of Engineering at L&T Infotech and GDA Technologies, where he led development and deployment of high speed interconnect IP blocks including PCI Express, RapidIO, USB3, and MIPI. Amit successfully built and guided L&T's IP Engineering and Applications organizations. He holds an MS in Communication Systems from IIT Kanpur (India)..