Paper Title: PCI Express: What's Next for Flash Storage

Paper Abstract: PCI Express® 3.0 architecture has enabled flash storage to transition to high speed, low latency power efficient performance over the past few years. However, the hunger for more performance in power constrained environments continues, and PCI-SIG® keeps delivering higher performance and more features with the emergence of the PCIe 4.0 and 5.0 specifications. This presentation will review the major features of PCIe 4.0 and 5.0 technology, which will continue to enable power efficient performance required as NAND capacities scale and faster SCM (Storage Class Memories) become mainstream. Session attendees will gain insight into the current status of the PCIe 4.0 technology roll-out and testing and will learn about the 5.0 specification development and timeline for completion in 2019.

Paper Author: Justin Wenck, Senior Technical Marketing Engineer, Datacenter SSD Technical Marketing Group, Intel Corporation, PCI-SIG

Author Bio: Justin Wenck is a Senior Technical Marketing Engineer in the Datacenter SSD Technical Marketing Group at Intel, where he is responsible for dual-port NVMe SSDs. He previously was a validation lead ensuring SSDs were PCI-SIG compliant, and a team leader developing circuits for memory PHY interfaces for Intel's most advanced memory technologies. He holds a PhD and MS in electrical and computer engineering from the University of California at Davis and a BSEE from Cal Poly San Luis Obispo.