Paper Title: Bullet-Proofing PCIe in Enterprise Storage SoCs with RAS features

Paper Abstract: The race to gain silicon market share in the enterprise space prompts semiconductor companies to develop SoCs with the highest performance communication interfaces, such as PCI Express 4.0 today and soon PCIe 5.0. To mitigate the high costs and risks, designers of enterprise storage SoCs are continuously looking to foolproof their PCIe interface designs with Reliability, Availability, and Serviceability (RAS) capabilities beyond the scope of the PCIe specification. In this presentation, we explore options and techniques available to SoC designers integrating PCIe connectivity, including programmable timers and counters, debug and error injection, and other capabilities offered in enterprise-class PCIe IP.

Paper Author: Michael Fernandez, Field Applications Engineer, PLDA

Author Bio: Michael Fernandez is a Field Application Engineer at PLDA inc, based in Silicon Valley. He has over 10 years of experience PCI, PCI-X and PCI Express IP cores integration and performance issues. He has worked with PLDA’s customers worldwide to help them with architecture level decisions, integration and debugging of PCIe® based designs. Michael Hold a MS in Micro Electronic from Polytech University from Montpellier in 2008.