Paper Title: Eliminating the Error Floor for LDPC with NAND Flash

Paper Abstract: Low Density Parity Check (LDPC) codes are being deployed in SSD due to their superior signal to noise gain and Bit Error Rate (BER) performance, However, many existing methods use simplifications in the decoder algorithm such as normalized Min-Sum to reduce hardware complexity and power dissipation. Unfortunately, the simplifications usually cause the LDPC codes to exhibit error floor which is a major concern with SSD reliability. In our paper we present modeling data based on dominant trapping sets evaluation, as well as, Field Programmable Gate Array (FPGA) BER data showing the existence of error floor with normalized Min-Sum decoder. We also present data with NGD Systems customized decoder and show how the error floor is completely eliminated.

Paper Author: Shafa Dahandeh, Sr. Error Code Engineer, NGD Systems

Author Bio: Shafa Dahandeh is a recognized expert in the fields of Error Correction Codes and Signal Processing, and a key contributor in the storage industry for over 25+ years. Prior to NGD Systems, Shafa was director of advanced technology at WD, a subsidiary of Western Digital Corporation. In that position, he was responsible for the development and integration of new and emerging technologies and led the development of the WD novel iterative coding technology for solid state drives. Prior to joining WD, Shafa worked at Seagate Technology, where he led the development of several generations of SoC including Seagate’s first custom iterative coding technology, delivering industry leading performance. Shafa held various leadership positions at Seagate Technology including director of advanced electronics and director of consumer electronic products. Shafa holds M.S. and B.S. degrees in electrical and electronics engineering from the University of Oklahoma. He has numerous articles published in scientific and engineering publications, and 12 patents issued, with several more pending. related to data storage technologies.