Thursday, August 9th
8:30-10:50 AM
COMP-301-1: Increasing Performance by Moving Compute Closer to Data (Computational Storage Track Track)
Chairperson: Jim Handy, Director/Chief Analyst, Objective Analysis

Organizer: Stephen Bates, CTO, Eideticom

Paper Title: A Scalable Architecture for Image Similarity Search using Intelligent Storage

Paper Abstract: Currently the lack of such intelligence in storage devices results in a disconnect in terms of innovation between applications, OS and storage infrastructure. Meanwhile, the advent of high-performance, high-capacity flash storage has changed the dynamics of the storage-compute relationship. Today, a handful of NVMe flash devices can easily saturate the PCIe bus complex of most servers. To address this mismatch, a new paradigm is required that moves computing capabilities closer to the data. This concept, known as computational storage, provides significant in-situ compute capabilities. This talk will introduce In-Situ Processing a technology that bring computing resources to the storage device while providing a seamless programming model to create smart SSDs. For applications manipulating large data sets and when parallelism can be extracted, In-Situ Processing offers scalability, higher performance and lower power consumption. As a real use case, we will present our efforts of exploiting the use of smart SSDs for Approximate Nearest neighbor (ANN) search, where smart SSDs are leveraged to do fast, scalable searching of nearest neighbors for large image dataset.

Paper Author: Richard Mataya, Executive VP Products/Co-Founder, NGD Systems

Author Bio: Dr. Vladimir Alves has been architecting and implementing solid state storage solutions since 2005. He occupied the position of Sr. Director of SSD SoC Development at Western Digital and STEC (acquired by HGST), in charge of architecting and implementing Enterprise SSD controllers. He is now a co-founder and CTO at NGD Systems focusing on storage technology innovation for the data center and fog. Dr. Alves obtained his Ph.D. degree in Microeletronics in 1992 from the National Polytechnic Institute in Grenoble, France. He is the author of more than 30 scientific publications in the fields of SoC architecture, computer architecture, semiconductor test, self-checking and fail-safe design circuits and the co-author of patents in US and Europe