Wednesday, August 8th
8:30-10:50 AM
CTRL-201-1: Controllers and Flash Technology, Part 1 - Hardware and Algorithms (Controllers Track Track)
Chairperson: David Declercq, CTO, CodeLucida

Organizer + Instructor: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Title: Novel Error Recovery Architecture based on Machine Learning

Paper Abstract: Our previous research showed the use of machine learning techniques to predict decoding parameters and future failure can lead to great improvement in endurance and throughput for SSD. Our recent research adopt auto-adjusting prediction model which is more accurate under different failure mode and operation conditon. A Novel Architecture for Error Recovery that can extend the endurance and reduce the latency is proposed based on our research.

Paper Author: Cloud Zeng, Sr Engineer, Lite-On Storage

Author Bio: Cloud Zeng is an Associate Project Manager at the LiteOn NVM Laboratory, where he works on error control coding, signal processing, and machine learning. He has focused on developing error handling schemes that can enhance the reliability of NAND flash memory. He reported the Error Recovery research based on Machine Learning at Flash Memory Summit 2016 & 2017. He earned an MSEE and BSEE (Honors Program) from the National Chiao Tung University (Taiwan).