Paper Title: NRAM Offers Huge Speed Increases for Storage Applications While Simplifying the

Paper Abstract: Be ready for yet another letter in the world of new non-volatile memory technologies. The letter is “N” for NRAM or carbon nanotube RAM, a technology invented almost 30 years ago. Carbon nanotubes behave as a predictable resistive network in a dielectric-free construction, with the added benefits of immunity to electromagnetic effects and temperature extremes. The result is a technology with 5 nanosecond core speed with potential for unlimited write endurance. Because it is layered above existing logic, NRAM can be built on any fabrication lines including logic or RAM processes, with density scalability beyond what the DRAM processes promise. As essentially a DDR4/DDR5 memory with non-volatility, NRAM enters the market as not only a main memory, it also replaces caches in storage devices while eliminating the need for battery backup. So what is not to like? Interest is coming from typical memory customers in the consumer electronics, mobile processing, internet of things, and enterprise systems – however NRAM also fits in trans-RAM applications such as neural and mesh processing. So watch for the big “N” to be a big market in upcoming years.

Paper Author: Bill Gervasi, Principal Systems Architect, Nantero

Author Bio: Bill Gervasi, Principal Systems Architect at Nantero, is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.