| Monday, August 7th |
Monday, August 7th
8:30-Noon | | Pre-Conference Seminar A: Introduction to 3D NAND (Pre-Conference Seminar Track 1 Track) | | Organizer + Chairperson + Instructor: Chuck Sobey, Chief Scientist, ChannelScience | Speaker(s):
| | Session Description:
| Decades of progress in traditional planar (2D) semiconductor manufacturing enabled the flash industry to replace many established storage technologies. Now 3D semiconductor manufacturing has set the stage for the next wave of data storage disruption. Over half of the NAND flash bits being shipped are now 3D. As NAND manufacturers move beyond their 3rd and 4th generations of 3D NAND, this percentage will continue to grow. What do you need to know about 3D (also called “Vertical”) NAND to use it to full advantage in your next design? How is the changing role of the FTL (flash translation layer) in data center appliances changing how 3D NAND is being used, tested, and optimized? If more of the native NAND performance is exposed, what do you do with it? What can you expect to encounter when using 3D NAND in extreme environments like automotive, industrial, and IoT? How should your company position itself for the opportunities and challenges that this new technology brings? How does 3D XPoint™ from Intel or QuantX™ from Micron (unveiled at Flash Memory Summit 2016) differ from 3D NAND and how might they be used together? Now is the time to prepare yourself, your key staff, and your company. Reliable, unbiased information is critical for making the right decisions! So don’t proceed (and spend a lot of development money) without a clear understanding of the fundamentals, opportunities, and challenges of this breakthrough technology! Learn from internationally-respected storage industry consultant and expert instructor, Chuck Sobey, about the benefits and challenges of 3D flash device technologies, alternative array architectures, controller partitioning, algorithm developments, and the problems posed by the technology. This tutorial is a great way to get up-to-speed quickly on this major technology shift. Cut through the hype and confusion surrounding 3D! Conquer the fear and apprehension regarding how 3D NAND might affect you! Build a firm foundation for yourself and your team. Learn how to ask the tough questions and know when you get the right answers! This tutorial is designed for engineers, managers, and executives who must make immediate decisions implementing or optimizing 3D flash technology. It is presented by KnowledgeTek, the world’s leading data storage technology training company. Suggested prerequisites include a technical background and an interest in 3D technology; the class does not assume detailed engineering knowledge of flash memory or semiconductor processing. Course Outline 1. The Path from 2D to 3D NAND • 3D: What it is and what it isn’t • 2D wraparound and planar floating-gate flash cells • The 2D NAND flash array • Problems and challenges with 2D flash • Charge trapping NAND flash • Roadmaps for 3D NAND • The device determines the system 2. Competing Technologies and Architectures for 3D Flash • Vertical transistor designs • 3D array architectures • Accessing data • SLC to TLC and QLC in 3D • Resistive storage technologies (ReRAM) 3. Process, Design, and Test Challenges • Etch and deposition vs. lithography • Logical-to-physical translation in 3D • Testing, characterization, and defects • Controller partitioning 4. Next Steps in 3D • Accessing raw NAND • Parameter setting with machine learning • Opportunities with 3D XPoint™ QuantX™ • A lesson from The Wrath of Khan • What to watch for at the Summit! • Suggested sources of reference information
| | About the Organizer/Moderator: | Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque).As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there.Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara
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Monday, August 7th
8:30-Noon | | Pre-Conference Seminar B: Introduction to NVM Express (NVMe) (Pre-Conference Seminar Track 2 Track) | | Organizer + Chairperson + Instructor: Hugh Curley, Consultant, HughCurley.com | Speaker(s):
| | Session Description:
| NVM Express (NVMe) is a specification for connecting non-volatile memory devices such as SSDs to computers via the PCIe bus. The idea is to take advantage of the high speed of PCIe (as compared to disk interfaces such as SAS or SATA), while maintaining full standardization and access to a large ecosystem. It has rapidly become a popular interface supported by almost all major SSD makers. Storage designers and end users alike appreciate its combination of low cost, high speed, widespread support, and standardized approach. NVMe started with a clean slate to build a command set and supporting mechanism that would take advantage of the PCIe transport and SSD storage devices. It is scalable from iPads to enterprise and high performance computing. At the Flash Memory Summit, many keynote presentations and breakout sessions assume a basic understanding of NVMe. Be prepared to take full advantage of the Summit by upgrading your background with this pre-conference presentation. This presentation assumes no specific knowledge of PCIe or NVMe, but does assume a general understanding of computers. Outline of Topics: Introduction to NVMe NVMe Operation and Structures Command and status Door bells Queues Interrupts Data flow Controller Memory Buffer Host Memory Buffer Admin Commands Create/Delete Submission/Completion Queues Set/Get Features DWord parameter passing Passing parameters in memory Identify Namespace Management and Attachment I/O Commands Command List Using RDMA NVMe 1.3 Enhancements New Commands Directive Send/Receive Device Self-test Sanitize NVMe-MI Send/Receive Doorbell Buffer Configuration Virtualization Management New Features Time Stamp Host Controller Thermal Management Non-Operational Power State Configuration New Registers Boot Partition Information Boot Partition Read Select Boot Partition Buffer Location New log pages are covered with the new command or feature NVMe 1.4 Enhancement (if released) IO Determinism
| | About the Organizer/Moderator: | Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe.. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "Very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. The KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.
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Monday, August 7th
8:30-Noon | | Pre-Conference Seminar C: Persistent Memory (Pre-Conference Seminar Track 3 Track) | | Chairperson: Doug Finke, Director, Product Marketing, XitoreOrganizer: Jim Pappas, Director, Initative Marketing, Intel Server Platforms GroupOrganizer + Instructor: Jonathan Hinkle, Principal Researcher, LenovoChairperson + Instructor: Alan Bumgarner, Senior Strategic Planner for Storage Software, Intel | Speaker(s):
| | Session Description:
| Persistent memory offers the cost and capacity advantages of storage devices at memory speed. It also brings opportunities for architecting software applications to utilize its new capabilities. Of course, the tradeoffs involved in using it are far from simple. NAND flash and other types of non-volatile memory behave quite differently from standard DRAM. Handling the differences requires new methods for system integration, programming, and management. Several solutions to the problems involved are currently in use, and several groups are proposing standards for both software and hardware. The obvious advantages of persistent memory indicate that designers will need to be aware of developments in this promising technology area. This seminar will provide an in-depth look into several leading technologies, current implementations, and applications that take advantage of persistent memory in compute and storage systems. Session PM-1: Introduction to Persistent Memory 8:30 -10:15 am Session PM-2 Current Implementations 10:30 - 12:00 noon
| | About the Organizer/Moderator: | Doug Finke is Director Product Marketing at Xitore, a startup developing very high-performance NVDIMM-based SSDs. Doug is focused on increasing industry awareness of NVDIMMs and persistent memory through writing whitepapers, talking to storage industry media, and appearing at conferences such as Persistent Memory Summit and Flash Memory Summit. He has been a key contributor in the computer, semiconductor, and storage industry for over 30 years. Before joining Xitore, Doug was at HGST where he was responsible for business management of large petabyte scale storage systems. Before that Doug served as Senior Director of Product Marketing at sTec (acquired by HGST) which pioneered the concept of solid state drives (SSDs) for use in enterprise computing applications. He holds seven patents related to NVDIMM design. He earned an MBA from MIT and a BS in Computer Engineering from the University of Illinois.
Jim Pappas is the Director of Technology Initiatives in Intel’s Data Center Group. In this role, Jim is responsible to establish broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded, or served on several organizations in these areas including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, The Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry. He has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies. He has spoken at major industry events including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.
Jonathan Hinkle is Director, Systems Platform Technologist at Lenovo, where he drives new server architecture and technologies in their Enterprise Product Group. Previously, Jonathan was Storage and Memory Systems Architect at Viking Technology, where he developed next-generation memory and storage products and technologies. Before Viking, Mr. Hinkle worked at IBM where he developed server systems ranging from high-end enterprise boxes to blade servers. He is the chairman of the JC45.1 RDIMM committee and the Hybrid Memory Module task group in the JEDEC standards organization. He also invented and drove first development of the VLP DIMM and the SATADIMM SSD. He is a senior member of the IEEE and has a Bachelors and Masters degree in Computer Engineering from North Carolina State University. He is a member of the Program Executive Committee for Flash Memory Summit.
Alan Bumgarner is Senior Strategic Planner for Storage Software in Intel’s Datacenter Group. He focuses on front line technical support, remote server management of multiple datacenters, product/channel/technical marketing, field sales, and strategic product planning. With Intel for over 20 years, he earned a BS in Business Administration Systems from the University of Phoenix.
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Monday, August 7th
8:30-Noon | | Pre-Conference Seminar D: Flash Storage Networking (Pre-Conference Seminar Track 4 Track) | | Organizer + Chairperson + Instructor: Rob Davis, VP Storage Technology, Mellanox Technologies | Speaker(s):
| | Session Description:
| Large storage systems require more complex connections than simple interfaces to achieve maximum efficiency and scalability. Designers want to share storage readily among multiple compute nodes and be able to perform clustering, failover, and other system-wide operations. They thus need networked storage rather than the traditional direct-attached variety. However, networked storage introduces new tradeoffs in terms of cost, complexity, speed, latency, and other factors. Flash storage makes design even more difficult because of its higher bandwidth and performance, thus placing more strain on switches and adapters. Many connection technologies exist, including Ethernet, Fibre Channel, PCI Express, and InfiniBand. Higher-speed versions are available, as well as lower-latency extensions such as Remote Direct Memory Access (RDMA) and iSCSI extensions for RDMA (iSER). Typical issues governing selection include familiarity with particular approaches, existing use, latency and performance requirements, scalability, ecosystem (including management tools), and cost.
| | About the Organizer/Moderator: | Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe
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Monday, August 7th
1:00-5:00pm | | Pre-Conference Seminar E: New Non-Volatile Memory Technologies (Pre-Conference Seminar Track 1 Track) | | Organizer + Chairperson + Instructor: Chuck Sobey, Chief Scientist, ChannelScience | Paper Presenters:
| | Session Description:
| NAND flash non-volatile memory (NVM) took over 30 years to emerge as a broad-based data storage alternative. But now that flash has established the path, we can expect other new NVM technologies to emerge more quickly. One key is matching each technology’s unique characteristics to applications that can benefit from them the most. This pre-conference tutorial introduces the most popular NVM technologies and explains their principles of operation, their pros and cons, and what new developments to expect. You’ll learn the fundamentals of phase change memory, 3D XPoint™, ReRAM, memristor, spin-transfer torque, and other emerging technologies, as well as how they fit into the current landscape. The knowledge you gain will help you to understand what it will take for any of these to replace flash or to take the lead in persistent memory computing and storage class memory (SCM)! Many new NVM technologies use sophisticated concepts from quantum physics. Your instructor, Chuck Sobey, is well-known for his ability to make difficult technological concepts clear and useful. You’ll be able to ask this veteran storage R&D consultant your most pressing questions and draw on his technical expertise and industry insight. Reliable, unbiased information is critical for making the right decisions! So don’t proceed (and spend a lot of development money) without a clear understanding of the fundamentals of these rapidly-evolving technologies, and where they can make the biggest impact for your company! Get an insider’s view into what’s happening in the industry and what you’re likely to see both near-term and long-term. New NVM Technologies is a great way to get up-to-date quickly and take maximum advantage of your attendance at the Flash Memory Summit. It is also an excellent stand-alone learning experience for those with limited time. Cut through the hype surrounding new NVM technologies! Conquer the fear and apprehension regarding what might replace flash technology! Learn how to ask the tough questions and know when you get the right answers for your application! This tutorial is designed for engineers, managers, and executives who need to make immediate decisions. It is presented by KnowledgeTek, the world’s leading data storage technology training company. Suggested prerequisites include a technical background and interest in data storage; this introductory class does not assume detailed engineering knowledge of chips, drives, non-volatile memory, or storage systems. Course Outline 1. NVM Overview • Memory vs. storage • Why do we need new NVM technologies? • NVM approaches: Magnetic, charge, phase, filamentary, bulk, etc. • Understanding the incumbent: The pros, cons, and future of NAND flash 2. Architectural Commonalities • Access devices • Cross point arrays • Multi-bit per cell approaches • 3D fabrication compatibility 3. Competing (or Co-Existing) Technologies • Phase change memory (PCM, PC-RAM) • 3D XPoint™ and QuantX™ • MRAM: Spin-transfer torque (STT-RAM) • ReRAM: Filamentary, interface, bulk, ion transport, memristor • MRAM: Spin-orbit torque (SOT-RAM) 4. System-level Considerations • Endurance and retention • Signal processing and error correction coding (ECC) • Speed, error rate, and power • Controller partitioning 5. Next Steps to Prepare for New NVM Technologies • Considerations for successful prototyping • Enabling neuromorphic computing • The device determines the system • What to watch for at the Summit! • Suggested sources of reference information
| | About the Organizer/Moderator: | Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque).As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there.Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara.
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Monday, August 7th
1:00-5:00pm | | Pre-Conference Seminar F: NVMe over Fabrics (Pre-Conference Seminar Track 2 Track) | | Organizer + Chairperson + Instructor: Hugh Curley, Consultant, HughCurley.com | Speaker(s):
| | Session Description:
| NVMe Management Interface allows users to perform much of the management “out-of-band” allowing management without interfering with the data path, or at a time the data path is unavailable. Most of the functions that can be done in-band, can also be done out-of-band, and vice versa. This course covers how the out-of-band management interface works. NVMe over Fabrics extends NVMe to large fabrics as opposed to the single-computer systems of PCIe. NVMe enables deployments with many SSDs using a network interconnect, such as RDMA over Ethernet or its competitors. Thanks to an optimized protocol stack, an end-to-end NVMe solution will reduce access latency and improve performance, particularly when paired with a low latency, high efficiency transport. Applications can then access SSDs rapidly, regardless of whether they are attached locally or accessed remotely across enterprise or data center networks. Course Outline: NVMe Management Interface Management Interface 1.0 and 1.1 Block Diagram MI, MCTP, SMBus Commands (Control Primitive, MI, Admin, PCIe) Basic Management Interface Read Drive Status Read Static Data Reset Arbitration bit NVMe over Fabrics Overview What are fabrics? What is mapping/binding? Why create NVMe over fabrics? What are the differences between Channel I/O and Memory I/O, and between messages and shared memory? RDMA What is RDMA? How RDMA operates Benefits of RDMA Zero Copy OS Bypass Detail of RDMA defined by IETF Reliable/Unreliable Connection/Datagram RDMA queue pairs with NVMe host and target Verbs RDMA operations InfiniBand InfiniBand is an interface ideally suited to handle SSDs and NVMe. It is used primarily in high performance computing, where the rapid transfer of large data files between computers or between computers and storage arrays is critical. To this end, InfiniBand was designed to use RDMA. Ethernet with iWARP or RoCE Ethernet is ubiquitous and high-speed, making it an ideal candidate for a transport protocol. However, Ethernet is not designed to use RDMA, so two competing protocols have been developed to add RDMA to it. This presentation will describe how they both work. Fibre Channel Fibre Channel is most often used to connect Storage Area Networks (SANs) in the enterprise market. Many of the required services for NVMe Over Fabrics Over FC already exist, e.g. Discovery (Name Server), Link Services, Process Login, and Error Recovery. However, Fibre Channel does not support RDMA.
| | About the Organizer/Moderator: | Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe.. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "Very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. The KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.
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Monday, August 7th
1:00-5:00pm | | Pre-Conference Seminar G: Using Machine Learning to Optimize Storage Systems (Pre-Conference Seminar Track 3 Track) | | Organizer + Instructor: Kiran Gunnam, Technical Director of Algorithms and DSP, Velodyne LiDAR | Speaker(s):
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| Today’s storage systems are very large and complex. They often consist of huge numbers of storage nodes of different types with different associated properties and costs. Optimization algorithms are also very complicated, and sample workloads are difficult to create. Furthermore, in the case of clouds, system administrators have no idea what the users are running or how workloads will vary in time. So how can we maximize system efficiency, that is, the cost/performance ratio? One way to get around the mentioned difficulties and limitations is to use machine learning techniques. Such methods measure how well the system is operating and improve by doing. That is, they learn much as a person does by practicing a task until he or she is expert in it. Machine learning is thus an alternative to implementing algorithms that may be difficult to determine and apply and not relevant to the situation at hand. Machine learning has been studied for a long time, and many approaches exist. For example, one can employ deep convolutional neural networks, which work like the human nervous system - reinforcing paths that lead to successful outcomes and downgrading those that do not. Other approaches include regularization, optimization algorithms, and practical methodology. Three case studies illustrate the incorporation of machine learning technology in developing storage systems. The first involves optimizing parameters for flash memories and SSDs to reduce data errors and predicting failures to provide reliable, high-performance data access. The second deals with classifier engines, programs that can take a set of declarations about a domain and infer further facts about it. The specific application involves classifying the properties of objects such as access patterns and lifetimes in an object storage system. The third case study focuses on recommendation engines, which suggest the best location or tier of storage anywhere in the world to help lower latency, improve performance or cut costs. The application is storage allocation in elastic storage systems.
| | About the Organizer/Moderator: | Dr. Kiran Gunnam is a technical director of algorithms and signal processing at Velodyne LiDAR, a developer of sensors for autonomous vehicles. He is leading the development of machine learning, simultaneous localization and mapping (SLAM), and signal processing algorithms and real-time hardware implementations for LiDAR sensor-based self-driving cars. Dr. Gunnam is both an innovative technology leader and an experienced developer of engineering seminars. He has made breakthrough technical contributions in advanced error correction systems, storage class memory systems, and vision based navigation systems. Dr. Gunnam has 70 issued patents and 100+ applications/invention disclosures on algorithms, computing, and storage systems. He is the lead inventor/sole inventor for 90% of them. His patented work has already been incorporated in more than 2 billion data storage and WiFi chips and is set to continue to be incorporated in more than 500 million chips per year. Dr. Gunnam has been an IEEE Distinguished Speaker and Plenary Speaker for lectures at 19 events and international conferences with more than 2,000 attendees worldwide. He also teaches graduate level courses focused on machine learning systems at Santa Clara University.
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Monday, August 7th
1:00-5:00pm | | Pre-Conference Seminar H: Flash Controller Design (Pre-Conference Seminar Track 4 Track) | | Organizer + Chairperson + Instructor: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate | Speaker(s):
| | Session Description:
| Flash controllers are complex systems that must handle a wide variety of effects and situations in solid state disks. They must implement properly the flash translation layer which converts system-level commands to instructions suited to the actual flash configuration. They must cope with wear, endurance, write amplification, and other issues. And they must be able to work with a variety of flash types and sizes to avoid getting into repeated design cycles. Error-correction techniques are still another issue with complex codes often being used to deal with failures in the underlying medium. FPGAs provide an obvious way to design initial versions and deal with low-volume situations. ASICs or market-standard chips can increase performance or reduce costs in many situations. Designs must also allow for later upgrades to lengthen their lifetimes.
| | About the Organizer/Moderator: | Dr. Erich F. Haratsch is Director of Engineering at Seagate Technology, where he is responsible for architecture development of performance, endurance, error correction and media management features in solid state disk controllers. Earlier in his career, Haratsch developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. Haratsch is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 US patents. He earned his MS and PhD degrees in electrical engineering from the Technical University of Munich (Germany).
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Monday, August 7th
1:00-1:45pm | | SNIA Tutorial #1: Understanding Real World Storage Workloads (Pre-Conference Seminar Track 5 Track) | | Session Sponsor: SNIA | | Organizer + Instructor: Eden Kim, CEO, Calypso Systems | Speaker(s):
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| The session will explain what Real World Workloads are, how they are captured and why they are important. Not limited to developers, the session will also bring a clear understanding of the value of Real World Storage Workloads to the IT community and Systems Integrators. The audience will receive the fundamental understanding of how and why Real World Storage Workloads are important in Datacenter storage, server and storage device design, optimization and qualification.
| | About the Organizer/Moderator: | Eden Kim is CEO of Calypso Systems, Inc., a leader in SSD test and measurement equipment and services. Eden is also Chair of the SNIA Solid State Storage Technical Working Group
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Monday, August 7th
1:50-2:45pm | | SNIA Tutorial #2-SAS-Today's Fast and Flexible Storage Fabric (Pre-Conference Seminar Track 5 Track) | | Session Sponsor: SNIA | | Organizer + Instructor: Jeremiah Tussey, Product Marketing Manager (Alliances), Scalable Storage Business Unit, Microsemi | Paper Presenters:
| SAS-Today's Fast and Flexible Storage Fabric
Jeremiah Tussey, Product Marketing Manager (Alliances), Scalable Storage Business Unit, Microsemi | Session Description:
| For storage professsionals seeking fast, flexible and reliable data access, Serial Attached SCSI (SAS) is the proven platform for innovation. With a robust roadmap, SAS provides superior enterprise-class system performance, connectivity and scalability. This presentation will discuss why SCSI continues to be the backbone of enterprise storage deployments and how it continues to rapidly evolve by adding new features, capabilities, and performance enhancements. It will include an up-to-the-minute recap of the latest additions to the SAS standard and roadmaps, the status of 12Gb/s SAS deployment, advanced connectivity solutions, MultiLink SAS™, and 24Gb/s SAS development. Presenters will also provide updates on new SCSI features such as Storage Intelligence and Zoned Block Commands (ZBC) for shingled magnetic recording.
| | About the Organizer/Moderator: | Jeremiah Tussey is the Alliance Marketing Manager for Microsemi’s Enterprise Storage and Communications Group, managing vendor alliances for SATA, SAS, PCIe, and NVMe products, as well as CPU-Platform and Operating System ecosystem enablement. He has over 18 years of experience in the storage industry, with focuses in Applications Engineering and Product Marketing for SCSI, SATA, PCIe, Fibre Channel, and Enclosure Management products. Jeremiah is the current Secretary of the SCSI Trade Association and current Treasurer of the Serial ATA International Organization. He received his bachelor’s in electrical engineering from the University of Colorado.
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Monday, August 7th
3:00-4:00pm | | SNIA Tutorial #3-A New Standard for IP Based Drive Management (Pre-Conference Seminar Track 5 Track) | | Session Sponsor: SNIA | | Organizer + Instructor: Mark Carlson, Principal Engineer, Industry Standards, Toshiba | Paper Presenters:
| A New Standard for IP Based Drive Management
Mark Carlson, Principal Engineer, Industry Standards, Toshiba | Session Description:
| As hyperscalers and enterprises building their own data centers disrupt the storage industry, new innovative connections to storage drives are emerging, including the use of IP based data path protocols. This talk will focus on a new standard from the SNIA called IP-Based Drive Management. Leveraging existing standards such as DMTF's Redfish, the standard allows for scalable management of individual drives numbering in the 10s of thousands in a typical datacenter.
| | About the Organizer/Moderator: | Mark A. Carlson, Principal Engineer, Industry Standards at Toshiba, has more than 35 years of experience with Networking and Storage development and more than 18 years experience with Java technology. Mark was one of the authors of the CDMI Cloud Storage standard. He has spoken at numerous industry forums and events. He is the co-chair of the SNIA Cloud Storage and Object Drive technical working groups, and serves as co-chair of the SNIA Technical Council.
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Monday, August 7th
4:00-5:00pm | | SNIA Tutorial #4- Innovations, Challenges, and Lessons Learned in HPC Storage (Pre-Conference Seminar Track 5 Track) | | Session Sponsor: SNIA | | Organizer + Instructor: Gary Grider, HPC Division Leader, Los Alamos National Laboratory | Paper Presenters:
| Innovations, Challenges, and Lessons Learned in HPC Storage
Gary Grider, HPC Division Leader, Los Alamos National Laboratory | Session Description:
| In this tutorial, we will introduce the audience to the lunatic fringe of extreme high-performance computing and its storage systems. The most difficult challenge in HPC storage is caused by millions (soon to be billions) of simultaneously writing threads. Although cloud providers handle workloads of comparable, or larger, aggregate scale, the HPC challenge is unique because the concurrent writers are modifying shared data. We will begin with a brief history of HPC computing covering the previous few decades, bringing us into the petaflop era which started in 2009. Then we will discuss the unique computational science in HPC so that the audience can understand the unavoidability of its unique storage challenges. We will then move into a discussion of archival storage and the hardware and software technologies needed to store today’s exabytes of data forever. From archive we will move into the parallel file systems of today and will end the lecture portion of the tutorial with a discussion of anticipated HPC storage systems of tomorrow. Of particular focus will be namespaces handling concurrent modifications to billions of entries as this is what we believe will be the largest challenge in the exascale era.
| | About the Organizer/Moderator: | Gary Grider is the Leader of the High-Performance Computing (HPC) Division at Los Alamos National Laboratory (LANL). He is responsible for all aspects of high performance computing technologies and deployment. He also manages the R&D portfolio for providing HPC solutions to the Lab through funding of university and industry partners. Additionally, he is the US Department of Energy Exascale Storage, IO, and Data Management National Co-Coordinator, helping manage US government investments in data management, mass storage, and I/O. Gary has 30 active patents or applications in the data storage area and has been working in HPC and HPC related storage for over 30 years. Gary earned BSEE and MBA degrees at Oklahoma State University and has presented at many events, including the OpenFabrics Workshop, Usenix HotStorage Workshop, Storage Developer Conference, and past Flash Memory Summits.
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