Monday, August 5th
Monday, August 5th
8:30-Noon
Pre-Conference Seminar A: Introduction to 3D NAND (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Chuck Sobey, Chief Scientist, ChannelScience

Session Description:
4-bits per cell (QLC) technology and the push for 128+ layers in 3D NAND flash continue to drive down the cost per gigabyte of solid-state storage. How do these developments affect the performance and reliability of storage systems? What is different about the NAND manufacturers’ technologies? How does 3D XPoint™ affect the flash market? If you are new to flash memory and want to get the most out of FMS, this seminar will get you up-to-speed quickly with the terms and concepts used in the industry. If you are an experienced storage professional, but are curious about the inner workings of flash and how they affect system design, this introduction will quickly give you the fundamentals of the critical aspects of flash The challenges and opportunities presented by increased storage density in 3D (or “vertical”) NAND flash are significant. A clear understanding of the structure and function of flash cells enables designers to get the most out of their systems. How is the changing role of the FTL (flash translation layer) in data center appliances changing how 3D NAND is being used, tested, and optimized? If more of the native NAND performance is exposed, what do you do with it? What can you expect to encounter when using 3D NAND in extreme environments like automotive, industrial, and IoT? How does the trend toward persistent memory affect flash usage? What are the consequences of the billions of dollars China is investing in 3D NAND manufacturing? This seminar is designed for engineers, managers, and executives who must make immediate decisions on implementing or optimizing 3D flash technology. Reliable, unbiased information is critical for making the right decisions! So don’t proceed (and spend a lot of development money) without a clear understanding of the fundamentals, opportunities, and challenges of this critical technology! This seminar is presented by KnowledgeTek, the world’s leading data storage technology training company. Suggested prerequisites include a technical background and an interest in 3D technology. The class does not assume detailed engineering knowledge of flash memory or semiconductor processing. Course Outline 1. The Fundamentals of 3D NAND ● 3D: What it is and what it isn’t ● Moore’s law ended for 2D NAND flash ● Charge trap flash cells ● Roadmaps for 3D NAND ● The device determines the system 2. Competing Technologies and Architectures for 3D Flash ● Vertical transistor designs ● 3D array architectures ● Accessing data ● SLC to TLC and QLC in 3D ● Comparison to MRAM, ReRAM, and other nonvolatile memories 3. Process, Design, and Test Challenges ● Etch and deposition vs. lithography ● Logical-to-physical translation in 3D ● Testing, characterization, and defects ● Controller partitioning 4. Next Steps in 3D ● Persistent memory ● Parameter setting with machine learning ● Will emerging NVMs replace flash? ● China’s flash initiatives ● Opportunities with 3D XPoint™ (QuantX™) ● A lesson from The Wrath of Khan ● What to watch for at the Summit!
Intended Audience:
Engineers, managers, and executives who must make immediate decisions implementing or optimizing 3D flash technology

About the Organizer/Chairperson:
Speaker Bio: Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer, as well as the General Chairperson of the Flash Memory Summit. He is the founder of the R&D services firm ChannelScience, which develops new capabilities in data storage. Currently, he is advising on such major trends as STT-MRAM, ReRAM, memory manufacturing in China, computational storage, 5G, AI/ML acceleration, and standards for personal AI agents. He has also provided strategic storage technology advice to government agencies worldwide. He has presented at many conferences, including Flash Memory Summit, and has given courses on storage-related topics around the world. He earned electrical and computer engineering degrees from Carnegie Mellon University and the University of California at Santa Barbara.

Monday, August 5th
8:30-Noon
Pre-Conference Seminar B: NVMe over Fabrics (NVMe-oF) (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Hugh Curley, Consultant, HughCurley.com

Session Description:
NVM Express (NVMe) is a specification for connecting non-volatile memory devices such as SSDs to computers via the PCIe bus. The idea is to take advantage of the high speed of PCIe (as compared to disk interfaces such as SAS or SATA), while maintaining full standardization and access to a large ecosystem. It has rapidly become a popular interface supported by almost all major SSD makers. Storage designers and end users alike appreciate its combination of low cost, high speed, widespread support, and standardized approach. NVMe started with a clean slate to build a command set and supporting mechanism that would take advantage of the PCIe transport and SSD storage devices. It is scalable from iPads to enterprise and high performance computing. At the Flash Memory Summit, many keynote presentations and breakout sessions assume a basic understanding of NVMe. Be prepared to take full advantage of the Summit by upgrading your background with this pre-conference presentation. This presentation assumes no specific knowledge of PCIe or NVMe, but does assume a general understanding of computers. Outline of Topics: Introduction to NVMe NVMe Operation and Structures Command and status Door bells Queues Interrupts Data flow Controller Memory Buffer Host Memory Buffer Admin Commands Create/Delete Submission/Completion Queues Set/Get Features DWord parameter passing Passing parameters in memory Identify Namespace Management and Attachment I/O Commands Command List Using RDMA NVMe 1.3 Enhancements New Commands Directive Send/Receive Device Self-test Sanitize NVMe-MI Send/Receive Doorbell Buffer Configuration Virtualization Management New Features Time Stamp Host Controller Thermal Management Non-Operational Power State Configuration New Registers Boot Partition Information Boot Partition Read Select Boot Partition Buffer Location New log pages are covered with the new command or feature NVMe 1.4 Enhancement (if released) IO Determinism
Intended Audience:
This seminar is designed for engineers, managers, and executives who need to make immediate decisions. It is presented by KnowledgeTek, the worldäó»s leading data storage technology training company. Suggested prerequisites include a technical background and interest in data storage; the class does not assume detailed engineering knowledge of any storage interface or storage systems.

About the Organizer/Chairperson:
Speaker Bio: Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.

Monday, August 5th
8:30-Noon
Pre-Conference Seminar C: Persistent Memory (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Bill Gervasi, Principal Systems Architect, Nantero

Presenter: Arthur Sainio, Director Product Marketing, SMART Modular Technologies

Presenter: Kumar Prabhat, Product Manager, NetApp

Session Description:
Persistent memory offers the cost and capacity advantages of storage devices at memory speed. It also brings opportunities for architecting software applications to utilize its new capabilities. Of course, the tradeoffs involved in using it are far from simple. NAND flash and other types of non-volatile memory behave quite differently from standard DRAM. Handling the differences requires new methods for system integration, programming, and management. Several solutions to the problems involved are currently in use, and several groups are proposing standards for both software and hardware. The obvious advantages of persistent memory indicate that designers will need to be aware of developments in this promising technology area. This seminar will provide an in-depth look into several leading technologies, current implementations, and applications that take advantage of persistent memory in compute and storage systems. Session PM-1: Introduction to Persistent Memory 8:30 -10:15 am Session PM-2 Current Implementations 10:30 - 12:00 noon
Intended Audience:
Hardware, firmware, and software architects, design engineers and engineering managers; storage engineers and managers; system analysts and engineers; CTOs; technical product planners and managers; product engineers; test engineers.

About the Organizer/Chairperson:
Speaker Bio: Bill Gervasi, Principal Systems Architect at Nantero, is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.

Speaker Bio: Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he leads efforts in new technologies such as persistent memory including MRAM and NVDIMMs. He has been a major promoter of persistent memory and NVDIMMs since they were first introduced. He has organized and presented sessions at Flash Memory Summit, Storage Developer Conference, and Persistent Memory Summit and has participated in many webinars and blogs. He is the co-chair of the Persistent Memory and NVDIMM Special Interest Group within SNIA/SSSI, which is focused on accelerating the awareness and adoption of persistent memory and creating new standards. Before joining SMART Modular, Arthur was a product marketing manager at Hitachi Semiconductor. Arthur earned an MBA from San Francisco State University and an MS from Arizona State University.

Speaker Bio: Kumar is a graduate of IIT Delhi and he has over 20 years of industry experience in flash memory, storage and infrastructure software space. Currently he is leading the product the product management efforts for NetApp MAX Data product. Previously he was Sr Director of Product with Plexistor, a persistent memory based software start up, Plexistor was acquired by NetApp. Prior to Pleistor, Kumar also worked with Cloudbyte, a software defined storage start up. Earlier in his career, he worked with leading Flash memory companies AMD, Spansion and SK Hynix. Kumar has also been entrepreneur and founded two software startups. He loves to travel and meet new people.

Monday, August 5th
1:00-5:00 PM
Pre-Conference Seminar E: NVMe/TCP (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Orit Wasserman, Principal Architect, Lightbits Labs

Presenter: Don Wake, Solutions Engineer, LightBits Labs

Presenter: Hugh Curley, Consultant, HughCurley.com

Session Description:
NVMe over Fabrics has quickly become a popular way to network flash memory, particularly with transports such as Fibre Channel, InfiniBand, and RoCE (RDMA over Converged Ethernet). However, the most popular networking fabric by far is the TCP used by standard Ethernet. Now NVMe/TCP provides access to this fabric, allowing data centers to combine what is now the standard SSD connection with the most popular network fabric. This is a winning combination because it is widely available and understood, offers very high bandwidth, and is inexpensive and easy to implement. Thanks to an optimized protocol stack, an end-to-end NVMe/TCP solution will reduce access latency and improve performance. Applications can then access SSDs rapidly, regardless of whether they are attached locally or accessed remotely across enterprise or data center networks. In the first half of this session, a tutorial covers NVMe over Fabrics, Ethernet with TCP, and NVMe over TCP. The second half is a hands-on tour of NVMe/TCP, the newest addition to the NVMe-oF family of standards and the first production-grade NVME/TCP-based software defined disaggregated storage solution, Lightbits LightOS. NVMe/TCP brings the power and speed of NVMe to TCP/IP networks and is already included in major Linux distributions. The audience will learn how NVMe/TCP works and how to connect to remote NVMe/TCP block devices and use them with applications. They will learn not just the theory of NVMe/TCP but also the practice of using it in a cloud data center. This is a hands-on session and attendees are expected to bring their own laptops. We will be using the Packet cloud environment for hands-on experimentation, bringing up Linux virtual machines that will use NVMe/TCP to connect to Lightbits LightOS servers in the Packet cloud.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Speaker Bio: Orit Wasserman is Principal Architect at Lightbits Labs and is an expert on NVMe/TCP, distributed systems, storage, open source and Ceph. In her previous role at Red Hat, Orit authored and co-maintained live migration for KVM/QEMU. Previously at IBM Research Labs she developed nested virtualization for KVM.

Speaker Bio: Don Wake is a Solutions Engineer at Lightbits Labs who’s passionate about building new technologies and guiding customers on their path towards a disaggregated approach to storage with NVMe/TCP. Don began working with network computing, storage and communications while serving in the United States Marine Corps. Since then, Don’s worn many hats as an engineer and in storage at HP, Sierra Logic/Emulex, Brocade, NetApp, QLogic, and Dell EMC-DSSD and now Lightbits Labs

Speaker Bio: Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.

Monday, August 5th
1:00-5:00 PM
Pre-Conference Seminar F: Flash Storage Networking (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Rob Davis, VP Storage Technology, Mellanox

Presenter: Alan Weckel, CEO/Founder, 650 Group

Presenter: Steve McQuerrey, Sr Technical Marketing Engineer, Pure Storage

Presenter: Brian Pan, General Manager, H3 Platform

Presenter: Rupin Mohan, Director R&D/Board Member, HPE / FCIA

Presenter: Abdel Sadek, Technical Marketing Engineer, NetApp

Presenter: Ilker Cebeli, Sr Director Product Planning, Samsung Semiconductor

Session Description:
Large storage systems require more complex connections than simple interfaces to achieve maximum efficiency and scalability. Designers want to share storage readily among multiple compute nodes and be able to perform clustering, failover, and other system-wide operations. They thus need networked storage rather than the traditional direct-attached variety. However, networked storage introduces new tradeoffs in terms of cost, complexity, speed, latency, and other factors. Flash storage makes design even more difficult because of its higher bandwidth and performance, thus placing more strain on switches and adapters. Many connection technologies exist, including Ethernet, Fibre Channel, PCI Express, and InfiniBand. Higher-speed versions are available, as well as lower-latency extensions such as Remote Direct Memory Access (RDMA) and iSCSI extensions for RDMA (iSER). Typical issues governing selection include familiarity with particular approaches, existing use, latency and performance requirements, scalability, ecosystem (including management tools), and cost.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts.

About the Organizer/Chairperson:
Speaker Bio: Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Speaker Bio: Alan Weckel is Technology Analyst/Co-Founder at 650 Group, where he is in charge of Ethernet switch research and new areas such as SDN forecasting and WAN optimization. He has written many articles for the trade and technical press, and is frequently quoted in such leading publications as Bloomberg, Businessweek, Forbes, Network World, and the Wall Street Journal. Before co-founding 650 Group, he was VP/analyst at Dell’Oro Group and had engineering and software development experience at Raytheon, General Electric Power Systems, and Cisco. He holds a BSEE and an MS in Management from Rensselaer Polytechnic Institute.

Speaker Bio: Steve McQuerry is a Sr. Technical Marketing Engineer on the platform team at Pure Storage. One of his areas of focus is helping customers understand the use cases and best practices for deploying NVMe-oF with FlashArray. Steve is a CCIE Emeritus (CCIE #6108) is a 20+ year data center veteran. For the last 16 years he has held both field and product positions for storage, networking, and compute OEMs. Steve has published multiple networking books and has been recognized as distinguished speaker at industry events. Steve holds a Bachelor of Science in Engineering Physics from Eastern Kentucky University.

Speaker Bio: Brian Pan is the founder/General Manager of H3 Platform, a leading cloud solution provider offering PCIe composable technology to cloud operators. H3 Platform’s customers include a tier 1 AI research laboratory in North America, the provider of the car hiring solution, and Tier 1 server vendors. Brian focuses on developing high-performance computing (HPC) applications that maximize the utilization of accelerators, interconnect, and storage. Before founding H3 Platform, Brian was Sales Director at Oracle Taiwan, ZyXEL, and QNAP. He earned a BSME degree from the National Cheng Kung University (Taiwan) and an MBA from the National Chengchi University (Taiwan).

Speaker Bio: Rupin Mohan is a Director of R&D and Chief Technologist of Storage Networking (SAN) at HPE Storage. Rupin leads a global engineering and product management teams responsible for development of Storage Networking products. Rupin has filed for 30+ patents at HPE. He is a Board Member of and Marketing Chairman for FCIA. Rupin completed his MBA from MIT Sloan School of Management as a Sloan Fellow. He also holds a MS in Engineering from Tufts University and BE in Computer Engineering from Delhi Institute of Technology.

Speaker Bio: Abdel Sadek has been in the storage industry for the past 16 years. Working on different projects with different partners on Interoperability of the NetApp E-Series storage systems with third party vendor components and established as a subject matter expert in NVMe over Fabrics implementation on E-Series. Recently transition to a Technical Marketing role focusing on high performance computing.

Speaker Bio: Ilker Cebeli is a Senior Director of Product Planning at Samsung where he focuses on Enterprise and Data Center SSD, NVMe-oF SSD, Emerging Memory, and All-Flash-Array Storage Software and Technologies. He has spent 25 years in a variety of roles within the data center computing, storage, networking and memory industry, and has been a key figure in developing strategy and establishing new product lines for data center-related technologies. Prior to joining to Samsung, Ilker worked at Micron, where he directed an advanced engineering team and led emerging memory projects in its Memory Division. Ilker also spent 15 years at Intel and he was responsible for Intel's Xeon™ product planning and server platform architecture definitions.

Monday, August 5th
1:00-5:00 PM
Pre-Conference Seminar G: Designing Flash Controllers (Pre-Conference Seminars Track)
Speaker(s):
Presenter: Oliver Hambrey, Research Engineer, Siglead

Presenter: Ahmed Hareedy, Postdoctoral Associate, Duke University

Presenter: Jeff Yang, Principal Engineer, Silicon Motion

Presenter: Radu Stoica, Researcher, IBM

Presenter: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Session Description:
Flash controllers are complex systems that must handle a wide variety of effects and situations in solid state disks. They must implement properly the flash translation layer which converts system-level commands to instructions suited to the actual flash configuration. They must cope with wear, endurance, write amplification, and other issues. And they must be able to work with a variety of flash types and sizes to avoid getting into repeated design cycles. Error-correction techniques are still another issue with complex codes often being used to deal with failures in the underlying medium. FPGAs provide an obvious way to design initial versions and deal with low-volume situations. ASICs or market-standard chips can increase performance or reduce costs in many situations. Designs must also allow for later upgrades to lengthen their lifetimes.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Speaker Bio: Oliver Hambrey is a research engineer at Siglead Europe Limited which he joined in 2010. He has a Master of Mathematics and MSc in Complexity Science degrees from the University of Warwick, UK which he obtained in 2007 and 2009 respectively. At Siglead Europe, he has worked on a variety of projects including the development of low complexity constrained coding algorithms, HDD magnetic read head quality estimation, detection techniques for two-dimensional magnetic recording, NAND flash characterization and the design of the spatially coupled BCH ECC engine used in Siglead’s SATAIII SSD controller.

Speaker Bio: Ahmed Hareedy is a postdoctoral associate in the Electrical and Computer Engineering Department at Duke University. He received his Bachelor and M.S. degrees in Electronics and Communications Engineering from Cairo University in 2006 and 2011, respectively. He received his Ph.D. degree in Electrical and Computer Engineering from the University of California, Los Angeles (UCLA) in 2018. Ahmed worked with Mentor Graphics Corporation between 2006 and 2014. He worked as an error correcting codes architect with Intel Corporation in the summer of 2015 and the summer of 2017. Ahmed is a recipient of the Best Paper Award from the IEEE Global Communications Conference (GLOBECOM), 2015. He won the 2016-2017 Electrical Engineering Henry Samueli Excellence in Teaching Award at UCLA. He is a recipient of the Memorable Paper Award from the Non-Volatile Memories Workshop (NVMW), 2018. He won the 2018-2019 Distinguished PhD Dissertation Award in Signals and Systems from the Electrical and Computer Engineering Department at UCLA.

Speaker Bio: Silicon Motion is a global leader and pioneer in developing NAND flash controller ICs for solid-state storage devices. We have the broadest portfolio of controller technologies and solutions and have shipped over five billion NAND controllers, more than any other company in the world. We are the world's leading merchant supplier of controllers for eMMC embedded memory used in smartphones and tablets, and the leading merchant supplier of controllers for client SSDs used in PCs and other applications. Our Shannon Systems enterprise-grade PCIe SSDs are targeted at the Chinese hyperscale data center market.

Speaker Bio: Radu Stoica is a Research Staff Member part of the Cloud and Computing Infrastructure at IBM Research Zurich. He is broadly interested in storage related topics, with an emphasis on storage class memories and cloud applications. His current work includes designing enterprise-grade flash controllers, developing data deduplication techniques, improving the efficiency of strongly consistent distributed databases and leveraging in-memory distributed filesystems as accelerators. Before joining IBM, he completed his Ph.D. at EPFL working in the DIAS group under the supervision of Prof. Anastasia Ailamaki. His thesis focused on adapting traditional relational database systems to take full advantage of new storage hardware such as flash memory.

Speaker Bio: Roman Pletka is a research staff member for cloud storage and security at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He has published 20 articles and obtained over 50 patents in security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over ten years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).

Tuesday, August 6th
Tuesday, August 6th
8:30-7:00 PM
FMS Persistent Memory Programming Hackathon (Persistent Memory Track)
Organizer + Chairperson: JIm Fister, Principal, The Decision Place

Paper Presenters:
Session Description:
The FMS Persistent Memory Programming Hackathon will provide a better understanding of how of how to use existing APIs to program persistent memory, as well as where it might benefit further research and development. Open Persistent Memory Hackathon drop-in sessions will run Tuesday August 6 and Wednesday August 7 from 8:00 am – 7:00 pm in the Great America Ballroom Foyer. Attendees will develop sample code based on open-source PM found in the Linux Kernel, PMDK.io and other interfaces. Following the Wednesday open Hackathon session, all are invited to a Persistent Memory Meetup from 7:00 – 8:30 pm in Great America Ballroom A to demonstrate the code they have developed.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Coming soon..

Tuesday, August 6th
8:30-9:35 AM
EMBD-101-A-1: Embedded Applications, Part 1 - Drive Design (Embedded Applications Track)
Organizer: Tom McCormick, Chief Engineer/Technologist, Swissbit

Chairperson: Bill Wong, Sr Content Director/Editor, Electronic Design Magazine

Paper Presenters:
Enhancing TLC Flash Designs for Embedded Applications
Thomas McCormick, Chief Engineer/Technologist, Swissbit

Impact of the Usage models on the Storage devices definition
Ivan Ivanov, Distinguished Engineer, CoC Systems, Harman

BGA SSDs Lead the Way in Embedded Applications
Chris Lien, Senior Manager, ATP Electronics Taiwan

Designing Reliable Flash Storage Systems
Axel Mehnert, VP of Marketing & Strategy, Hyperstone

Session Description:
Flash storage is becoming important factor for both consumers and in the enterprises. Benefits of flash storage are many, but much higher cost of flash storage as compared to traditional storage is making it hard to justify financially buying of the flash storage. What many storage customers don?t necessarily realized that price per megabyte or gigabyte of capacity is outdated model and it does not represent true cost of storage. Many enterprise consumers of storage keep buying more and more hard drives, not to satisfy capacity requirement, but to satisfy performance requirement, but when total cost of ownership is taken into consideration, flash storage becomes very competitive with much smaller footprint, cooling and power requirements. There are also certain workloads, which can benefit tremendously from using flash storage and those will be discussed in this presentation.
Intended Audience:
Embedded systems designers including hardware and software designers, engineering managers, system analysts, product designers, product engineers, and marketing managers.

About the Organizer/Chairperson:
Tom McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development and full life cycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory product research and development.. His ongoing research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications. He has presented at Flash Memory Summit and the Non-Volatile Memory Workshop, and has published an article on embedded flash in EE Times. He holds a PhD in Computer Engineering from Northeastern University, an MBA and an MS in Computing Engineering from the University of Massachusetts at Lowell, and an MSME and BSME (summa cum laude) from Drexel University.

Bill Wong is an Embedded/Systems/Software Technology Editor at Electronic Design Magazine. He writes several columns, including the popular Lab Bench, alt.embedded, and Bill’s Workbench hands-on column. He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the technology industry for almost 40 years, including over 15 years with Electronic Design. He is a frequent conference participant as a speaker, chairperson, and organizer, including at the Embedded Systems Conference. He holds a BSEE from Georgia Tech and a Master’s in computer science from Rutgers.

Tuesday, August 6th
8:30-9:35 AM
FTEC-101A-1: Annual Update on Flash Technology (Flash Technology Track)
Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Chairperson: Xinde Hu, Principal Engineer, Western Digital

Paper Presenters:
Annual Update on Flash Technology
, ,

Session Description:
Is NAND flash at a crossroads? Is the end of scaling near? How is 3D flash doing? Are the reported production problems real and how important are they? What?s the real story with 3D XPoint? In practice, NAND flash technology keeps advancing with manufacturers reporting successful products at ever-smaller dimensions. 3-D flash is in production, as the transition continues. Flash memory remains the dominant non-volatile memory technology near term, and the 3D developments mean it will retain that status for years to come.
Intended Audience:
Flash users including design engineers, engineering managers, system engineers, CTOs, embedded system designers, and system analysts; product planners, marketers, and engineers who want to know more about whatäó»s happening in flash technology.

About the Organizer/Chairperson:
Leah Schoeb is a Sr. Developer Relations Manager in the platform architecture team at AMD, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, with the last decade in solid state technology. She is also the Founding Data Architect at Data Glass, where she assists systems companies with performance engineering and optimization, market positioning, and benchmarking. She was previously Acting Director Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as the Industry Trends Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC), and Storage Networking Industry Association (SNIA). She is a member of the SNIA Technical Council and a co-founder of their Solid State Storage System Technical Work Group. She earned an MBA at the University of Phoenix and a BSEE at the University of Maryland, College Park.

Xinde Hu is currently Director of System Architecture @eSSD at Western Digital. His responsibility includes creating, designing, and evaluating innovative system architecture concepts and implementations for the next generations of non-volatile memory based storage systems. Before joining Western Digital, Dr. Hu held architectural leader positions in STEC and STMicroelectronics. Dr. Hu has authored more than a dozen technical papers on data storage systems and has 38 patents issued. He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.

Speaker Bio: Jim Handy is President of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy writes the Chip Talk blog for Forbes online and contributes to two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Tuesday, August 6th
8:30-9:35 AM
INVT-101A-1: Gen-Z: The Best Interface for Emerging Memory Technologies (Enterprise Storage Track)
Chairperson: Kim Parnell, President, Parnell Engineering and Consulting

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Gen-Z: The Best Interface for Emerging Memory Technologies
Valerie Padilla, Technology Strategist, Server CTO, Dell EMC

Session Description:
Most processor-memory interfaces assume a fixed type of volatile memory (usually DRAM). Other variations (such as static memory or ROM) require special interface hardware to operate on the memory bus. Gen-Z is a new data access fabric that abstracts the memory media, breaking the processor-memory interlock and allowing for a variety of memory types and operations. Memory may be persistent (that is, act like very fast storage), and operations may occur in it (that is, memory-centric or in-memory computing). Multiple paths may allow for multiple channels or protect against faults. With Gen-Z, new memory types can provide a wide range of functions for advanced applications without any need to slow down the memory bus or change its basic architecture. Memory and processors can now follow separate and independent innovation paths, increasing the capabilities of computers to handle new applications involving big data, real-time analytics, AI/ML, and edge computing.
Intended Audience:
Hardware design engineers and managers, system engineers and managers, engineering managers/CTOs, product planners, and interface specialists

About the Organizer/Chairperson:
Dr. Kim Parnell is a consultant and Expert Witness for litigation, providing services through Parnell Engineering & Consulting (PEC). He holds a Stanford PhD and MSME in Mechanical Engineering, a BES from Georgia Tech, and is a Registered Professional Mechanical Engineer in California. Kim often consults on high-tech patents in litigation or before the PTAB using his direct experience with reliability, failure and forensic investigation involving devices such as consumer products and cellular telephones including battery failures/fires. He frequently consults on medical devices in terms of patents or design issues, and he has supported an early-stage company on venture funding of LDPC Technology for Flash Memory applications. Parnell is an ASME Fellow, an IEEE Senior Member, a member of ASM International (the Materials Information Society) and of SAE (Society of Automotive Engineers). He is Past Chair of the IEEE-SCV (Santa Clara Valley) Section, and is a current Board Member and Past Chair of the IEEE-CNSV (Consultants' Network of Silicon Valley) - and IEEE-CNSV has a booth on the show floor. Kim taught full-time in the Mechanical Engineering Department at Santa Clara Univ., and also taught graduate level courses at Stanford University.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Valerie Padilla is a Technology Strategist in the Office of the Server CTO at Dell EMC where she evaluates emerging technologies, designs conceptual architectures, and performs strategic studies. She is currently laser focused on memory-centric and composable architectures, collaborating with vendors in evaluating fabric technologies such as PCIe, NVMe-oF, and Gen-Z. She is also strongly interested in software-defined storage and open-source projects such as Ceph. She has over 10 years experience with Dell as a performance, system, and software engineer. Valerie earned a BSEE from the University of Texas at Austin.

Tuesday, August 6th
8:30-10:50 AM
ARCH-101-1: Open-Channel SSDs for Host-Based Optimization (Architectures Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
Use of Open-Channel SSDs in Chinese Datacenters
Wei Xu, Technical Support Manager, Shannon Systems

A Global FTL Architecture to Drive Multiple SSDs
Roy Shterman, Senior Solutions Architect, LightBits Labs

Open-Channel SSDs for Host-Based Optimization
Sheng Qiu, Staff Engineer, Alibaba

An Advanced Error Recovery Scheme for Open-Channel SSDs
Jeff Yang, Principal Engineer, Silicon Motion

The Denali Open-Channel Standard: Its Impact and Its Future
Javier Gonzalez, Principal Software Engineer, Samsung

Session Description:
There are currently several alternative approaches to the handling of detailed SSD operations such as the placement of data and the timing of garbage collection. The standard approach has been to embed the details inside the Flash Translation Layer (FTL). The driver then only has to perform straightforward input and output operations. However, hyperscale operators want to be able to control everything from the system software in the interests of obtaining more efficient operations and minimizing latency. I/O determinism and the open-channel SSD offer the higher flexibility at the cost of more complex system software. Both paradigms make sense in different markets with clouds and other hyperscale operators preferring greater control while smaller data centers prefer the simpler interface. This session will focus on Open-Channel SSDs, which are able to reduce write amplification and improve QoS and NAND utilization in both data centers and enterprise solutions. However, various proprietary specifications have created some chaos in the industry as vendors are forced to support the same feature set on different (and incompatible) specification versions. This session will include Denali, the first industry effort to generate a standard Open-Channel specification as supported by Microsoft and a wide range of vendors and users.
Intended Audience:
Hardware and Software Design Architects, Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Product Managers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, and Data Center Architects.

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 6th
8:30-10:50 AM
AUTO-101-1: Tomorrow's Auto Safety/Security Requirements (Automotive Applications Track)
Chairperson: Alan Messer, Chief Strategy & Technology Officer, InnovationShift

Organizer: Andy Marken, President, Marken Communications

Paper Presenters:
The Storage/Management Challenges of the Autonomous Transportation Ecosystem
Alan Messer, Chief Strategy & Technology Officer, InnovationShift

Requirements for Fail-Safe Automotive Storage Solutions with Secure NOR Flash
Sandeep Krishnegowda, Marketing Director, Flash Business Unit, Cypress Semiconductor

The Role of Secure Flash Memory in Automotive Applications
Anthony Le, Vice president of marketing, Macronix America

Autonomous Vehicles: Direction, Growth, and Challenges
Andrew Wygle, Embedded Software Engineer specializing in data programming of Flash devices., Data I/O

Tomorrow's Data Storage Integrity and Safety for Autonomous Cars
Bernd Niedermeier, Sales Director Automotive, Europe, Tuxera

Session Description:
The primary motivating forces for getting humans from behind the steering wheel of tomorrow’s vehicle is to reduce, if not eliminate, the approximately 1.3 million deaths on the world’s highways/byways today; reduce the volume of vehicles on the road; and significantly reduce vehicles’ environmental impact . Fast, reliable in-vehicle and ecosystem communications/data storage will be a key component in meeting that goal. Data in tomorrow’s vehicles must be 100 percent reliable, available and instantly provided to the various decision-making systems in the new moving environment. How will we design, develop and use storage redundancy, “soft fail” solutions that can protect passengers and those around them as well securely handle the constant flow of accurate information and vehicle upgrades/enhancements while the vehicle is in motion.
Intended Audience:
Automotive system designers, hardware and software designers, engineering managers, system engineers and analysts, product and product marketing engineers, computer and communications specialists.

About the Organizer/Chairperson:
Alan Messer is Chief Strategy and Technology Officer with consulting company Innovation Shift. He has been a worldwide leader in advanced software and intelligent services for connected consumers for over 20 years. Alan was formerly VP Software and Innovation and CTO of Global Connected Consumer eXperience at General Motors where he led work on products, platforms, and future technologies for the Connected Car and Services. Before General Motors, Alan was VP Advanced Software Technology at Samsung Electronics covering Internet of Things, Intelligence, Privacy, Mobile Social/Media, Content Delivery, and Cloud Services. Alan has also worked at HP, Sony Electronics, and startups. He has served several industry organizations in advisory and board roles as well as working with analysts/media.

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Tuesday, August 6th
8:30-10:50 AM
CHNA-101-1: Flash Growth & Opportunity in China (China Track)
Organizer + Chairperson: Jerome Luo, President, Sage Microelectronics

Paper Presenters:
Flash and NVM Technology Enabling AIoT
Michael Wang, VP, GigaDevice Semiconductor

Flash Evolution Demands Controller Innovations
David Wu, CEO, YeeStor Microelectronics

Balanced and Optimized Block Storage in the Tencent Cloud
Allen Liu, Solution Architect, Tencent Cloud

Ethernet SSD (NVMe over Ethernet)
Hailuan Liu, R&D director, Hangzhou Dianzi University

The Future of RRAM: From Embedded Application to In Memory Computing and Beyond
Jianguo Yang, Associate Professor, Institute of Microelectronics of the Chinese Academy of Sciences

Session Description:
China is today a major player in both using and developing flash products. Those working at organizations outside China need to understand what is happening currently at Chinese companies, universities, and other organizations. The Chinese market offers many potential opportunities for products, services, and collaboration. Interests range throughout the non-volatile memory area, including development of new technologies, enterprise storage, embedded applications, and hyperscale datacenters.
Intended Audience:
Corporate executives, sales executives, marketing professionals, business development specialists, analysts, investors, engineering managers and directors, product planners, product and product marketing managers, and any flash industry participants interested in working in or learning more about China

About the Organizer/Chairperson:
Jianjun (Jerome) Luo is the founder and president of Sage Microelectronics, a provider of ICs and solutions for digital storage and data security applications (including SSD controllers) with offices in both Silicon Valley and Hangzhou, China. Jerome is also a Professor and Director of the Microelectronic Research Institute at Hangzhou Dianzi University. Jerome helped organize the first flash memory conference held in China (the China Flash Forum held in Beijing on October 23, 2014). He has been an ASIC design engineer and Director of R&D at Initio and has designed more than 10 ASICs. He earned a PhD in semiconductor technology from Zhejiang University, a Master’s in Microelectronics from the Hangzhou Institute of Electronics Engineering, and a Bachelor’s in Electronics Engineering from Shanghai Jiaotong University.

Tuesday, August 6th
8:30-10:50 AM
ENAP-101-1: Enterprise Applications, Part 1 (Enterprise Applications Track)
Organizer + Chairperson: Tom Burniece, President, Burniece Consulting Services

Paper Presenters:
Accelerating NVMe Adoption With Enterprise Storage-as-a-Service
Marc Leavitt, Sr. Director, Product Marketing, Zadara

IBM Storage: A Lighthouse for the Data-Driven Multicloud World
Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Multi-Site Collaboration Across Flash and Cloud with a Global Namespace
David Flynn, CEO, Hammerspace

Tipping Point: The Next Revolution for Compute and Storage
Steve Sicola, Founder & CEO, StorTrek Consulting

Session Description:
Flash memory has revolutionized storage system and computing architectures for many enterprise applications. Actual case studies from innovative storage companies, including descriptions of the problem, approach, and results, provide examples of practical situations. Applications will include SQL and NoSQL databases, OLTP, data warehousing, big data analytics, Hadoop/MapReduce, financial transactions, and in-memory computing. Customers will co-present with some speakers.
Intended Audience:
Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Storage Managers, Network Engineers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, Application Administrators, Database Administrators, Application Developers, and Data Center Architects

About the Organizer/Chairperson:
Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Tuesday, August 6th
8:30-10:50 AM
PMEM-101-1: Persistent Memory Part 1: Advances in Persistent Memory (Persistent Memory Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Chairperson: Dave Eggleston, Principal, Intuitive Cognition Consulting

Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Paper Presenters:
State of the Union-Persistent Memory Today and Tomorrow
Jim Pappas, Director, Technology Initiatives, Intel

Current Status and Overview of Standards Related to Persistent Memory
Jonathan Hinkle, Principal Researcher, Lenovo

Deploying Persistent Memory and Acceleration via Compute Express Link
Stephen Bates, CTO, Eideticom

An Overview of New and Emerging Media
Dave Eggleston, Principal, Intuitive Cognition Consulting

FPGA-Attached Persistent Memory Accelerates Applications Cost-Effectively
, ,

STT-MRAM, a High Performance Complement to Flash Memory
Tom Andre, Vice President of Engineering, Everspin Technologies

Session Description:
Persistent memory offers fast, byte-addressable access to data that persists! No more waiting endlessly for accesses to load data into memory or doing task switches to find something that can make progress during the wait. Obviously, the advance should mean huge speedups for applications that can’t currently keep data in memory, such as database, big-data analytics, and hyper-converged platforms. It is already proving to be great for accelerating applications such as MSFT SQL, VDI, high-availability storage, and others. But what about the software? It is currently all written and optimized to still copy data from memory to storage. Architects, developers, end user adopters, and vendors of today’s persistent memory must understand what development tools, platforms, management tools, and applications are currently available or in-progress to harness this new development in their systems.
Intended Audience:
Hardware Design Engineers, Engineering Managers, CTOs, Storage Engineers, System Engineers and Managers, Software Engineers, Product Planners and Engineers, IT Managers, HPC Engineers and Managers, Large-Scale System Designers

About the Organizer/Chairperson:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Tuesday, August 6th
9:45-10:50 AM
BMKT-101B-1: Annual Update on Flash Arrays (Business/Marketing Track)
Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Paper Presenters:
Session Description:
Flash arrays contain multiple SSDs, replacing traditional hard drives. They may be either all-flash with no hard drives at all or hybrids with both types of drives. They are currently very popular in data centers as a packaged solution that provides fast access at a reasonable price. They can do everything a disk array can do (and much faster), although SSDs usually have lower capacities than hard drives.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Coming soon..

Tuesday, August 6th
9:45-10:50 AM
DPRO-101B-1: Data Recovery of SSDs (Data Protection Track)
Organizer: Troy Hegr, Sr. Manager Global BD, Ontrack Data Recovery

Chairperson: Krishna Chander, Principal Analyst, Chander Consulting

Paper Presenters:
The Past and Current State of Mobile Device Data Recovery
Steve Hruska, Senior Hardware R&D Engineer, Ontrack Data Recovery

Erasure verification on flash memory-Is the data really gone?
Will DeLisi, NAND Flash Recovery Specialist, DriveSavers Data Recovery

Josey Santana, Data Recovery Engineer, DriveSavers Data Recovery
The Use Of Encryption For Sanitization: A Case Study
Robin England, Hardware Research & Development Team Lead, Ontrack Data Recovery

Intra-disk RAID for Extreme Data Recovery
Cristian Zambelli, Assistant Professsor, University of Ferrara (Italy)

Session Description:
SSDs are very reliable data storage devices. But when something goes amiss, users need to know what considerations should be taken into account to access and protect your organization's sensitive data? How is inaccessible data recovered from SSDs? Are SSDs designed to make finding lost data easier? When should one engage a data recovery specialist? How do you ensure your sensitive data is securely erased and sanitized from an SSD at the end of its useful life? Data recovery experts, digital forensic specialists, and SSD manufacturers will discuss the technology and science behind data recovery and data sanitization from flash based storage. If you've ever experienced data loss, want to know how to effectively plan and be prepared in the event of data loss, or need to know who the experts are and what they do, this is a must-attend session!. Attendees will gain an in-depth understanding of the effort involved in restoring lost data from an SSD, and how to ensure sensitive data is protected and erased when an SSD is at the end of its useful life or needs to be repurposed for alternate uses.
Intended Audience:
System engineers and managers; IT managers; storage engineers and managers; recovery specialists

About the Organizer/Chairperson:
Troy Hegr is a Sr. Manager at Ontrack, the world leader in data recovery, data erasure, and data protection. Mr. Hegr helps facilitate discussion and fosters partnerships in the technical community with leading data storage and computer system designers, SSD manufacturers and industry groups. Mr. Hegr benefits from over 25 years of experience in the data recovery and digital forensics industries and has been a Flash Memory Summit CAB member, session organizer, and presenter for several years. Mr. Hegr is based in the Tampa Bay, Fl. area and has an Electronics Technician degree from DeVry Institute of Technology and holds a certification in project management from the University of Minnesota, Carlson School of Management.

Krishna Chander is the Principal Analyst at Chander Consulting, where he focuses on storage systems marketing and analysis. He was previously a Senior Storage Analyst at iSuppli. He also has extensive experiences at IBM and Hitachi in storage systems analysis, thin film manufacturing, product development, and market positioning. He has an MS in Chemical Engineering from Lehigh University and an MBA from SUNY-Binghamton.

Tuesday, August 6th
9:45-10:50 AM
EMBD-101B-1: Embedded Applications, Part 2 - Examples (Embedded Applications Track)
Organizer: Tom McCormick, Chief Engineer/Technologist, Swissbit

Chairperson: Bill Wong, Sr Content Director/Editor, Electronic Design Magazine

Paper Presenters:
Smart Storage Design for Edge Computing in Industrial IoT
Chanson Lin, Founder/CEO, EmBestor Technology

The Role of Smart SSDs in the Artificial Intelligence of Things (AIoT)
Color Cheng, Senior Product Manager, Innodisk

Using SSD Performance Numbers Effectively
Jan Peter Berns, Managing Director, Hyperstone

Session Description:
Embedded systems have long used flash memory to support highly diverse system features and functionality under a wide range of operating conditions. In recent years, cost pressures from consumer applications have reduced the performance characteristics of the most widely available flash memory devices and have strained their ability to meet the more stringent reliability requirements of embedded applications. Embedded flash must have special characteristics to meet industrial, mil/aero, and other applications? needs in areas such as temperature, pressure, operating lifetime, shock, vibration, EMI, RFI, and radiation exposure.
Intended Audience:
Embedded systems designers including hardware and software designers, engineering managers, system analysts, product designers, product engineers, and marketing managers.

About the Organizer/Chairperson:
Tom McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development and full life cycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory product research and development.. His ongoing research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications. He has presented at Flash Memory Summit and the Non-Volatile Memory Workshop, and has published an article on embedded flash in EE Times. He holds a PhD in Computer Engineering from Northeastern University, an MBA and an MS in Computing Engineering from the University of Massachusetts at Lowell, and an MSME and BSME (summa cum laude) from Drexel University.

Bill Wong is an Embedded/Systems/Software Technology Editor at Electronic Design Magazine. He writes several columns, including the popular Lab Bench, alt.embedded, and Bill’s Workbench hands-on column. He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the technology industry for almost 40 years, including over 15 years with Electronic Design. He is a frequent conference participant as a speaker, chairperson, and organizer, including at the Embedded Systems Conference. He holds a BSEE from Georgia Tech and a Master’s in computer science from Rutgers.

Tuesday, August 6th
9:45-10:50 AM
ENST-101B-1: Annual Update on Enterprise Flash Storage (Enterprise Storage Track)
Chairperson: Rohit Gupta, Segment Manager, Enterprise Storage Solutions, Western Digital

Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:
Session Description:
Enterprise flash storage continues to advance from being a faster plug-in replacement for disk drives to being a storage layer on its own. The original SSD conception obviously allowed storage designers to use the mature hardware and software ecosystem available for HDDs, adding only the Flash Translation Layer to make the necessary adjustments. However, this approach still left SSDs with all the disadvantages of disk storage including its complexity and low speed. NVMe has now brought a standardized high-speed parallel interface to solid-state storage, allowing it to act as a high performance tier in all-flash arrays, and now allowing it to be readily networked through the new NVMe Over Fabrics (NVMe-oF) standard. The world of NVMe-oF expanded rapidly this year from ultra-low latency JBODs to high-performance, low latency arrays with a full set of data services. Even more improvement is on the way, as we begin to treat solid-state storage as memory rather than as a peculiar form of disk drive. This advance will bring great change as in-memory databases become both truly all in memory and as persistent as traditional DBMSes. Low latency RDMA networks, which are also used by NVMe-oF, will allow an application to use memory semantics to write into another system?s non-volatile memory address space. This session will examine the development of these technologies into products enterprises can deploy, and the applications such products can best address. We?ll also look into our murky crystal ball a little and predict what users can expect to see over the next 2 - 3 years.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Coming soon..

Leah Schoeb is an independent master technologist focused on system-level problems ranging from cloud infrastructure and virtualization to system and data infrastructure performance. She has over 25 years experience in helping systems companies with performance engineering and optimization, market positioning, benchmark evidence creation, and guiding industry standards development for system, virtualization, containerized, and data solutions. She has served in leadership roles for performance architecture for a wide variety of major companies, including Rubrik, VMware, Sun Microsystems, Dell, Intel, and Amdahl. She has also been a Managing Partner at the analyst firm Evaluator Group and an active participant in standards work for the Storage Networking Industry association (SNIA) and the Transaction Processing Council (TPC). She earned a BSEE from the University of Maryland and an MBA from the University of Phoenix. She is a member of the Flash Memory Summit’s Conference Advisory Board and the organizer of the Annual Update series of presentations.

Speaker Bio: Howard Marks has been writing, speaking, and consulting about enterprise technology for over thirty years. As a consultant, he has designed storage, server, and network infrastructures for organizations such as The State University of New York (Purchase), BBDO Worldwide, and the Foxwoods Resort Casino. He also operates an independent laboratory (DeepStorage) which tests storage products for both vendors and magazines. He started testing and reviewing products at PC Magazine in the late 1980s and has written hundreds of articles and product reviews for such media as Network World, Network Computing, and InformationWeek. A top rated speaker at industry events, he has spoken at Storage Decisions, Interop, and Microsoft’s TechEd. He has also developed training programs for organizations such as JP Morgan and American Express.

Tuesday, August 6th
9:45-10:50 AM
INVT-101B-1: Achieving Lowest-Latency Storage with NVMe (NVMe Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Kim Parnell, President, Parnell Engineering and Consulting

Paper Presenters:
Achieving Lowest-Latency Storage with NVMe
Josh Goldenhar, VP Product Marketing, LightBits Labs

Motti Beck, Director Enterprise Market Develop, Mellanox

Session Description:
Low-latency storage is critical for a wide variety of applications, including transaction processing, financial trading systems, and video transmission. NVMe provides extremely low latency (single-digit microseconds) when used locally. How can we extend this level across networked flash which may experience both network delays and congestion? The solution is to provide software that pools NVMe storage access across the network at local speeds and latencies. The software must be distributed and support a variety of fabrics and architectures. It must also offer negligible overhead and application-independent operation. The result is NVMe sharing that scales performance and capacity linearly - and provides the low latency that today's applications require.
Intended Audience:
Storage engineers and managers, hardware design engineers and managers, data center engineers and managers, product planners, system engineers and managers

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Dr. Kim Parnell is a consultant and Expert Witness for litigation, providing services through Parnell Engineering & Consulting (PEC). He holds a Stanford PhD and MSME in Mechanical Engineering, a BES from Georgia Tech, and is a Registered Professional Mechanical Engineer in California. Kim often consults on high-tech patents in litigation or before the PTAB using his direct experience with reliability, failure and forensic investigation involving devices such as consumer products and cellular telephones including battery failures/fires. He frequently consults on medical devices in terms of patents or design issues, and he has supported an early-stage company on venture funding of LDPC Technology for Flash Memory applications. Parnell is an ASME Fellow, an IEEE Senior Member, a member of ASM International (the Materials Information Society) and of SAE (Society of Automotive Engineers). He is Past Chair of the IEEE-SCV (Santa Clara Valley) Section, and is a current Board Member and Past Chair of the IEEE-CNSV (Consultants' Network of Silicon Valley) - and IEEE-CNSV has a booth on the show floor. Kim taught full-time in the Mechanical Engineering Department at Santa Clara Univ., and also taught graduate level courses at Stanford University.

Coming soon..

Speaker Bio: Josh Goldenhar is VP Products at Excelero, a leading provider of software-defined storage. He is responsible for defining, promoting, and steering the company’s high-performance, scalable block storage solution. Before joining Excelero, he led product strategy and management at EMC (XtremIO) and at DataDirect Networks. He has over 20 years experience in the technology industry. He earned a Bachelor’s degree in Cognitive Science from the University of California, San Diego. He is often interviewed in the trade and technical press and has presented at webinars and at events, including the International Conference on Massive Storage Systems and Technologies (MSST).

Tuesday, August 6th
9:45-10:50 AM
NVME-101B-1: Zoned Namespaces Overview/Endurance Group Management (NVMe Track)
Session Sponsor: NVM Express
Organizer: Cameron Brett, Director SSD Product Marketing, Kioxia

Chairperson: Paul Suhler, Storage Architect, Micron Technology

Paper Presenters:
Handling Sequential Write Workloads in Mixed NVMe/Hard Drive Systems
Dave Landsman, Director Industry Standards, Western Digital

Endurance Group Management: Host control of SSD media organization
Mark Carlson, Principal Engineer, Industry Standards, Kioxia

Paul Suhler, Storage Architect, Micron Technology

Session Description:
The NVMe Zoned Namespaces (ZNS) interface, which is being developed in the NVM Express workgroup, will be introduced. By dividing an NVMe namespace into zones, which are required to be sequentially written, ZNS offers essential benefits to hyper-scale organizations, all-flash array vendors and large storage-system vendors wishing to take advantage of storage devices optimized for sequential write workloads. ZNS reduces device-side write amplification, over-provisioning and DRAM, while improving tail latency, throughput and drive capacity. Also, by bringing a zoned-block interface to NVMe SSDs, ZNS brings alignment with the ZAC/ZBC host model already being used by SMR HDDs, and enables a zoned-block storage layer to emerge across the SSD/HDD ecosystem. SSD customers can have different requirements for the organization of the media in a drive: one large pool of capacity, separate sub-drives with performance isolation (I/O determinism), or one large pool plus a small pool capable of higher-performance writes. By allowing the host to configure a drive’s media in the field, a single SSD model can satisfy very different use cases. NVMe Endurance Group Management provides a mechanism for media to be configured into Endurance Groups and NVM Sets. This presentation will explain various use cases and how the mechanism is used to configure not just SSD media but also storage array components.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

Paul Suhler is a storage architect in SSD engineering at Micron Technology, where he is responsible for NVMe interfaces and for educating internal teams as well as customers. He is Micron's primary representative to the NVMe Technical Work Group to which he has contributed many proposals. He is also active in the SFF Technical Work Group, having chaired working groups on the U.3 specification, Ethernet drive connectors, and Ethernet speed negotiation. He has worked in the data storage industry for over twenty years at companies including HGST, Quantum, Seagate, and Adaptec. He has also been a member of the research faculty at the University of Southern California. He received the INCITS Technical Excellence Award, and is a Senior Member of IEEE. He holds a PhD and BS in computer engineering from the University of Texas at Austin, and an MS in computer engineering from the University of California, Berkeley. He is the author of papers and journal articles on parallel computing.

Tuesday, August 6th
9:45-10:50 AM
TEST-101B-1: The Straight Truth: How Today's Storage Performs on Real Workloads (Testing Track)
Chairperson: Jathin Ullal, Infrastructure Architect, Saygo

Organizer: Dennis Martin, Sr Analyst, Principled Technologies

Paper Presenters:
The Straight Truth: How Today's Storage Devices Perform on Realistic Workloads
Dennis Martin, Sr Analyst, Principled Technologies

Session Description:
Everyone (designers, marketers, salespeople, executives, and customers) wants to know how flash storage really performs. And they want to know it from an independent source using real-world applications. Principled Technologies will report on vendor-neutral performance tests run on database and virtualization workloads typical of today's data centers. The tests cover systems from several manufacturers, using a variety of form factors and interfaces and including both block and file protocols. Attendees will get good estimates of what to expect in practice, since the tests are independent and focus on current applications and environments. This session will also discuss recent advances such as NVMe over Fabrics (NVMe-oF), 3D XPoint performance, and high-speed interfaces such as 100 GbE and 32Gb Fibre Channel. Vendors will learn how their products shape up and where they should put their efforts.
Intended Audience:
Storage managers, storage engineers, data center managers and engineers, system architects, CTOs and CIOs, product planners, product managers and marketing engineers, design engineers, test engineers, performance analysts, and sales and marketing managers and executives

About the Organizer/Chairperson:
Jathin Ullal is a Global Product Line Manager at HPE, where he collaborates with customers and identifies their needs to translate them into successful products. He was previously an Infrastructure Architect at Saygo, where he was responsible for the design, deployment, and support of a hybrid cloud infrastructure covering over 80 cloud and IT offerings across legacy IT, private, public, and managed cloud. Before Saygo, he set up and led marketing and engineering teams at both venture-funded startups and large companies. He has held leadership positions at HP, Cisco, and Nortel, including being in charge of the design, deployment, and support of the networking, security, and management infrastructure for 15 SaaS applications hosted in 24 global data centers. Widely regarded as an expert in cloud computing and SaaS, he has presented at many conferences and led sessions and seminars. He holds an MSEE from the University of New Mexico.

Dennis Martin is a Senior Analyst at Principled Technologies, where he focuses on validation and performance testing of data center products. He was previously the founder and President of the analyst firm Demartek (acquired by Principled Technologies). Principled Technologies has its own fully equipped, modern test lab with the servers, networking, and storage gear found in today’s data centers. Its widely recognized reports cover products and technologies from both well-known vendors and startups, including Broadcom, Cisco, Dell EMC, HPE, IBM, Intel, NetApp, Pure Storage, Samsung, Seagate, Toshiba, and Western Digital. Principled Technologies also produces popular industry references, including its “Storage Interface Comparison” covering every interface used by storage systems and its “SSD Deployment Guide” that explains everything you need to know to deploy flash-based storage systems in the datacenter. Dennis’ commentary “NVMe over Fabrics Rules of Thumb” is a must-read for those designing storage systems that will take advantage of NVMe devices with multiple network adapters for network fabrics. Dennis is frequently quoted in the press (in such outlets as TechTarget, Market Watch, and Street Insider) on such topics as best practices for deploying SSD technologies and analyzing performance claims for all-flash arrays. A 39-year veteran of the technology industry, Dennis was previously a Senior Analyst with Evaluator Group and a marketing and engineering executive with StorageTek.

Speaker Bio: Dennis Martin is a Senior Analyst at Principled Technologies, where he focuses on validation and performance testing of data center products. He was previously the founder and President of the analyst firm Demartek (acquired by Principled Technologies). Principled Technologies has its own fully equipped, modern test lab with the servers, networking, and storage gear found in today’s data centers. Its widely recognized reports cover products and technologies from both well-known vendors and startups, including Broadcom, Cisco, Dell EMC, HPE, IBM, Intel, NetApp, Pure Storage, Samsung, Seagate, Toshiba, and Western Digital. Principled Technologies also produces popular industry references, including its “Storage Interface Comparison” covering every interface used by storage systems and its “SSD Deployment Guide” that explains everything you need to know to deploy flash-based storage systems in the datacenter. Dennis’ commentary “NVMe over Fabrics Rules of Thumb” is a must-read for those designing storage systems that will take advantage of NVMe devices with multiple network adapters for network fabrics. Dennis is frequently quoted in the press (in such outlets as TechTarget, Market Watch, and Street Insider) on such topics as best practices for deploying SSD technologies and analyzing performance claims for all-flash arrays. A 39-year veteran of the technology industry, Dennis was previously a Senior Analyst with Evaluator Group and a marketing and engineering executive with StorageTek.

Tuesday, August 6th
3:40-4:45 PM
AUTO-102A-1: Autonomous Vehicles - The Storage Challenges of Edge Computing (Automotive Applications Track)
Chairperson: Alan Messer, Chief Strategy & Technology Officer, InnovationShift

Organizer: Andy Marken, President, Marken Communications

Paper Presenters:
Cross Temperature of NAND Flash Storage in Automotive Applications
Crystal Chang, Senior Manager, ATP Electronics

Memory Requirements for Edge Computing in IoT applications
Nabil Damouny, Chief Strategist, Autonomous Edge

Providing Next-Generation Autonomy with PCIe Fabrics and Shared Storage
Wesley Yung, Principal Applications Engineer, Microchip

Network Drives Are the Next (R)evolution of Automotive Storage
Noam Mizrahi, VP Technology, CTO Office, Marvell

Session Description:
With transportation edge computing takes on a new meaning. Will data volumes of data have to be stored/used close to the decision point or will only a minimum of data be required while the majority of data be captured, processed, used discarded. How much storage will be needed in tomorrow’s vehicle and how much will be required in the ecosystem. Find out the design requirements – size, performance, security, privacy - for the next level of edge computing storage in a mobile environment. Or miss the bus and watch the taillights of your storage opportunities disappear over the hill.
Intended Audience:
Automotive system designers, hardware and software designers, engineering managers, system engineers and analysts, product and product marketing engineers, computer and communications specialists.

About the Organizer/Chairperson:
Alan Messer is Chief Strategy and Technology Officer with consulting company Innovation Shift. He has been a worldwide leader in advanced software and intelligent services for connected consumers for over 20 years. Alan was formerly VP Software and Innovation and CTO of Global Connected Consumer eXperience at General Motors where he led work on products, platforms, and future technologies for the Connected Car and Services. Before General Motors, Alan was VP Advanced Software Technology at Samsung Electronics covering Internet of Things, Intelligence, Privacy, Mobile Social/Media, Content Delivery, and Cloud Services. Alan has also worked at HP, Sony Electronics, and startups. He has served several industry organizations in advisory and board roles as well as working with analysts/media.

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Tuesday, August 6th
3:40-4:45 PM
BMKT-102A-1: Know What the Flash Customer Wants and Needs (Business/Marketing Track)
Chairperson: Dave Raffo, Editorial Director, TechTarget

Organizer: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Chadd Kenney, VP Products and Solutions, Pure Storage

Panelist: Ken Steinhardt, Field CTO, Infinidat

Panelist: Walt Hinton, CMO, Pavilion Data Systems

Panelist: Marc Staimer, President, Dragon Slayer Consulting

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Session Description:
Tech Target will present the latest 2019 research including IT purchase trends/growth/emerging techs/drivers and how broader infrastructure changes impact flash spending across the board. Tech Target will also include some best practices for marketing and sales leaders on topic alignment, best performing content etc. Following presentation is a Panel Session.
Intended Audience:
CMOs, VP Marketing, Marketing Directors and Managers, Product Marketing Specialists, Sales Representatives and Managers, Business Development Executives, MarCom and PR Specialists, Product Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Financial Analysts and Executives, Venture Capitalists, Media Representatives, Channel Marketing Managers, Distributors, VARs, System Integrators, and Solution Providers.

About the Organizer/Chairperson:
Dave Raffo is Executive News Director for Storage at TechTarget. He joined TechTarget in 2007 after spending three-and-a-half years covering storage for Byte and Switch. As executive news director of the Storage Group, he leads TechTarget’s news coverage of storage, data protection and hyper-convergence for SearchStorage,SearchDataBackup, SearchConvergedInfrastructure and SearchDisasterRecovery. Dave also worked as managing editor of EdTech Magazine, as features and new products editor at Windows Magazine, and technology editor at eLearning company WatchIT. Before turning to technology, he was an editor and sports reporter for United Press International in New York for 12 years. A New Jersey native, Dave currently lives in northern Virginia.

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Tuesday, August 6th
3:40-4:45 PM
CHNA-102A-1: Nonvolatile Memory Technology in China Today (China Track)
Organizer + Chairperson: Jerome Luo, President, Sage Microelectronics

Panel Members:
Panelist: Chris Tsu, CEO, Sage Microelectronics

Panelist: Jianguo Yang, Associate Professor, Institute of Microelectronics of the Chinese Academy of Sciences

Panelist: Michael Wang, VP, GigaDevice Semiconductor

Panelist: Rizwan Ahmed, Head of Product, Western Digital

Session Description:
Panelists from major companies and institutions in China will discuss the current state-of-the-art of nonvolatile memory reserach and development.
Intended Audience:
Engineers, executives, and analysts interested in the latest NVM technologies under research and development in China.

About the Organizer/Chairperson:
Jianjun (Jerome) Luo is the founder and president of Sage Microelectronics, a provider of ICs and solutions for digital storage and data security applications (including SSD controllers) with offices in both Silicon Valley and Hangzhou, China. Jerome is also a Professor and Director of the Microelectronic Research Institute at Hangzhou Dianzi University. Jerome helped organize the first flash memory conference held in China (the China Flash Forum held in Beijing on October 23, 2014). He has been an ASIC design engineer and Director of R&D at Initio and has designed more than 10 ASICs. He earned a PhD in semiconductor technology from Zhejiang University, a Master’s in Microelectronics from the Hangzhou Institute of Electronics Engineering, and a Bachelor’s in Electronics Engineering from Shanghai Jiaotong University.

Tuesday, August 6th
3:40-4:45: PM
CMOB-102A-1: 5G Broadband & the Onslaught of Local Data (Consumer/Mobile Applications Track)
Chairperson: Matt Eastwood, SVP, Enterprise Infrastructure and Datacenter, IDC

Organizer: Chuck Sobey, Chief Scientist, ChannelScience

Panel Members:
Panelist: Balaji Ethirajulu, Senior Director of Strategy and Product Marketing, Ericcson

Speaker: Russell Ruben, Director of Marketing for Automotive Solutions, Western Digital

Panelist: Danny Tseng, Staff Manager, Technical Marketing, Qualcomm

Speaker: Danny Tseng, Staff Manager, Technical Marketing, Qualcomm

Session Description:
5G is coming to town. Its wide broadband throughput is like connecting a gigantic mile wide pipe to every home, business, smartphone, and tablet. 5G requires large local stores and local processing with low latency (below 1 ms). Different stakeholders have different needs for additional local storage and processing as a result of 5G becoming widely available. Attention moves from clouds to local devices and from remote processing to local processing with an increasing emphasis on very low latency. 5G will support many new applications with AI being pushed out to the edge as well.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Matt Eastwood is Senior Vice President of IDC's Infrastructure, Cloud, Developer and Partnering research groups. He leads a team of analysts responsible for identifying and analyzing people, process and technology trends affecting the deployment and management of edge infrastructure, enterprise datacenters and clouds worldwide. He speaks frequently at IDC, industry, and user events around the world and is frequently quoted in leading business and technology publications. He received bachelor and master's degrees in civil engineering from Northeastern University and Worcester Polytechnic Institute respectively.

Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer, as well as the General Chairperson of the Flash Memory Summit. He is the founder of the R&D services firm ChannelScience, which develops new capabilities in data storage. Currently, he is advising on such major trends as STT-MRAM, ReRAM, memory manufacturing in China, computational storage, 5G, AI/ML acceleration, and standards for personal AI agents. He has also provided strategic storage technology advice to government agencies worldwide. He has presented at many conferences, including Flash Memory Summit, and has given courses on storage-related topics around the world. He earned electrical and computer engineering degrees from Carnegie Mellon University and the University of California at Santa Barbara.

Tuesday, August 6th
3:40-4:45 PM
CTRL-102A-1: Annual Update on Flash Controllers (Controllers Track)
Chairperson: Mike McKean, Director, Encore Semi

Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:
Session Description:
The development of high-speed, well-designed, and low-cost controllers has been a key factor leading to wider use of flash memory. Controllers must account for flash's special features, as well as providing error correction, wear management, and high availability. The controller market has also been in a state of flux with new entrants constantly appearing while old stalwarts are acquired or lose their technical edge. The big news in the last year has been the rapid emergence of NVMe controllers, which appear ready to dominate the market. There has also been interest in higher-speed and lower-latency controllers and in ones that can be managed more precisely (via I/O determinism) and networked efficiently.
Intended Audience:
Design engineers and engineering managers who want to keep up with developments in flash controllers; product planners, marketers, and engineers who want to know more about whatäó»s happening with controllers, especially those interested in the emerging NVMe (and NVMe-oF) technology as well as in designs intended for hyperscale users

About the Organizer/Chairperson:
Mike McKean is currently Director of Sales at Encore Semi, a design services firm focused on ASIC and firmware/software design and development. At Encore Semi, he leverages his ASIC and firmware background to grow key accounts and support projects with technical skills. He is currently leading firmware development for projects using multiple SSD controller architectures. Before joining Encore, Mike was VP Product Solutions at cybersecurity startup FHOOSH and General Manager for the Colorado Design Center of Synapse Design Automation. At Synapse, Mike led the successful execution of multiple HDD, SDD, and consumer electronics projects. He has 30 years experience in the semiconductor and systems industries. Mike is a regular presenter, chairperson, and organizer at Flash Memory Summit. He earned an MBA from the University of Texas at Austin and a BS in Engineering Science from Trinity University (TX).

Leah Schoeb is a Sr. Developer Relations Manager in the platform architecture team at AMD, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, with the last decade in solid state technology. She is also the Founding Data Architect at Data Glass, where she assists systems companies with performance engineering and optimization, market positioning, and benchmarking. She was previously Acting Director Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as the Industry Trends Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC), and Storage Networking Industry Association (SNIA). She is a member of the SNIA Technical Council and a co-founder of their Solid State Storage System Technical Work Group. She earned an MBA at the University of Phoenix and a BSEE at the University of Maryland, College Park.

Speaker Bio: David McIntyre is Principal Consultant at DS McIntyre Consulting, where he focuses on machine learning solutions, as well as programmable logic and GPU applications in the data center. He previously led the compute and storage business for Altera (now part of Intel). He has also held leadership positions at IBM, Fairchild, and startup Transmeta where he marketed and led the development of comprehensive product portfolios for high performance computing, enterprise networking, and enterprise storage. He earned MSEE and BSEE degrees at Ohio University and an MBA at San Jose State University. David is a regular speaker at networking and data center infrastructure conferences, including Flash Memory Summit.

Tuesday, August 6th
3:40-4:45 PM
ENST-102A-1: Enterprise Storage Design (Enterprise Storage Track)
Organizer: Camberley Bates, Managing Director/Analyst, Evaluator Group

Organizer: Jean Bozman, President, Cloud Architects

Chairperson: Molly Presley, VP Marketing, Qumulo

Paper Presenters:
Dramatically Increasing Filesystem Performance with Flash
John Kim, Director Storage Marketing, NVIDIA

Advancing NVMe-oF Adoption Based on Practical Experience
VR Satish, CTO, Pavilion Data Systems

Using Storage Class Memory to Accelerate All Flash Storage - Lessons Learned
Stephen Daniel, Distinguished Technologist, HPE / SPC

Session Description:
Enterprise storage today must adapt to new requirements in the data center. Although cloud computing, analytics, deep learning, and big data have received the most attention recently, server and desktop virtualization, data tiering, efficient architectures, and implementation of data policies still must be further addressed. As the number of applications and users keeps increasing, the need for rapid, predictable, and intelligent access to data becomes more important. Solid state storage is a key technology in meeting higher demand and providing faster access to data at reasonable cost. However, managers must understand which flash technology to adopt and how to make price/performance tradeoffs. New physical architectures, new technologies, and new approaches to long-existing issues such as caching and distributed systems must all be leveraged to optimize enterprise storage and its solutions.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Camberley Bates is Managing Director/Analyst at Evaluator Group, a leading analyst firm covering IT infrastructure and services. She has dedicated Evaluator Group to delivering unbiased in-depth research on information management and data storage - and helping customers use that research to develop the infrastructure they need. She is responsible for corporate leadership and coverage of go-to-market and channel strategies. She has over 20 years of executive experience leading sales and marketing teams at VERITAS, GE-Access, EDS, and IBM. Her achievements include developing a new market category at Copan Systems, restructuring channel programs at Veritas, and growing a new division of GE Access from $14 million to $500 million in revenue through a solution-practice methodology. Camberley is a frequent panelist and chairperson at such events as Interop and Flash Memory Summit, as well as being frequently quoted in the trade and technical press. She holds a BS degree in International Business from California State University Long Beach and executive certificates from Wellesley and Wharton School of Business.

Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

Molly Presley runs Product Marketing at Qumulo. Throughout her career, Molly has been responsible for understanding the challenges users are looking to solve, and building product and go-to-market strategies to help them. She has broad experience in data-driven markets including enterprise IT, autonomous vehicles, life sciences, video surveillance, and HPC. Prior to joining Qumulo, Molly was responsible for a combination of product marketing and product management at Quantum and DDN. She also founded the Active Archive Alliance and has spent several years on the Storage Networking Industry Association (SNIA) board of directors.

Tuesday, August 6th
3:40-4:45 PM
INVT-102A-1: Key-Value Store and NVMe Deliver Close to DRAM Performance (Enterprise Storage Track)
Chairperson: Mark Seligman, Principal, InPredict

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Key-Value Store and NVMe Deliver Close to DRAM Performance
Nikolas Ioannou, Research Staff, IBM Research

Session Description:
Many applications require low-latency data store services, a requirement typically satisfied using key-value stores backed by DRAM. However, large amounts of DRAM are very expensive. Also, recently introduced storage devices built on novel NVM technologies offer far higher performance than conventional SSDs. uDepot is a new key-value store built bottom-up to deliver the performance of fast NVM block-based devices. It is crafted carefully to avoid inefficiencies, uses a two-level indexing structure that adjusts its footprint dynamically to match the inserted items, and employs a novel task-based I/O runtime system to maximize performance. As an embedded store, uDepot's performance nearly matches the raw performance of fast NVM devices for both throughput and latency, while being scalable across multiple devices and cores. Using the popular Memcache protocol, it can deliver performance to network clients that is very close to DRAM-based systems. It offers much higher caching capacities at dramatically reduced cost in dollars per gigabyte. A uDepot-based memcache service is currently available as an experimental service in the IBM cloud.
Intended Audience:
Hardware design engineers and managers, storage engineers and managers, system engineers and managers, product planners, engineering managers and CTOs

About the Organizer/Chairperson:
Mark Seligman has over 20 years of experience in the development of compiler back-ends for high-performance chip and system vendors, as well as application tuning for GPUs and multicore processors (CPUs). He has over ten years of experience in computational statistics and workflow acceleration for scientific applications, and is a member of IEEE-CNSV which has a booth on the show floor. As a consultant with InPredict, Mark's projects include smoothing the transition from a working prototype or in-house solution to a scalable, high-performance application. He offers refactoring and rescaling services, as well as consultation, to facilitate redeployment, and he specializes in parallelization, whether across a cloud implementation or within a GPU. Mark can also tailor applications to run in embedded environments and SOCs.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Nikolas Ioannou is a Research Staff Member at IBM Research Zurich, where he works on nonvolatile storage, distributed file systems, data reduction algorithms for distributed storage, and systems aspects of machine learning frameworks. He is currently working on the uDepot data store optimized for NVMe storage, acceleration of machine learning systems, and the Snap ML library which provides high-speed training of popular machine learning models. He holds over 50 granted patents and patent applications and has authored articles in journals such as the ACM Transactions on Storage and the IBM Journal on Research and Development and presentations at many major conferences including Usenix Conference on File and Storage Technologies (FAST) and IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS). He has also presented at past Flash Memory Summits. He earned his PhD in computer science from the University of Edinburgh (UK).

Tuesday, August 6th
3:40-4:45 PM
NVME-102A-1: NVMe-MI Overview & New Developments/NVMe-oF What's New in 1.1 (NVMe Track)
Session Sponsor: NVM Express
Chairperson: Peter Onufryk, Fellow Data Center Solutions BU, Intel

Organizer: Cameron Brett, Director SSD Product Marketing, Kioxia

Paper Presenters:
The NVM Express Management Interface: Overview & New Developments
Austin Bolen, Sr Principal Engineer, Dell

Myron Loewen, Platform Architect in NVM Solutions Group, Intel
NVMe Over Fabrics: What's NEW in Version 1.1
David Black, Distinguished Engineer, Dell EMC

Fred Knight, , NetApp
Sagi Grimberg, , Lightbits Labs

Session Description:
The NVM Express Management Interface (NVMe-MI) specification defines a standardized framework for managing NVMe storage devices and enclosures. The specification defines an architecture, command set, and out-of-band transport mapping used by NVMe hosts or management controllers to manage NVMe elements. This presentation provides an introduction to the NVMe-MI 1.1 specification and an overview of new items being standardized for NVMe-MI 1.2. NVMe over Fabrics 1.1 is the latest version of the NVMe over Fabrics standard that accompanies the NVMe 1.4 standard. This combination introduces important new fabrics functionality such as the NVMe-oF/TCP transport and ANA (Asymmetric Namespace Access) Multipathing. Come hear about all the new fabrics functionality and how it’s likely to be used from three key authors of these standards.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and product marketing managers, interface specialists, system engineers and managers, and marketing managers

About the Organizer/Chairperson:
Peter Onufryk has been very active in NVMe standardization as an NVMe Board Member and NVMe Management Workgroup Chair. He has been a featured speaker at many events on NVMe and NVMe-MI, including Flash Memory Summit. He holds over 40 patents in interfaces and communications and has written several published articles. He was previously Director of Engineering at Integrated Device Technology (IDT) and a research staff member at AT&T Bell Labs. He earned a PhD in electrical and computer engineering from Rutgers University and an MSEE from Purdue University.

Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

Tuesday, August 6th
3:40-4:45 PM
SECU-102A-1: Plugging Holes in Storage Security (Security Track)
Organizer: Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Chairperson: Paul Suhler, Storage Architect, Micron Technology

Organizer: Mike McKean, Director, Encore Semi

Paper Presenters:
Advanced Countermeasures: Integrating SSDs Into Cyber-Security Defense
Sebastien Jean, Director of System Architecture, Phison Electronics

Physical Chip-ID based Encryption and Security in SSD Controller
Hiroshi Watanabe, Professor, National Chiao Tung University

The End of Opal 2.0 and SED SSDs?
Shing Lee, R&D Senior Manager, ADATA Technology

Session Description:
This session will explore issues and challenges in securing data on flash memory devices and systems. It will pose related issues and opportunities and will discuss how technologies and market trends are impacting deployment of such systems in large government and private organizations. Topics covered will include self-encrypting storage, standards, secure erasure and elimination, encryption, trusted storage, embedded and industrial computing applications, and security for flash drives, SSDs, and industrial devices.
Intended Audience:
Security and Infosec Specialists, Officers, and Engineers; Storage Managers and Engineers Mobile Technology Managers; Network and Data Center Directors, Managers, and Engineers; Enterprise Storage System Designers; Enterprise Flash and SSD Product Managers and Marketing Engineers; Large-Scale Systems Designers, Investors and Analysts

About the Organizer/Chairperson:
Bob Thibadeau is Chairman and CEO of the Drive Trust Alliance (DTA). Previously he was Chief Technologist for Seagate Technology and the originator of the Trusted Computing Group’s Self-Encrypting Drive (SED) Technologies. Currently the DTA has developed “Auto Erase” key management technology for SEDs in Automotive and other system IoT situations where SEDs are physically distributed in the IoT system (drivetrust.com/auto-erase). Previously, he headed projects in Robotics at Carnegie Mellon University for the major Automotive OEMs which resulted in nearly universal adoption of his inventions.

Paul Suhler is a storage architect in SSD engineering at Micron Technology, where he is responsible for NVMe interfaces and for educating internal teams as well as customers. He is Micron's primary representative to the NVMe Technical Work Group to which he has contributed many proposals. He is also active in the SFF Technical Work Group, having chaired working groups on the U.3 specification, Ethernet drive connectors, and Ethernet speed negotiation. He has worked in the data storage industry for over twenty years at companies including HGST, Quantum, Seagate, and Adaptec. He has also been a member of the research faculty at the University of Southern California. He received the INCITS Technical Excellence Award, and is a Senior Member of IEEE. He holds a PhD and BS in computer engineering from the University of Texas at Austin, and an MS in computer engineering from the University of California, Berkeley. He is the author of papers and journal articles on parallel computing.

Mike McKean is currently Director of Sales at Encore Semi, a design services firm focused on ASIC and firmware/software design and development. At Encore Semi, he leverages his ASIC and firmware background to grow key accounts and support projects with technical skills. He is currently leading firmware development for projects using multiple SSD controller architectures. Before joining Encore, Mike was VP Product Solutions at cybersecurity startup FHOOSH and General Manager for the Colorado Design Center of Synapse Design Automation. At Synapse, Mike led the successful execution of multiple HDD, SDD, and consumer electronics projects. He has 30 years experience in the semiconductor and systems industries. Mike is a regular presenter, chairperson, and organizer at Flash Memory Summit. He earned an MBA from the University of Texas at Austin and a BS in Engineering Science from Trinity University (TX).

Tuesday, August 6th
3:40-6:00 PM
ARCH-102-1: NVMe Zoned Namespaces for Improved Performance and Scalability (Architectures Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
Benefits of ZNS in Datacenter Storage Systems
Woo Suk Chung, Storage Software Team Lead, SK hynix

NVMe Zoned Namespaces in Practice
Matias Bjorling, Director of Emerging System Architectures, Western Digital

Fast Integration and Furious Performance with Zoned Flash Drives
Robert Lercari, VP Engineering, Radian Memory Systems

SPDK Flash Translation Layer Library for Zoned Namespace SSDs
Wojciech Malikowski, Software Engineer, Intel Technology Poland

Session Description:
Zoned Namespace (ZNS) SSDs are proposed for inclusion in the next NVMe specification. These will enable scalable storage architectures with a better TCO by shifting the main FTL functions to the host. This standards-based approach will enable host-side data placement to coalesce data writes at the application level, rather than at the individual SSD device level. ZNS SSDs will have improved management of data reads in concert with write operations for improved storage bandwidth performance, reduced write amplification, and efficient garbage collection. This architectural approach to large-scale storage repositories has further TCO benefits by allowing for the dramatic reduction DRAM used in SSDs, along with a reduction in NAND overprovisioning.
Intended Audience:
Hardware and Software Design Architects, Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Product Managers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, and Data Center Architects.

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 6th
3:40-6:00 PM
PMEM-102-1: Persistent Memory Part 2: Software and Applications (Persistent Memory Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Chairperson: Jeff Chang, VP Marketing, AgigA Tech

Chairperson: Arthur Sainio, Director Product Marketing, SMART Modular Technologies

Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Presenters:
Impact on Application Development - NVM Programming Model in the Real World
Andy Rudoff, Enterprise Storage Architect, Intel

Persistent Memory Applications and Technologies
Mark Webb, President, MKW Ventures

Providing Native Support for Byte-Addressable Persistent Memory in Golang
Pratap Subrahmanyam, Fellow, VMware

Applying Persistent Memory to Neuromorphic Computing
Darryl Koivisto, Chief Technology Officer, Mirabilis Design

Session Description:
Persistent Memory is READY. Industry standards are established, products are shipping (with more to come), platform support is available and multiple operating systems have native PM support. This enables new capabilities for a broad array of applications. Databases can now work faster and rebuild with little downtime. Run more virtual machines on the same core footprint. Accelerate cloud computing by removing file system overhead with direct persistent load/store semantics. Learn more about the latest software and application advances that have been enabled by the adoption of Persistent Memory, and see what others are doing to accelerate their application performance.
Intended Audience:
Hardware Design Engineers, Engineering Managers, CTOs, Storage Engineers, System Engineers and Managers, Software Engineers, Product Planners and Engineers, IT Managers, HPC Engineers and Managers, Large-Scale System Designers

About the Organizer/Chairperson:
Jeff Chang is VP Sales/Marketing at AgigA Tech, a pioneer in NVDIMM technology. He is responsible for product strategy, definition, and rollout as well as customer and partner relationships. He has also focused on the promotion and evangelization of NVDIMM technology to the industry at-large through conference appearances, articles in the trade and technical press, webinars, and webcasts. Jeff is co-chair of the NVDIMM Special Interest Group (SIG) within SNIA/SSSI. Before joining AgigA Tech, he held executive management and marketing positions at Entropic Communications, Staccato Communications, and Cypress Semiconductor. Mr. Chang has built and managed successful product portfolios spanning multiple end user markets including personal computing, consumer electronics, mobile handsets, enterprise systems, and operator-class communication systems. He earned a BSEE from the University of Washington.

Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he leads efforts in new technologies such as NVDIMMs. He has been instrumental in making SMART a leader in embedded applications of solid state storage over the last 20 years. He has promoted NVDIMMs through conference appearances, articles in the trade and technical press, webinars and webcasts, and organization of an NVDIMM Special Interest Group within SNIA/SSSI (where he serves as co-chair). He has been a frequent organizer, speaker, and moderator at SNIA events, Flash Memory Summit, and the In-Memory Computing Summit. Arthur earned an MBA from San Francisco State University and an MS from Arizona State University.

Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Tuesday, August 6th
3:40-6:00 PM
SSDS-102-1: Enterprise SSDs (SSDs Track)
Organizer + Chairperson: Mike Gluck, Principal, Gluck Enterprises

Paper Presenters:
The New Storage Tier between High-Performance SSDs and HDDs
Kent Smith, Enterprise SSD Manager, Micron

How to Detect and Handle SD and SSD Media Failures
Thom Denholm, Technical Product Manager, Datalight

Overcoming the Reductions in NAND Endurance Ratings
JB Baker, Senior Director of Product Management, ScaleFlux

Applying Blockchain to SSD Supply Chain Traceability
Michelle Lam, , IBM

Using Universal Backplane Management (SFF-TA-1005) to enable Tri-Mode Backplanes
Jeff Plank, Technical Director, Microsemi a Microchip Company

Designing SSD Storage Systems for Low Latency Without Large Outliers
Sebastien Jean, Director of System Architecture, Phison Electronics

Time to Market New Flash Device to Production SSD
John Plasterer, Chief Architect, NETINT Technologies

Session Description:
Enterprise SSDs are achieving higher capacities and higher performance and are therefore used in more applications, displacing HDDs in a wide variety of environments. Storage system designers must make new tradeoffs among performance, data retention and endurance for SSDs to account for their special characteristics. Hyperscale data centers also have special requirements that must be met, most likely with architectures specifically intended for these fast-growing environments.
Intended Audience:
Executives, Engineers, End Users, Technology Journalists, Press, Technologists, Marketing Professionals, Applications Engineers, Entrepreneurs, Academics, Students, and other Researchers

About the Organizer/Chairperson:
Mike Gluck is Vice President and CTO at Sanity Solutions. Mike has over 35 years of experience in the computer and data storage industry. His focus is assisting clients craft innovative data management solutions that provide distinctive value and competitive advantages for their strategic business goals. Internally, he analyzes key IT trends, paradigm shifts and disruptive technologies, searching for leading-edge vendors and products that can provide differentiation and competitive advantages for clients.

Tuesday, August 6th
4:55-6:00 PM
AUTO-102B-1: Autonomous Vehicles Transportation Ecosystem Challenges (Automotive Applications Track)
Organizer + Chairperson: Andy Marken, President, Marken Communications

Panel Members:
Speaker: Andy Walls, Fellow/CTO/Chief Architect, Flash Storage, IBM

Speaker: Neil Werdmuller, Director, Storage Solutions, Arm Holdings

Panelist: Kun Zhou, Program Manager, California PATH, UC Berkeley

Speaker: Chris Lien, Senior Manager, ATP Electronics Taiwan

Session Description:
With transportation edge computing takes on a new meaning. Will data volumes of data have to be stored/used close to the decision point or will only a minimum of data be required while the majority of data be captured, processed, used discarded. How much storage will be needed in tomorrow’s vehicle and how much will be required in the ecosystem. Find out the design requirements – size, performance, security, privacy - for the next level of edge computing storage in a mobile environment. Or miss the bus and watch the taillights of your storage opportunities disappear over the hill.
Intended Audience:
Automotive system designers, hardware and software designers, engineering managers, system engineers and analysts, product and product marketing engineers, computer and communications specialists.

About the Organizer/Chairperson:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Tuesday, August 6th
4:55-6:00 PM
BMKT-102B-1: Data Growth and a Future with Zettabytes (Business/Marketing Track)
Chairperson: Mike Matchett, TechTarget Research Advisor, Small World Big Data

Organizer: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Ramnath Sai Sagar, Senior Product Marketing Manager, AI and Deep Learning, Pure Storage

Panelist: Kirk Bresniker, Chief Architect/HPE Fellow/VP, HPE

Panelist: Ken Steinhardt, Field CTO, Infinidat

Panelist: Walt Hinton, CMO, Pavilion Data Systems

Session Description:
A session on how AI/Machine learning, IoT and analytics will impact the explosive growth of data and how that will impact storage capacity and performance. “IDC says that 22 Zettabytes (ZB) of digital storage will be shipped across all storage media types between 2018 and 2025” –how will this change the way we look at and mange storage from both a capacity and performance standpoint?
Intended Audience:
CMOs, VP Marketing, Marketing Directors and Managers, Product Marketing Specialists, Sales Representatives and Managers, Business Development Executives, MarCom and PR Specialists, Product Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Financial Analysts and Executives, Venture Capitalists, Media Representatives, Channel Marketing Managers, Distributors, VARs, System Integrators, and Solution Providers.

About the Organizer/Chairperson:
Mike Matchett is Principal IT industry analyst at Small World Big Data, focusing on technology trends and the intersection where IT enterprise meets emerging markets. He is also a lead consultant and advisor to TechTarget’s Market Research and Development Group. With more than 25 years of high-tech marketing and product management experience, Mike writes across data center, cloud and big data segments predicting that all data will become big, all clouds hybrid, and the converged data center re-imagined from center to edge. Prior to TechTarget, Mike spent 5 years in a Sr. Analyst role w/ the Taneja Group where he provided services for existing and emerging IT enterprise infrastructure markets. Mike has a B.S in electrical engineering from the Massachusetts Institute of Technology.

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Tuesday, August 6th
4:55-6:00 PM
CMOB-102B-1: Break the Storage Bottleneck for 5G and IoT (Consumer/Mobile Applications Track)
Organizer: Chuck Sobey, Chief Scientist, ChannelScience

Chairperson: Matt Eastwood, SVP, Enterprise Infrastructure and Datacenter, IDC

Paper Presenters:
Session Description:
The Internet-of-Things (IoT) is here today. New 5G Low Power and private 5G networks enable sensors to store scads of information and transfer it faster and more efficiently. The IoT world has billion of devices with sensors, large storage, and communications. The result is massively connected networks, all active interacting and creating an incredible network intelligence. The low-power devices store GBs of data and do local processing to reduce the strain on networks. The challenge is to integrate IoT and 5G to provide benefits to the enterprise. NB-IoT has been announced but there are also private IoT and Long Range Bluetooth focused on IoT as well. Storage plays a critical role in all of these networks.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer, as well as the General Chairperson of the Flash Memory Summit. He is the founder of the R&D services firm ChannelScience, which develops new capabilities in data storage. Currently, he is advising on such major trends as STT-MRAM, ReRAM, memory manufacturing in China, computational storage, 5G, AI/ML acceleration, and standards for personal AI agents. He has also provided strategic storage technology advice to government agencies worldwide. He has presented at many conferences, including Flash Memory Summit, and has given courses on storage-related topics around the world. He earned electrical and computer engineering degrees from Carnegie Mellon University and the University of California at Santa Barbara.

Matt Eastwood is Senior Vice President of IDC's Infrastructure, Cloud, Developer and Partnering research groups. He leads a team of analysts responsible for identifying and analyzing people, process and technology trends affecting the deployment and management of edge infrastructure, enterprise datacenters and clouds worldwide. He speaks frequently at IDC, industry, and user events around the world and is frequently quoted in leading business and technology publications. He received bachelor and master's degrees in civil engineering from Northeastern University and Worcester Polytechnic Institute respectively.

Tuesday, August 6th
4:55-6:00 PM
CMOB-102B-2: New Form Factor Makes SSDs Shine in Client Applications (Consumer/Mobile Applications Track)
Session Sponsor: Toshiba Memory
Organizer + Chairperson: John Geldman, Director, SSD Industry Standards, Kioxia

Paper Presenters:
A New Replaceable SSD Form Factor
John Geldman, Director, SSD Industry Standards, Kioxia

A Replaceable Connector
Kenta Minejima, , Japan Aviation Electronics

Compatibility Testing Environment for NVMe SSDs
Miki Takahashi, , Granite River Labs

Storage Form Factor Trends for Notebook PC
Takashi R Sugawara, , Lenovo

Session Description:
Replacement of hard drives by SSDs in client PCs is continuing, and SSDs have become standard in new computers. The M.2 form factor has ushered in a new class of thin, light SSD designs, improving the mobile computing experience. Next generation mobile devices embracing 5G, hybrid tablet/phone, and ultra-thin computing are driving the need for SSDs to become lighter, smaller, removable, and more power-efficient. With flash memory becoming even more dense and cost effective, a new form factor is needed to keep pace with new demands in client computing. See why this innovation will be used by leading system makers and how it will come to market.
Intended Audience:
Hardware and software design engineers, engineering managers, system engineers and analysts, product engineers and managers, product planners, performance and application analysts

About the Organizer/Chairperson:
John Geldman is Director SSD Industry Standards at Toshiba Memory. He focuses on standards for cloud storage, HDD and SSD storage devices, data security, and persistent (storage class) memory. His previous standards committee engagements include INCITS T10 and T13, NVMe, PCI-SIG, SATA-IO, TCG, SFF, SNIA, OSF, OCP, and JEDEC. He is well-known as a storage interface leader adept at guiding standards organizations and architecting groundbreaking technical developments. His specialties include SSD architecture, IP development, storage security, and storage card products. He was previously Director Industry Standards at Micron, where he led the company’s participation in such standards bodies as T10, T13, SATA, IEEE 1667, USB, CompactFlash, and the SD Association. He has also worked for Brecis Communications, Basis Communications, and Cirrus Logic. He holds 9 patents and has been recognized for his standards work by the SD Association and INCITS. A frequent blogger and conference contributor, he has been a speaker, organizer, and chairperson at Flash Memory Summit, as well as being a member of the Conference Advisory Board. He holds an MSCS from Santa Clara University and a BSECE from Clarkson University.

Tuesday, August 6th
4:55-6:00 PM
ENST-102B-1: Application Acceleration (Enterprise Storage Track)
Organizer: Camberley Bates, Managing Director/Analyst, Evaluator Group

Organizer: Jean Bozman, President, Cloud Architects

Chairperson: Michelle Tidwell, Program Director, Storage Software for Hybrid Cloud, IBM Storage Systems

Paper Presenters:
Applications Demanding Accelerated Disaggregated Storage
Scott Schweitzer, Sr Mngr, Marketing Communications, Solarflare

Real World Application Performance for the Latest Storage Technologies
Eden Kim, CEO, Calypso Systems

Modelling and Measuring Demanding Transactional Workloads Using SPC-1
Stephen Daniel, Distinguished Technologist, HPE / SPC

A Data-Path-Blind Distributed Storage Cluster Manager
Ronen Hod, Software Developer, Excelero

Session Description:
One of the main purposes for employing flash memory is to accelerate applications. Many of the most popular recent applications, such as business analytics and NoSQL databases, often run quite slowly, particularly as their datasets increase in size. Furthermore, high-speed SSDs may themselves require acceleration as their requirements are beyond the capabilities of many low-end processors.
Intended Audience:
Hardware and software design engineers, engineering managers, system engineers and analysts, product engineers and managers, product planners, performance and application analysts

About the Organizer/Chairperson:
Camberley Bates is Managing Director/Analyst at Evaluator Group, a leading analyst firm covering IT infrastructure and services. She has dedicated Evaluator Group to delivering unbiased in-depth research on information management and data storage - and helping customers use that research to develop the infrastructure they need. She is responsible for corporate leadership and coverage of go-to-market and channel strategies. She has over 20 years of executive experience leading sales and marketing teams at VERITAS, GE-Access, EDS, and IBM. Her achievements include developing a new market category at Copan Systems, restructuring channel programs at Veritas, and growing a new division of GE Access from $14 million to $500 million in revenue through a solution-practice methodology. Camberley is a frequent panelist and chairperson at such events as Interop and Flash Memory Summit, as well as being frequently quoted in the trade and technical press. She holds a BS degree in International Business from California State University Long Beach and executive certificates from Wellesley and Wharton School of Business.

Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

Michelle Tidwell is Program Director and Global Offering Manager of Software Defined Storage for Hybrid Multi Cloud environments at IBM. She is responsible for product delivery and strategy around Hybrid Multi Cloud storage software and solutions. Previous to this role, Michelle was Business Line Manager, IBM Storage Strategic Alliance Offerings, working with Strategic ISVs globally to develop new storage solutions and business alliances across a number of vertical and cross-industry segments. Michelle is also serving as a Board member on the Storage Networking Industry Association (SNIA) Board of Directors for IBM. Michelle holds a Bachelor of Science in Electrical Engineering and Computer Science from Santa Clara University.

Tuesday, August 6th
4:55-6:00 PM
INVT-102B-1: Achieving Fault Tolerance for Storage Class Memory (Persistent Memory Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Xinde Hu, Principal Engineer, Western Digital

Paper Presenters:
Achieving Fault Tolerance for Storage Class Memory
Huynh Tu Dang, Principal Engineer, Western Digital

Session Description:
Storage Class Memory (SCM) allows designers to replace several tiers of the memory hierarchy with a single, cost-effective, uniform memory/storage. To make such large-scale deployments practical, however, designers must be able to deal with unavoidable SCM wearout and failures. A new approach can provide fault tolerance in SCM-based main memory. It treats memory as a distributed storage system and relies on replication, plus programmable interconnect providing fast consensus to keep the replicas consistent. Initial experiments demonstrate reasonable overhead over local memory access and show great promise as scalable, fault-tolerant main memory.
Intended Audience:
Hardware design engineers and managers, storage engineers and managers, system engineers and managers, product planners and designers, engineering managers and CTOs

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Xinde Hu is currently Director of System Architecture @eSSD at Western Digital. His responsibility includes creating, designing, and evaluating innovative system architecture concepts and implementations for the next generations of non-volatile memory based storage systems. Before joining Western Digital, Dr. Hu held architectural leader positions in STEC and STMicroelectronics. Dr. Hu has authored more than a dozen technical papers on data storage systems and has 38 patents issued. He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.

Speaker Bio: Huynh Tu Dang is a Principal Engineer at Western Digital, where he develops network-accelerated fault-tolerant data management systems. His research interests are in dependable distributed systems and computer networking. He has pioneered a novel approach to accelerate performance of consensus systems using a new type of programmable switch. He earned a PhD in computer science from UniversitĂ Della Svizzera Italiana (USI in Lugano, Switzerland), and an MS in computer science from Polytech Nice-Sophia Antipolis (Nice, France). He has published many articles in both journals and conference proceedings and has applied for two patents.

Tuesday, August 6th
4:55-6:00 PM
NEWM-102B-1: Annual Update on Emerging Memory Technologies (New Memory Technologies Track)
Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Chairperson: Satoru Araki, Senior Director, Program/Product Management, Spin Memory

Paper Presenters:
Product Lifecycle Status of Emerging Memories
Mark Webb, President, MKW Ventures

Session Description:
Emerging memories have been forever banished to tiny niche markets subject to their impossibly insurmountable DRAM and NAND overlords? Or have they? Each year, Flash Memory Summit offers predictions about how new memory technologies are near the horizon and why they will disrupt the memory business and system architectures. Will emerging memories perpetually be 3 years to production or is the dawning of something new finally here? This session will offer a practical walkthrough of what we've learned about emerging memories over the past decade, the barriers that threaten their emergence, and what technical, manufacturing, ecosystem, and market conditions need to exist for them to be truly successful.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Leah Schoeb is a Sr. Developer Relations Manager in the platform architecture team at AMD, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, with the last decade in solid state technology. She is also the Founding Data Architect at Data Glass, where she assists systems companies with performance engineering and optimization, market positioning, and benchmarking. She was previously Acting Director Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as the Industry Trends Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC), and Storage Networking Industry Association (SNIA). She is a member of the SNIA Technical Council and a co-founder of their Solid State Storage System Technical Work Group. She earned an MBA at the University of Phoenix and a BSEE at the University of Maryland, College Park.

A technology management executive with over 20 years’ experience, Satoru Araki is currently Sr Director, Product/Program Management at Spin Transfer Technologies. He was previously a Dir, Program Management and Platform Development at HGST where he served as technology project/program director for several technical projects and products. He has previously been a Dir, Advanced Wafer Engineering and Advanced Technology at HGST. He also has prior experience with Read-Rite and TDK as a Sr. Director. He holds a BS, MS, and PhD in Applied Physics from Waseda University, Japan and an MBA from San Jose State University.

Speaker Bio: Mark Webb is Principal/Consultant at MKW Ventures Consulting where he provides consulting services in SSDs, NAND, NVM, and semiconductor technology and competitive analysis. With over 25 years experience in semiconductor and system engineering and manufacturing, Mark consults with SSD OEM and ODM companies, memory manufacturers, and investment firms. Before founding MKW Ventures, Mark was Director of Manufacturing for the NVM Solutions Group at Intel, where he was responsible for SSD system and NAND component manufacturing. He also has been Corporate Product Quality and Reliability Manager for IM Flash Technologies, the widely publicized joint venture between Intel and Micron that became an industry leader in NAND technology. Mark is a frequent presenter at Flash Memory Summit and other key venues, and his analysis of technology adoption and product costs are often referenced by investment firms, analysts, technology training firms and major OEMs. He earned a BSEE at California State University, Chico.

Tuesday, August 6th
4:55-6:00 PM
NVME-102B-1: NVMe Software Drivers: What’s New and What’s Supported? (NVMe Track)
Session Sponsor: NVM Express
Organizer: Cameron Brett, Director SSD Product Marketing, Kioxia

Chairperson: Uma Parepalli, Sr Director, Marvell

Paper Presenters:
NVMe Software Drivers – What's New and What's Supported?
Scott Lee, Software Engineer Lead, Microsoft

Murali Rajagopal, Storage Architect, VMware
Jim Harris, , Intel

Session Description:
NVMe Driver eco-system exists for all leading Operating Systems including Microsoft Windows, Leading Linux flavors, VMWare as well as Platform Firmware UEFI. This session will cover what is new since last year for each of the drivers as well as gives an overview of the NVMe Driver eco-system including NVMe over Fabrics.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

Uma Parepalli is a senior level architecture and management leader with more than 28 years of experience in engineering, product and program management in enterprise, cloud and data center servers, storage, and networking, real-time embedded systems, consumer electronics, automotive, locomotive and aerospace domains. He is currently with Marvell and prior to that he worked for SK Hynix, Broadcom, Dell EMC, Intel, Wipro and others. Uma is an expert in hardware-software codesign and development of Intel and ARM64 Servers, Storage (PCIe NVMe, Fabrics, SAS, SATA), Platform firmware/UEFI domains. He had lead diversity & inclusion teams at Dell EMC and Intel earlier, and is the first diversity chair at Flash Memory Summit in 2019. Uma is a computer engineering graduate from University of Mysore.

Tuesday, August 6th
4:55-6:00 PM
SECU-102B-1: Building Security into Your System (Security Track)
Organizer: Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Chairperson: Mike McKean, Director, Encore Semi

Organizer: Paul Suhler, Storage Architect, Micron Technology

Paper Presenters:
Protecting the Platform through Measurement and Attestation
Jeff Plank, Technical Director, Microsemi a Microchip Company

Combating Persistent Cyber Attacks: The Secure Flash-to-Cloud Approach
Naseem Aslam, Sr. Manager, Product Marketing, Cypress

Yoni Kahana, VP Customers, NanoLock Security
Moving Target Defenses for Data Storage Devices
Donald Matthews, President and CEO, NexiTech

Session Description:
Ransomware is malicious software that threatens to publish the victim?s data or block access to it unless the victim pays a ransom. The problem of ransomware began around 2012 and has grown rapidly (and internationally). The sophistication of the attacks has grown rapidly, and the difficulty of stopping them or tracing what happens to payments has also increased greatly. The largest threat appears to be to medium-sized installations that depend on their data, lack much sophistication in methods or personnel, and are capable of paying large ransoms. Examples include school districts, hospitals, professional firms, and small/medium-size businesses. As flash memory becomes more widespread, it will surely become still another method for attack. As a new technology, it is often left unprotected and its vulnerabilities are neither well-known nor well-understood. As more data migrates to flash, the problem will only get worse. Flash manufacturers at all levels will need to understand this threat and what they can do to combat it.
Intended Audience:
Security and Infosec Specialists, Officers, and Engineers; Storage Managers and Engineers Mobile Technology Managers; Network and Data Center Directors, Managers, and Engineers; Enterprise Storage System Designers; Enterprise Flash and SSD Product Managers and Marketing Engineers; Large-Scale Systems Designers, Investors and Analysts

About the Organizer/Chairperson:
Bob Thibadeau is Chairman and CEO of the Drive Trust Alliance (DTA). Previously he was Chief Technologist for Seagate Technology and the originator of the Trusted Computing Group’s Self-Encrypting Drive (SED) Technologies. Currently the DTA has developed “Auto Erase” key management technology for SEDs in Automotive and other system IoT situations where SEDs are physically distributed in the IoT system (drivetrust.com/auto-erase). Previously, he headed projects in Robotics at Carnegie Mellon University for the major Automotive OEMs which resulted in nearly universal adoption of his inventions.

Mike McKean is currently Director of Sales at Encore Semi, a design services firm focused on ASIC and firmware/software design and development. At Encore Semi, he leverages his ASIC and firmware background to grow key accounts and support projects with technical skills. He is currently leading firmware development for projects using multiple SSD controller architectures. Before joining Encore, Mike was VP Product Solutions at cybersecurity startup FHOOSH and General Manager for the Colorado Design Center of Synapse Design Automation. At Synapse, Mike led the successful execution of multiple HDD, SDD, and consumer electronics projects. He has 30 years experience in the semiconductor and systems industries. Mike is a regular presenter, chairperson, and organizer at Flash Memory Summit. He earned an MBA from the University of Texas at Austin and a BS in Engineering Science from Trinity University (TX).

Paul Suhler is a storage architect in SSD engineering at Micron Technology, where he is responsible for NVMe interfaces and for educating internal teams as well as customers. He is Micron's primary representative to the NVMe Technical Work Group to which he has contributed many proposals. He is also active in the SFF Technical Work Group, having chaired working groups on the U.3 specification, Ethernet drive connectors, and Ethernet speed negotiation. He has worked in the data storage industry for over twenty years at companies including HGST, Quantum, Seagate, and Adaptec. He has also been a member of the research faculty at the University of Southern California. He received the INCITS Technical Excellence Award, and is a Senior Member of IEEE. He holds a PhD and BS in computer engineering from the University of Texas at Austin, and an MS in computer engineering from the University of California, Berkeley. He is the author of papers and journal articles on parallel computing.

Wednesday, August 7th
Wednesday, August 7th
8:30-7:00 pm
FMS Persistent Memory Programming Hackathon (Persistent Memory Track)
Organizer + Chairperson: Jim Fister, Principal, The Decision Place

Paper Presenters:
Session Description:
The FMS Persistent Memory Programming Hackathon will provide a better understanding of how of how to use existing APIs to program persistent memory, as well as where it might benefit further research and development. Open Persistent Memory Hackathon drop-in sessions will run Tuesday August 6 and Wednesday August 7 from 8:00 am – 7:00 pm in the Great America Ballroom Foyer. Attendees will develop sample code based on open-source PM found in the Linux Kernel, PMDK.io and other interfaces. Following the Wednesday open Hackathon session, all are invited to a Persistent Memory Meetup from 7:00 – 8:30 pm in Great America Ballroom K to demonstrate the code they have developed.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Coming soon..

Wednesday, August 7th
8:30-9:35 AM
HYPR-201A-1: Flash and PM in Hyperscale (Hyperscale Applications Track)
Organizer + Chairperson: Jonathan Hinkle, Principal Researcher, Lenovo

Paper Presenters:
Hyperscale Challenges
Ross Stenfort, Hardware System Engineer, Storage, Facebook

Minimizing Customer Interruptions Due to SSD Failures
Brennan Watt, System Architect, Microsoft

Accelerating Hadoop at Twitter with NVMe SSDs: A Hybrid Approach
Matthew Singer, Sr. Staff Hardware Engineer, Twitter

Using an In-Memory Data Accelerator to Improve Cloud Analytics
Jian Zhang, Software Development Engineer, Intel

Session Description:
Coming Soon..
Intended Audience:
Coming Soon..

About the Organizer/Chairperson:
Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Wednesday, August 7th
8:30-9:35 AM
INVT-201A-1: NVMe-oF: What Performance Can You Expect for Real Applications? (NVMe-oF Track)
Chairperson: Andrew Cromarty, President, Heath Company

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
NVMe-oF: What Performance Can You Expect for Real Applications?
Andy Walls, Fellow/CTO/Chief Architect, Flash Storage, IBM

Session Description:
NVMe inside storage and servers is becoming ubiquitous. Gartner is projecting that 89% of servers and 52% of storage systems will have NVMe attach by 2022. The advantages over disk interfaces are obvious - higher bandwidth and lower latency. Now we are seeing NVMe extended to provide system-wide attachment via NVMe-oF and a variety of fabrics. Here again, initial tests show significant advantages over previous networking schemes. Response time is generally quite close to that of attached storage. However, simple tests don't tell the entire story. What are the benefits with real systems that have significant parallelism and many operations going on at the same time? Networks introduce new problems such as traffic issues and noisy neighbors. Fabrics also vary in their maturity and capabilities. Progress is continuing in both network speeds and traffic control methods. Designers can expect NVMe-oF plus NVMe devices to provide outstanding overall performance, particularly in large hyperscale deployments.
Intended Audience:
Data center engineers and managers; storage engineers and managers; performance analysts; hardware design engineers and managers; system engineers and managers; product planners

About the Organizer/Chairperson:
Dr. Andrew Cromarty is Managing Member of Distributed Systems Technology, and also President of Heath Company (Heathkit). He serves as an expert witness on patent infringement and contract dispute matters, and advises startups and technology corporations on operations, technology, corporate M&A due diligence, and product strategy. Andrew’s technical expertise includes software development, Internet/networking, distributed computing, multimedia, wireless/telecommunications, and eCommerce. His business expertise includes contracting, corporate and team management and evaluation, IT operations, market identification and evaluation, and product definition and development.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Andy Walls is Chief Architect and CTO for IBM’s Flash Systems Division. He is also an IBM Fellow, the company’s most prestigious honor. A 35-year storage industry veteran, Andy is a pioneer in enabling flash memory in the enterprise. He has developed enterprise storage systems that achieve high performance, good endurance, and the availability data centers require. He was responsible for the Texas Memory Systems acquisition and has since defined the architecture for all FlashSystem products. He is currently defining next generation products that can be used in traditional SAN environments as well as in clouds and by emerging workloads. He is widely recognized an expert in storage and flash memory. He has designed ASICs, PCBs, firmware stacks, and systems. Known as an innovator, he has filed over 100 patents. Andy earned a BSEE from UC Santa Barbara.

Wednesday, August 7th
8:30-9:35 AM
MRES-201A-1: Market Research Panel (Market Research Track)
Organizer: Jean Bozman, President, Cloud Architects

Chairperson: John Rotchford, Managing Director, SASI

Panel Members:
Panelist: Chris DePuy, Research Analyst/Co-Founder, 650 Group

Panelist: Camberley Bates, Managing Director/Analyst, Evaluator Group

Panelist: Jean Bozman, President, Cloud Architects

Panelist: Tom Coughlin, President, Coughlin Associates

Session Description:
The flash memory market has recently seen explosive growth and rising demand, attracting many startups and creating exciting acquisitions and IPOs. On the technology front, NAND flash products are achieving lower cost through higher densities and by cascading from SLC to MLC to TLC to 3-D. New products are being targeted for the enterprise ranging from embedded flash on servers to improve their I/O performance a thousand-fold to networked SSDs targeting lower costs. A new generation of smart controllers significantly increases performance using hierarchical flash caching, improves high availability, and enhances endurance through deploying ECC, wear-leveling, over- provisioning, and garbage collection techniques together with auto-configuration and workload aware auto-tiering placement. Such controllers help make SSDs suitable for mission critical enterprise applications. Attend this key session on the state of the flash Industry. It will cover market forecasts, shares, technology progress, competition, go-to-market pricing structures, and possible mergers and acquisitions. Ask questions of analysts to crystallize your understanding of markets and potentially competitive products. Areas of interest include: Forecast of flash growth in server and storage markets Market segments where flash will displace other technologies New configurations such as all-flash arrays and flash in DIMM (NVDIMM) Price trends and their impact on markets New interfaces such as NVMe and NVMe-oF Effects of software-defined storage and hyperconvergence Whether future computer systems will incorporate flash directly at all levels The role storage will play in the transition from on-premise data centers to clouds The status of emerging technologies such as MRAM, RRAM, and 3D XPoint? Acquisition candidates
Intended Audience:
Marketing managers, CMOs, product marketing managers and engineers, marketing specialists, sales engineers, marketing communications specialists, product planners, marketing consultants

About the Organizer/Chairperson:
Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

John Rotchford is Managing Director and Founder at SASI, a boutique mergers and acquisitions (M&A) advisory firm focused on serving investors and entrepreneurs in the IT industry. SASI represents leading venture backed private companies that are exploring strategic M&A options. John is a 20-year technology industry veteran with a unique blend of investment banking, strategy consulting, corporate development, and start-up experience. He was previously a Vice-President at Silicon Valley Bank, where he co-managed the information technology practice, and Director Corporate Development at Iomega, where he was responsible for strategic planning, M&A, and new investment activities. He earned a BS in Accounting and Finance from Babson College.

Wednesday, August 7th
8:30-9:35 AM
NVME-201A-1: NVMe IDC Market Overview/Enterprise Servers and Storage (NVMe Track)
Session Sponsor: NVM Express
Organizer + Chairperson: Cameron Brett, Director SSD Product Marketing, Kioxia

Chairperson: J Metz, Board Member, SNIA

Paper Presenters:
NVMe Markets: Rising at Breakneck Speed with Even Better Days Ahead
Eric Burgener, Research VP Infrastructure Systems and Platforms, IDC

Session Description:
NVMe is rapidly become a leading interface for enterprise storage, replacing the traditional hard drive interfaces such as SAS and SATA. Markets are now in the billions of dollars and show no signs of peaking. Recent primary research covers deployment in a wide variety of production environments and explores what is driving the purchases, what the major workloads are, and what issues have arisen. It includes an overview of the current market and future trends. Full steam ahead is the order of the day, and customers and vendors can use the research to guide new products and purchases, estimate market sizes, and project revenue opportunities. With the increased availability and awareness of NVMe products, more enterprises are making the transition to NVMe. Join our panel discussion to learn how server and storage vendors are helping make this transition possible.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

J Metz is currently an R&D Engineer for the Office of the CTO in Cisco’s Compute and Server Group, where he focuses on directions for storage strategy. He is an award-winning public speaker, author, and contributor to industry trade publications, blogs, webinars, and conferences. He has been a leader in developing industry standards, with membership on the Board of Directors for the Fibre Channel Industry Association (FCIA), Storage Networking Industry Association (SNIA), and the Non-Volatile Memory Express (NVMe) Promoter’s Board. J has previous experience with QLogic and Apple. He earned his PhD from the University of Georgia. J has been a speaker, panelist, and chairperson in well-received sessions at several past Flash Memory Summits.

Wednesday, August 7th
8:30-10:50 AM
CTRL-201-1: Controllers and Flash Technology, Part 1 - Hardware and Algorithms (Controllers Track)
Chairperson: David Declercq, CTO, CodeLucida

Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Paper Presenters:
Maximizing Performance/cost of SSD composed of Memory-type and Storage-type SCMs
Reika Kinoshita, Student, Chuo University

Advanced data integrity assurance for QLC flash
Licheng Xue, Sr. Staff Engineer, Starblaze

Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives
Saugata Ghose, Special Faculty Systems Scientist, Carnegie-Mellon University

Towards data-driven NAND flash controller development
Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Error Handling Technologies for QLC-Based Storage
Wei Lin, System Architect, Phison Electronics

SSD with Compression: Implementation, Interface and Use Cases
Erich Haratsch, Senior Director Architecture, Marvell

Session Description:
This session provides details on improving the endurance, retention, and performance of 2D and 3D NAND flash devices. Important strategies and signal processing that controllers can employ to further improve key reliability measures are revealed. The forum also presents novel implementations for reducing power usage and solving problems caused by write amplification. Learn about new technology developments and have time for questions and answers with top industry experts.
Intended Audience:
ECC engineers and specialists, design engineers, engineering managers and directors, hardware and firmware architects, field application engineers, test engineers, system designers and analysts , storage engineers and managers

About the Organizer/Chairperson:
David Declercq is the co-founder and CTO of Codelucida Inc. He was previously full professor at the ENSEA in Cergy-Pontoise, France, from 2001 to 2017. He is a senior member of the IEEE, and a widely renowned researcher in the area of LDPC code and decoder design. He published more than 150 papers in the area, and holds 8 patents. Several of his contributions towards LDPC code and decoder design have been employed by industry as well as adopted in several standards. He is especially recognized for his pioneering works on non-binary LDPC code and decoder designs.

Erich F. Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Wednesday, August 7th
8:30-10:50 AM
ENAP-201-1: Enterprise Applications, Part 2 (Enterprise Applications Track)
Organizer + Chairperson: Tom Burniece, President, Burniece Consulting Services

Paper Presenters:
NVMesh: A Cluster Application For NVMe Drives
Tom Leyden, VP Marketing, Excelero

Persistent Memory: Revolutionizing the Modern Database
Gurmeet Goindi, Master Product Manager, Oracle

Analytics @ Rack-Scale with NVMe-oF
Walter Hinton, CMO, Pavilion Data Systems

Optimize Enterprise Applications with Shared Accelerated All-Flash Storage
Suhas Nayak, Director, Products & Solutions Marketing, Pure Storage

Session Description:
Flash memory has enabled new storage system and computing architectures which can handle many enterprise applications far more efficiently than is possible with hard drives. This session will feature actual case studies by innovative storage companies, including descriptions of the problem, approach, and results. Customers will co-present with some speakers.
Intended Audience:
IT Managers, Application Administrators, Database Administrators, Application Developers, Data Center Architects, Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Storage Managers, Network Engineers, Marketing Engineers, Consultants, Analysts, and System Administrators.

About the Organizer/Chairperson:
Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Wednesday, August 7th
8:30-10:50 AM
NEWM-201-1: 3D XPoint: Current Implementations and Future Trends (New Memory Technologies Track)
Organizer + Chairperson: Milind Weling, Sr VP Programs and Operations, Intermolecular

Paper Presenters:
3D XPoint Technology and Market Update
Mark Webb, President, MKW Ventures

Where is 3D XPoint Headed?
Jim Handy, Director/Chief Analyst, Objective Analysis

Approaches that Combine Optane with QLC Offer Solutions Competitive with TLC
Kapil Karkra, Software Architect, Intel

Michal Wysoczanski, , Intel
Piotr Wysocki, , Intel
Memory-Converged Infrastructure Based on Persistent Memory
Charles Fan, Co-founder & CEO, MemVerge

Using an Emerging Memory Cache with a High-Speed Client SSD
Stanley Huang, Director, SSD Product Marketing, Silicon Motion

Storage Engine for 3D XPoint and 3D QLC NAND SSDs
Jack Zhang, Software Engineering Manager, Intel

Session Description:
The speculation surrounding Intel/Micron 3D XPoint technology has been huge, ever since its introduction in 2015. What is the reality? Where is the technology today and what applications are already using it? What are the effects of the relatively high prices (five times that of flash) that have now been suggested? Where will the technology be in 2022 and what steps will occur along the way? Obviously, this is long-term speculation with no guarantees. However, a look at the far horizon can provide guidance as to what developers are thinking and what initial users and observers now feel is possible.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, IT Architects and Strategists, Data Center Managers, Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Milind Weling is Senior Vice President of Programs and Operations at Intermolecular. He is responsible for IMI’s high throughput experimentation technology and manages the technical execution of customer programs for the discovery of advanced materials and leading edge device optimization. Milind is a senior engineering and management professional with extensive experience in advanced memory and logic semiconductor technology development, DFM and design-process interactions, new product introduction, and foundry management. His previous senior management roles include DFM products engineering at Cadence Design Systems and high performance CMOS technology development at Sun Microsystems, Philips Semiconductors and VLSI Technology. Milind holds a B. Tech degree in Electrical Engineering from the Indian Institute of Technology, Bombay, and a MS degree in Electrical Engineering from the University of Hawaii. He holds 50+ patents and has co-authored over 70 technical papers, primarily focused on process technology, reliability and integration.

Wednesday, August 7th
8:30-10:50 AM
NVME-201-1: PCIe/NVMe Issues (NVMe Track)
Organizer + Chairperson: Deepankar Das, CTO, Sureline Systems

Organizer: Rakesh Cheerla, Software Product Line Manager - SmartNICs, Intel

Paper Presenters:
Boosting QLC SSD Performance and Endurance for Data Centers
Orit Wasserman, Principal Architect, Lightbits Labs

Standardization for a Key-Value Interface underway at NVM Express and SNIA
William Martin, SSD IO Standards Development, Samsung Electronics

Using a PCIe Analyzer with NVMe-Based Products
Isaac Livny, Applications Engineer, Teledyne LeCroy

NVMe Gen-4 Thermal Management: Too Hot To Touch
Grace Chen, Project Manager, Phison Electronics

Session Description:
PCIe SSDs offer higher performance than ones based on disk interfaces, since they utilize the high-speed (and widely supported) PCIe bus. They have quickly become popular in a wide variety of enterprise applications, particularly in implementations utilizing the new NVMe standard. Of course, all the usual design problems occur ranging from connectors through power management, power consumption, configurability, and hardware/software tradeoffs. But with over 100 million enterprise PCIe ports already shipped, this is an approach enterprises find to be both reasonably priced and easily implemented. It can work in both client and data center applications.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Rakesh is a Solutions Planner at Intel, working with customer on SmartNIC solutions, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Wednesday, August 7th
8:30-10:50 AM
PMEM-201-1 Persistent Memory Part 3: Remote Persistent Memory-Case for Use Cases (Persistent Memory Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer: Paul Grun, OpenFabrics Alliance Chair; Storage I/O and Interconnect Architect, Cray

Organizer + Chairperson: Rob Peglar, President, Advanced Computing and Storage

Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Paper Presenters:
The Case for Use Cases
Paul Grun, OpenFabrics Alliance Chair; Storage I/O and Interconnect Architect, Cray

The Impact of Persistent Memory on Interconnects and Fabrics
Kurtis Bowman, President, Gen Z Consortium

Session Description:
Grappling with any emerging new technology requires a disciplined approach to developing the new technology and understanding its application. Remote Persistent Memory is an exciting new technology, but its ultimate impact is not yet in focus. This section describes how a ‘top down’ approach is being applied to the development of Remote Persistent Memory as an emerging technology. To illustrate that top down approach, this section introduces the work underway in the industry to describe use cases for remote persistent memory, and how those use cases will drive fabric requirements.
Intended Audience:
Application Architects and Designers, CTOs, System Engineers and Managers, HPC Engineers and Managers, Network and System Architects, System Integrators, Storage Engineers, Hardware and Software Design Engineers, and Product Planners

About the Organizer/Chairperson:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Paul Grun, Chair, OpenFabrics Alliance, is a senior technologist in Cray’s Storage and Data Management group, where he focuses on applying I/O technology to building large-scale systems. He is also a member of the InfiniBand Trade Association’s Steering Committee and chair of the Technical Working Group. He was chair and principle author for the working group responsible for creating the RoCE (RDMA over Converged Ethernet) specification. He also played a key role in creating the InfiniBand transport protocol. During his more than 30 year career, he has been intimately involved in all aspects of server I/O beginning with storage for large mainframe systems and,turning to high performance network architecture. He earned a BSEE from Syracuse University.

Robert Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit. He is a highly sought-after keynote speaker and panelist at leading storage and computing events.

Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Wednesday, August 7th
8:30-10:50 AM
SOFT-201-1: Composable Infrastructure and Software-Defined Storage (Software Track)
Organizer + Chairperson: Matias Bjorling, Director of Emerging System Architectures, Western Digital

Organizer + Chairperson: Renu Raman, VP Cloud Architecture and Engineering, VMware

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Software Composable SSD Architecture Design for Enterprise Applications
Leander Yu, Vice President, Bigtera

Storage Management with Swordfish API for Open-Channel SSDs
Slawomir Putyrski, Principal Engineer, Intel

Addressing the Latency Gap with Composable Architectures
Larrie Carr, Sr Technical Director, Microchip

Challenges of Distributed Erasure Coding
Daniel Herman Shmulyan, Data Service Team Leader, Excelero

DAOS: Scalable Software-Defined Storage for HPC/Big Data/AI Convergence
Jeff Olivier, Software Engineer, Intel, Extreme Storage Architecture and Development

Session Description:
This session will include an exploration of composable infrastructure architectures that are enabled by technologies like OpenCAPI, CCIX and Gen-Z. It will also explore how software-defined infrastructures operate independently of any hardware-specific dependencies, and are programmatically extensible. In today's enterprise, the explosion of data and data sovereignty laws require infrastructures to be resilient and location transparent. Software infrastructures also allow for significantly improving operational efficiency. This session will discuss what is driving the move towards software-defined infrastructures, and how data management capabilities can be leveraged.
Intended Audience:
Software and hardware engineers and engineering managers; software specialists; systems analysts and engineers; product planners and managers; software managers; technical marketing engineers and managers.

About the Organizer/Chairperson:
Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

Renu Raman is VP and Chief Architect of Cloud Architecture & Engineering at SAP. He is responsible for the architecture, design, and development of SAP’s groundbreaking HANA cloud infrastructure compute and storage. He also has devised a high-performance persistence architecture for in-memory databases which he described at a previous Flash Memory Summit. He was previously Founder/CEO at Unity Microsystems, a developer of memory virtualization technology. He also had a long career at Sun Microsystems where he focused on developing many highly successful SPARC processors and associated devices. He was also an executive-in-residence at Tallwood Venture Capital for several years. He earned an MSEE from Northwestern University.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Wednesday, August 7th
8:30-10:50 AM
TEST-201-1: Testing/Performance Analysis (Testing Track)
Organizer + Chairperson: Easen Ho, President, S3 Metrics

Organizer + Chairperson: Joseph Chen, VP Engineering, ULINK Technolgy

Paper Presenters:
Optimizing SSD Performance Efficiently with Realistic Workloads
Bob Weisickle, CEO, OakGate Technology

Enterprise SSD Failure Analysis and Debug
Andrei Konan, Sr. Staff Firmware Engineer, SK Hynix Memory Solutions America

Using an Analytics Pipeline to Monitor NAND Health Data in the Field
Behzad Amiri, Senior Nand Engineer, Pure Storage

Accelerating the Qualification of Enterprise SSDs
Leah Schoeb, Sr. Developer Relations Manager, AMD

Optimal Flash Storage Solutions for Applications Requiring Frequent Writes
KuoHua Yuan, Director, ADATA Technology

Characterizing SSDs with the SMART Monitor
Shuhei Tanakamaru, Principal Engineer, Seagate

Memory Fencing for Detection of DMA Memory Address Violations
Bob Weisickle, CEO, OakGate Technology

Performance Evaluation of All-Flash Ceph Storage with QLC SSDs
John Mazzie, Senior Solutions Engineer, Micron Technology

Session Description:
Testing and performance analysis are an essential part of flash development and system evaluation. Conformance to standards, behavior under environmental stress, and the effects of varying workloads and system conditions must all be checked thoroughly. Performance analysis is also a key to determining how devices will behave in operation and in comparing devices during the evaluation stage. One problem of particular concern is wear, since the underlying memory elements are known to fail after a certain number of writes have been performed. Evaluations must be done with workloads that reflect actual client experience to ensure validity.
Intended Audience:
Test engineers, hardware design engineers, engineering managers, system engineers and analysts, product engineers and managers, product planners

About the Organizer/Chairperson:
Easen Ho is the president of S3Metrics, a consultancy specializing in SSD testing. He was formerly CTO of Calypso Systems, a leading solid state technology test equipment and test services company. Easen has been active in test standards development, and has given many talks at events such as Flash Memory Summit. He is a principal architect of the SNIA Solid State Storage Performance Test Specification. He received his PhD from MIT and an MS from Tokyo Institute of Technology, both in laser and optical engineering. He has been involved in many storage ventures over the last 15 years, including being Founder and President of Digital Papyrus.

Joseph Chen is VP of Engineering at Ulink Technology, a supplier of IT storage interface test tools. His focus areas include enterprise HDD/SSD development and qualification, SoC technical management, self-encrypted drives, and industry standards such as T10, IEEE 1667, and the Trusted Computing Group. He was previously Director of Systems Technology and Senior Firmware Manager at Samsung Electronics - SISA. At Samsung, he supervised SAS SSD design and development and managed the self-encrypting drive (SED) development project to produce Opal compliance. He has 30 years experience in the high-technology industry, including positions at Silicon Magic and Cirrus Logic. He holds an MS in computer science from Texas A&M University.

Wednesday, August 7th
9:45-10:50 AM
HYPR-201B-1: Hyperconverged Infrastructure (Hyperscale Applications Track)
Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Chairperson: Samira Khan, Assistant Professor, University of Virginia

Paper Presenters:
Accelerating Converged System Performance with FPGA-Based Switches
Quinn Jacobson, Strategic Architect, Achronix

Optimizing Hyperconverged Infrastructure for NVMe-Based Flash Storage
Kais Belgaied, Storage & Servers Division CTO, Sanmina

Achieving Ultra-High NVMe/TCP Throughput Using TCP Acceleration
Kelly Masood, CTO, intilop

Session Description:
Coming soon..
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Samira Khan is an Assistant Professor at the University of Virginia (UVa). Prior to joining UVa, she was a Post Doctoral Researcher at Carnegie Mellon University, funded by Intel Labs. Her research focuses on building system stack for emerging technologies. She is the recipient of NSF CRII Award, SPX Award, JUMP Center Award, and Rising Stars in EECS Award. She received her PhD from the University of Texas at San Antonio. During her graduate studies, she worked at Intel, AMD, and EPFL.

Wednesday, August 7th
9:45-10:50 AM
INVT-201B-1: Hybrid Cloud Flash Optimization for AI and Metadata Management (AI/Machine Learning Track)
Chairperson: Andrew Cromarty, President, Heath Company

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Hybrid Cloud Flash Optimization for AI and Metadata Management
David Flynn, CEO, Hammerspace

Session Description:
Flash technologies are key to enabling data-intensive workloads deployed across scale-out hybrid multi-cloud architectures, but as we approach the end of Moore's law we are forced to confront some uncomfortable truths. Advancements in silicon won't be enough on their own to carry us forward into the next era and building bigger, better data silos simply will not scale for next-generation workloads. To achieve our ambitions for scale, performance, and data governance we need to rethink the traditional approach to data management; becoming significantly more efficient with how data is made available and where it gets consumed by shifting our focus to the metadata. Managing rich metadata services at scale with an IT-assist from intelligent AI-driven automation will deliver the on-demand agility we need to seamlessly span clouds; the fine granular control we need to maximize the utility of our resources; and the intuitive usability we need for data operators to become masters of their data.
Intended Audience:
Data center managers, cloud managers and engineers, storage managers and engineers; cloud specialists; system managers and engineers; AI specialists; database specialists

About the Organizer/Chairperson:
Dr. Andrew Cromarty is Managing Member of Distributed Systems Technology, and also President of Heath Company (Heathkit). He serves as an expert witness on patent infringement and contract dispute matters, and advises startups and technology corporations on operations, technology, corporate M&A due diligence, and product strategy. Andrew’s technical expertise includes software development, Internet/networking, distributed computing, multimedia, wireless/telecommunications, and eCommerce. His business expertise includes contracting, corporate and team management and evaluation, IT operations, market identification and evaluation, and product definition and development.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Hammerspace co-founder and Chief Executive Officer David Flynn is a recognized leader in IT innovation who has been architecting disruptive computing platforms since his early work in supercomputing and Linux systems. David pioneered the use of flash for enterprise application acceleration as founder and former CEO of Fusion-io, which was acquired by SanDisk in 2014. He served as Fusion-io President and CEO until May 2013, and board member until July 2013. As the CEO of Fusion-io, David oversaw all operations, was responsible for the company’s strategic direction, and was the visionary behind the company’s innovative technology and market strategy. Preceding his position as CEO, David was the technical founder and CTO of Fusion-io, where he created the company’s foundational research and development efforts, as well as the development of short- and long-term technology roadmaps. Previously, David served as Chief-Architect at Linux Networx where he was instrumental in the creation of the OpenFabrics stack, and designed several of the world’s largest supercomputers leveraging Linux clustering, InfiniBand, and RDMA-based technologies. David also served as Project BlackDog’s Chief Scientist and Vice President of Engineering. He has also held positions at Network Computer, Inc. and Liberate Technologies, a spin-off of Oracle Corporation, developing thin-client solutions.

Wednesday, August 7th
9:45-10:50 AM
MRES-201B-1: NVMe Market Research Panel (Market Research Track)
Organizer + Chairperson: Jean Bozman, President, Cloud Architects

Panel Members:
Panelist: Andy Walls, Fellow/CTO/Chief Architect, Flash Storage, IBM

Panelist: Narayan Venkat, VP, Data Center Systems, Western Digital

Panelist: Marcus Thordal, Director Technical Solutions, Broadcom

Panelist: Eric Burgener, Research VP Infrastructure Systems and Platforms, IDC

Panelist: Mike Heumann, Managing Partner, G2M Communications

Panelist: Jonmichael Hands, Product Marketing Manager, Intel

Session Description:
NVMe has emerged rapidly as a major market since its introduction just a few years ago. It is intended as a standard package to enable designers to handle storage over the popular and widely supported PCIe bus. The largest part of the market is for simple adapters that connect a computer to a storage device. The advantage over the disk interfaces is higher speed. More recent extension of NVMe have opened new markets for switches, software, management, and system-level storage devices. Markets also include all-flash arrays, storage appliances, NVMe over Fabric (NVMe-oF) adapters, storage software, and intellectual property. NVMe-oF is the extension of NVMe to handle multiple computers, including clusters, multiprocessors, and distributed systems. As of 2016, over 70 companies had announced products based on NVMe, and over 100 companies had joined the NVM Express Organization, the governing body for NVMe. High-level members (known as promoters) include such important companies as Cisco, Dell EMC, Facebook, Intel, Micron, Microsemi, Microsoft, NetApp, Oracle, Samsung, Seagate, Toshiba, and Western Digital.
Intended Audience:
Marketing managers, CMOs, product marketing managers and engineers, marketing specialists, sales engineers, marketing communications specialists, product planners, marketing consultants

About the Organizer/Chairperson:
Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

Wednesday, August 7th
9:45-10:50 AM
NVME-201B-1: Client NVMe SSDs/NVMe in the Virtualized World (NVMe Track)
Session Sponsor: NVM Express
Organizer: Cameron Brett, Director SSD Product Marketing, Kioxia

Chairperson: J Metz, Board Member, SNIA

Paper Presenters:
Client NVMe SSD Objectives and Opportunities
Shivashenkar Muralishankar, , Intel

Lee Zaretsky, , Dell
NVMe in the Virtualized World
Suds Jain, Product Manager, VMware

Session Description:
NVMe technology is continuously evolving to meet the to meet the needs of consumers in the client space. During this panel, the experts will discuss the major industry trends in client storage, provide an overview of the various client classes of SSDs and review relevant form factors. They will discuss the future of NVMe architecture in the client space, including the impact of PCIe 4.0 technology, TLC versus QLC and the status of hard drives. The data-centric world is challenging the current status-quo in IT infrastructure industry. NVMe and its ecosystem hold an important part of data-centric future. Please join this session to learn all about NVMe and NVMe-oF™ in virtualized world, how Virtual and cloud deployments are leveraging NVMe as a de-facto interface to access varied storage services and use-cases and how NVMe is fueling the evolution towards disaggregated infrastructure.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

J Metz is currently an R&D Engineer for the Office of the CTO in Cisco’s Compute and Server Group, where he focuses on directions for storage strategy. He is an award-winning public speaker, author, and contributor to industry trade publications, blogs, webinars, and conferences. He has been a leader in developing industry standards, with membership on the Board of Directors for the Fibre Channel Industry Association (FCIA), Storage Networking Industry Association (SNIA), and the Non-Volatile Memory Express (NVMe) Promoter’s Board. J has previous experience with QLogic and Apple. He earned his PhD from the University of Georgia. J has been a speaker, panelist, and chairperson in well-received sessions at several past Flash Memory Summits.

Wednesday, August 7th
9:45-10:50 AM
SSDS-201B-1: New Enterprise and Datacenter SSD Form Factors (EDSFF) (SSDs Track)
Organizer + Chairperson: Dave Landsman, Director Industry Standards, Western Digital

Organizer: Anthony Constantine, Platform Architect, Intel

Paper Presenters:
EDSFF 1 year in: What have we learned
Anthony Constantine, Platform Architect, Intel

Why m.2 is Unsustainable (and what can we do about it)
Lee Prewitt, Principal Program Manager, Microsoft

EDSFF for NVMe Computational Storage Processors
Stephen Bates, CTO, Eideticom

Adventures in Form Factors
Ross Stenfort, Hardware System Engineer, Storage, Facebook

Session Description:
It has been a bit over a year since the EDSFF form factor standards were launched in SFF. As the industry has begun building to the specs, we have learned some things, and already begun innovating on the specifications. This session will cover what we've learned, in general, since the introduction. We'll focus in particular on the evolution of E1.S to enable storage and compute acceleration use cases in compute servers. And we'll discuss how E1.S and E1.L, together, are providing solutions to replace M.2 in Datacenter and Enterprise.
Intended Audience:
System and device developers.

About the Organizer/Chairperson:
Dave Landsman is Director of Industry Standards at Western Digital, where he manages storage standards efforts for data center, client, and mobile/removable markets. A recognized leader in storage standards, Dave has been involved in many important groups, including NVMe, PCI-SIG, JEDEC, SATA-IO, T10, T13, SNA, SFF, and USB-IF. He is currently WD’s board representative for NVMe, SATA-IO, and the CompactFlash Association, and is co-chair of the Storage Work Group at the Trusted Computing Group. He has contributed to many standards work groups and has presented on standards at many conferences including Flash Memory Summit. He has worked on storage for 12 years and has over 30 years experience in the semiconductor industry. He earned a BA in computer science from the University of California, San Diego.

Anthony Constantine is a Principal Engineer at Intel that focuses primarily on driving innovation to storage from mobile to datacenter. He is an active contributor in the standards area with published contributions in SFF/SNIA, PCI-SIG, ONFI, and JEDEC. He serves as Technical Chair and Editor for both Open NAND Flash Interface (ONFI) and Enterprise and Datacenter Form Factor (EDSFF). Anthony has over 18 years of experience at Intel with prior experience in memory, low speed IO interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Wednesday, August 7th
3:20-4:25 PM
AUTO-202A-1: Auto Infotainment Advances/Obstacles (Automotive Applications Track)
Organizer: Andy Marken, President, Marken Communications

Chairperson: Greg Basich, Associate Director, Automotive Infotainment and Telematics and Connected Mobility Services, Strategy Analytics

Paper Presenters:
Auto Infotainment and Connectivity in Autonomous Vehicles - Impacts on Storage
Greg Basich, Associate Director, Automotive Infotainment and Telematics and Connected Mobility Services, Strategy Analytics

Secure F-RAM for Automotive Event Data Recording in ADAS Applications
Doug Mitchell, Product Marketing Engineer MPS, Cypress Semiconductor

Infotainment and Autonomous Vehicles - The challenges of storage
Michael Huonker, Engineer Advanced Head Unit, Daimler AG

NVMe Mass Storage Integration on Emerging Automotive Systems
Matthias Beste, HW Design Engineer, Intel

Session Description:
Auto Infotainment store or stream Advances - Entertain or Distract - The infotainment system of tomorrow’s vehicle will be the major control session for the vehicle and passengers that will have to both inform/entertain them but also enable the vehicle and individuals to quickly and accurately analyze the vehicle as well as stationary and moving objects around them. How will we deliver, store and use this constant stream of data, information, entertainment efficiently and effectively to a centralized location. How much high-speed storage capacity will be needed and how will redundancy be implemented to provide sufficient safeguards to the vehicle all of the time and in all types of conditions.
Intended Audience:
Senior management, engineering managers, Tier 1 and automotive design management

About the Organizer/Chairperson:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Greg Basich is the Associate Director with Strategy Analytics’ Automotive Infotainment & Telematics service and the company’s Automotive Connected Mobility service. He has been with Strategy Analytics for more than 5 years after a previous 13-year career as a business-to-business automotive journalist. At Strategy Analytics, Greg focuses on a number of topics, including connected car technologies and business models, automotive infotainment, mobility services such as car sharing and ride hailing, and automotive cyber security.

Wednesday, August 7th
3:20-4:25 PM
BMKT-202A-1: CMO Panel: Flash Will Be Everywhere but the Customer Still Rules (Business/Marketing Track)
Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Walt Hinton, CMO, Pavilion Data Systems

Panelist: Dan Liddle, VP Marketing, Viking Enterprise Solutions

Panelist: Josh Epstein, Chief Marketing Officer, Kaminario

Panelist: Brendan Wolfe, VP Product Marketing, Hammerspace

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Session Description:
Marketing enterprise flash storage is difficult. The technology is complex and fast-changing, and customers are often very confused and ill-informed. How does one develop a clear message that meets the customer’s needs and offers solid ROI? What role does marketing analytics play in gaining a competitive advantage? Has the marketing playbook really changed? What are the winning strategies with the shift to cloud, hyperconverged architecture, and software defined infrastructure? What magic do successful marketers have up their sleeve as they follow the golden rule of “Know Your Customer”?
Intended Audience:
CMOs, VP Marketing, Marketing Directors and Managers, Product Marketing Specialists, Sales Representatives and Managers, Business Development Executives, MarCom and PR Specialists, Product Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Financial Analysts and Executives, Venture Capitalists, Media Representatives, Channel Marketing Managers, Distributors, VARs, System Integrators, and Solution Providers.

About the Organizer/Chairperson:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Wednesday, August 7th
3:20-4:25 PM
CTRL-202A-1: CXL - A Coherent Interface for Ultra-High-Speed Transfers (Controllers Track)
Organizer: Kurt Lender, Sr Manager Server Technology, Intel

Chairperson: Nathan Brookwood, Research Fellow, Insight 64

Panel Members:
Speaker: Kurt Lender, Sr Manager Server Technology, Intel

Panelist: Barry McAuliffe, Director - Technology Strategy, Office of the CTO, HPE

Panelist: Kurt Lender, Sr Manager Server Technology, Intel

Panelist: Kurtis Bowman, President, Gen Z Consortium

Panelist: Chris Petersen, Hardware Systems Technologist, Facebook

Session Description:
CXL introduces a general high-speed coherent interface, allowing the ultra-high-speed connection of all kinds of new technologies including accelerators, coprocessors, memories, and other devices. It thus supports various types of persistent memory, coprocessors (including GPUs and AI chips), and accelerators (including FPGAs and more advanced devices). CXL’s advantages include: · Single link for I/O, cache, and memory (including coherency) · Physical compatibility with the widely used PCIe interface with greatly reduced latency and coherency required by memory devices. · Support from major server, storage, software, memory, processor, and networking equipment makers, as well as hyperscale customers · Simple transition from traditional processor-memory systems · Ability to meet the needs of big data and high-performance computing, as well as those of emerging applications such as AI, ML, VR/AR, robotics, 5G, cloud computing, and image and video processing.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, IT Architects and Strategists, Data Center Managers, Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Coming soon..

Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. During his 40 year career in the industry, Mr. Brookwood has experience with Micronics Computers, Intergraph, Convergent Technologies, Prime Computer, and Digital Equipment. He is a graduate of MIT and has taken classes at Harvard Business School.

Wednesday, August 7th
3:20-4:25 PM
INVT-202A-1: Handling the Network Requirements of High-Speed NVMe SSDs (Hyperscale Applications Track)
Chairperson: Paul Lassa, Principal Systems Engineer, ICH Consulting

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Handling the Network Requirements of High-Speed NVMe SSDs
Rob Davis, VP Storage Technology, Mellanox

Manoj Wadekar, Storage Architect, Facebook

Session Description:
Today's NVMe SSDs can provide data at rates up to 20 Gb/s, with higher numbers coming. Such rates are essential to meet the requirements of applications such as real-time analysis, AI/ML, IoT, and high-performance video and wireless. However, they put tremendous strain on network resources. How do designers match the network to today's needs and tomorrow's expectations at a reasonable cost? Solutions include higher-speed Ethernet connections, rack-scale architectures, composable infrastructure and compute storage disaggregation to improve scalability and meet disparate application requirements. New storage stacks are also critical to take full advantage of SSDs, persistent memory, and high-speed switches and routers. Of course, all these approaches come with their own costs and limitations. Designers will need a deep understanding of network behavior to achieve cost-effective, scalable solutions that extend even to the largest hyperscale datacenters.
Intended Audience:
Hardware design engineers and managers, networking specialists; storage engineers and managers; system engineers and managers; data center managers; CIOs and CTOs

About the Organizer/Chairperson:
Paul Lassa is a consultant with ICH Consulting where he is a versatile designer in engineering development of high-volume consumer products and storage. Technical strategy and project execution in hardware, system, ASIC / SoC, and embedded software development is a hallmark of his work, and he specializes in the desgin of performance-, power- and cost-optimized devices, from concept through volume deployment. Paul's passion is to deliver utility, performance, and craftsmanship in amazing and powerful electronic products and infrastructure. He is a member of IEEE-CNSV which has a booth on the show floor.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe. He has presented at many conferences, including Storage Developer Conference, Red Hat Summit, Open Infrastructure Summit, and many past Flash Memory Summits.

Wednesday, August 7th
3:20-4:25 PM
NEWM-202A-1: RRAM (New Memory Technologies Track)
Organizer + Chairperson: Dave Eggleston, Principal, Intuitive Cognition Consulting

Paper Presenters:
RRAM Comes of Age
Shane Hollmer, VP Engineering, Adesto Technologies

Update XP ReRAM Technology
Amigo Tsutsui, Senior Business Producer, Sony Semiconductor Solutions

Making SiOx ReRAM a Cost-effective Embedded Memory
Amir Regev, CTO, Weebit-nano

TaOx-based ReRAM for Variability-Aware Approximate Computing
Chihiro Matsui, Assistant Professor, Chuo University/University of Tokyo (Japan)

Session Description:
RRAM (resistive RAM) development keeps progressing, with companies using a variety of approaches to pursue potential applications in high capacity storage, mid-range nonvolatile caches, and low cost embedded solutions. Come hear industry leaders offer views on the current state of RRAM technology, the target applications, and the road to commercialization.
Intended Audience:
Hardware design engineers, engineering managers, systems analysts and engineers, product and technology planners, CTOs, consultants, and memory specialists

About the Organizer/Chairperson:
Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Wednesday, August 7th
3:20-4:25 PM
NVME-202A-1: How Facebook & Microsoft Leverage NVMe Cloud Storage (NVMe Track)
Session Sponsor: NVM Express
Organizer + Chairperson: Cameron Brett, Director SSD Product Marketing, Kioxia

Paper Presenters:
How Facebook & Microsoft Successfully Leverage NVMe Cloud Storage
Ross Stenfort, Hardware System Engineer, Storage, Facebook

Lee Prewitt, Principal Program Manager, Microsoft

Session Description:
What do Facebook and Microsoft have in common? They are cloud market leaders using NVMe SSDs in their architectures. Get a close up look into their application requirements and challenges, why they chose NVMe flash for the storage, and how they are successfully deploying NVMe to fuel their businesses.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

Wednesday, August 7th
3:20-4:25 PM
TEST-202A-1: Testing Issues (Testing Track)
Organizer + Chairperson: Marilyn Kushnick, R & D Engineer, Advantest

Paper Presenters:
Using Functional Verification in Testing NVMe Controller Designs
Vikas Tomar, Product Engineer, Mentor

Characterizing NAND Devices at High Speed
Tamas Kerekes, President and CEO, NplusT

Challenges of Testing PCIe Gen4 SSDs (and Beyond)
Justin Treon, Applications Engineer, Advantest

Improvement of Read Disturb Policy in SSDs
Qingru Meng, Engineer, Intel

Session Description:
Testing is essential to ensuring that flash devices will meet system requirements. It may involve modeling as well as testing and must include a wide variety of effects. It also depends on the type of flash devices being tested, which may range from cards through entire arrays. It must reflect real-world conditions and include the effects of both hardware and software.
Intended Audience:
Test engineers, hardware design engineers, engineering managers, system engineers and analysts, product engineers and managers, product planners

About the Organizer/Chairperson:
Marilyn Kushnick is a Research and Development Engineer at Advantest, where she is currently an RTL designer for FPGAs in testers. She specializes in low power mode testing of SSD drives. She has experience in both the hardware and software sides of test equipment, having worked on embedded Linux drivers, tester controller software and GUI, and test programs. She holds a BS in electrical and computer engineering from UCLA.

Wednesday, August 7th
3:20-5:45 PM
CTRL-202-1: Controllers and Flash Technology, Part 2 - Error Correcting Codes (Controllers Track)
Organizer + Chairperson: Erich Haratsch, Senior Director Architecture, Marvell

Paper Presenters:
Improving Quality of Service for 3D NAND SSDs Using LDPC Correction
Rino Micheloni, VP & Fellow, Microsemi

Intelligent Read Threshold Tracking to Mitigate Read Retry Requests
Oliver Hambrey, Research Engineer, Siglead

Ultra MMI: an LDPC decoder that doubles throughput at end-of-life.
Shiuan Hao Kuo, Supervisor Engineer, Silicon Motion

A Low-Cost LDPC Solution for Flash Memory
Osso Vahabzadeh, Staff Design Engineer, Symbyon Systems

Using Machine Learning Techniques to Reduce SSD Costs
Cloud Zeng, Sr Engineer, Lite-On Storage

Improving Waterfall Performance of low-cost FAID LDPC Decoders
David Declercq, CTO, CodeLucida

Session Description:
This session describes recent developments in implementing LDPC (low density parity check) and other codes for error correction in NAND flash memories. You will learn practical aspects of power-efficient LDPC implementations, handling new NAND technologies, and developing an erasure recovery scheme. Get important insight from industry experts and have time for direct questions and answers!
Intended Audience:
ECC engineers and specialists, design engineers, engineering managers and directors, hardware and firmware architects, field application engineers, test engineers, system designers and analysts , storage engineers and managers

About the Organizer/Chairperson:
Erich F. Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Wednesday, August 7th
3:20-5:45 PM
FTEC-202-1: 3-D Flash (Flash Technology Track)
Organizer + Chairperson: Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Organizer: Shawn Adams, Product Marketing Manager, Micron

Paper Presenters:
Comparison of Current 3D NAND Chip and Cell Architectures
Jeongdong Choe, Senior Technical Fellow, TechInsights

Component-Level Characterization of 3D TLC, QLC, and Fast SLC NAND
Patrick Breen, Flash Characterization Engineer, IBM

Characterization of 3D NAND Flash Memories beyond 1GT/s
Rino Micheloni, VP & Fellow, Microsemi

Modeling and Mitigating Early Retention Loss and Process Variation in 3D Flash
Sauguta Ghose, Special Faculty Systems Scientist, Carnegie-Mellon University

Onur Mutlu, Professor, ETH Zurich and Carnegie Mellon University
Measuring the Difficulty of Programming 3D NAND
Vic Ye, Manager of NAND Flash Analysis Team, YeeStor Microelectronics

A Deep Dive into 3D NAND Silicon
Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Session Description:
3D NAND flash continues to advance and will soon dominate flash technology because of its lower cost and higher density. Issues in its widespread use include error-correction methods, manufacturing challenges, reliability, and lifespan. Manufacturers will need to continue to improve 3D processes to meet the needs of many applications. Situations requiring high reliability and extended lifetimes will require a great deal more development effort.
Intended Audience:
Product strategists, design engineers, engineering managers and directors, hardware and firmware architects, field application engineers, software developers, test engineers, system designers and analysts, storage engineers and managers

About the Organizer/Chairperson:
Jung Yoon is a Senior Technical Staff Member and Technology & Quality lead in IBM's Systems Supply Chain Organization. He leads a worldwide supply chain engineering team focusing on semiconductor technologies used across all IBM Systems and products. He is a recognized industry leading expert in DRAM, flash memory, SSDs, and semiconductor devices in general, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. He has presented papers at many conferences including several past Flash Memory Summits. He earned a PhD in materials science from Columbia University and an MS in materials science from University of California Berkeley. He serves on Flash Memory Summit’s Conference Advisory Board and has chaired key technical sessions over the last three years.

Shawn Adams is a Product Marketing Manager at Micron Technology, where he focuses on client SSD and NAND marketing. A 16-year veteran of the technology industry, he has led product development, strategy, and marketing for hardware and software portfolios. He has experience in both domestic and international markets and in a broad range of virtual market segments. Before joining Micron Technology, he worked for Healthwise, DBSI, and MPC. He holds an MBA from Northwest Nazarene University and a Bachelor’s in Business Administration from Idaho State University.

Wednesday, August 7th
3:20-5:45 PM
NVME-202-1: PCIe/NVMe Storage (NVMe Track)
Organizer + Chairperson: Rakesh Cheerla, Software Product Line Manager - SmartNICs, Intel

Organizer + Chairperson: Deepankar Das, CTO, Sureline Systems

Paper Presenters:
Building NVMe storage systems with PCIe 4.0 embedded switch IP
Sampath Banka, Senior Applications Engineer, PLDA

Building Storage Systems for the Burst Blockchain Platform
Olga Buchonina, Founder, ActionSpot

Daniel Jones, , Burst Software Developer
Getting the Most Out of QLC-based NVMe Storage
Andy Watson, Cloud Strategies for Startups, Amazon

FTL Flow Control for CFexpress Camera Hosts Using Large Sequential NVMe Reads
Vishwas Saxena, Technologist, Firmware Engineering, Western Digital

Applying NVMe in Embedded and Mobile Applications
Horace Chen, Director, Product Management, Phison Electronics

Sebastien Jean, Director of System Architecture, Phison Electronics
Thunderbolt 3: Bringing NVMe Storage to Consumer Computers
Shailendra Sinha, Sr. Business Development Manager, Intel

Physical Partitioning NVMe Controller Design for Improved SSD QOS Consistency
Gary Adams, Senior Director of Marketing, Silicon Motion

Session Description:
PCIe SSDs have rapidly emerged as the devices of choice in the enterprise because of their high speed, well-understood and widely used interface, and extensive support from major vendors. The NVMe standard for storage operations over PCIe offers a base platform comparable to those available for disk interfaces such as SAS and SATA. Furthermore, continuing advances in the underlying PCI Express interface (now in Version 4.0) offer a solid path for the future. Attention has now moved to implementing a wide range of essential system-level features in PCIe/NVMe. These include server storage platforms, standards for remote monitoring and management, high-availability features such as dual-porting, and virtual implementations for use with VMware.
Intended Audience:
Design engineers, hardware engineers, engineering managers, product and product marketing engineers, applications engineers, storage specialists and managers, storage technologists, systems engineers and analysts

About the Organizer/Chairperson:
Rakesh is a Solutions Planner at Intel, working with customer on SmartNIC solutions, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Wednesday, August 7th
3:20-5:45 PM
PMEM-202-1: Persistent Memory Part 4: Current Research in Persistent Memory (Persistent Memory Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Chairperson: Mark Carlson, Principal Engineer, Industry Standards, Kioxia

Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Paper Presenters:
Exploiting Managed Language Semantics to Mitigate Wear-Out in Persistent Memory
Shoaib Akram, , Ghent University

PMTest:-A Fast and Flexible Testing Framework for Persistent Memory Programs
Samira Khan, Assistant Professor, University of Virginia

Performance Characterization of a DRAM-NV Hybrid Memory Architecture for HPC
Brad Settlemyer, Scientist, Los Alamos National Laboratory

Hyperdimensional Computing & Cognitive Memory of the Pattern Kind
Gil Russell, Principal Analyst, WebFeet Research

Session Description:
Research on persistent memory has exploded over the last five years. Top universities, industrial research labs, and device manufacturers have scholars and staff dedicated to subjects like advances in memory devices or memory cell design, operating system and file system designs for non-volatile memories, and implications of non-volatile memories for scientific, big data, and high performance workloads. This session presents some of the most recent research by leaders in the field.
Intended Audience:
Application Architects and Designers, CTOs, System Engineers and Managers, HPC Engineers and Managers, Network and System Architects, System Integrators, Storage Engineers, Hardware and Software Design Engineers, and Product Planners

About the Organizer/Chairperson:
Mark A. Carlson, Principal Engineer, Industry Standards at Toshiba Memory, has more than 35 years of experience with Networking and Storage development and more than twenty year's experience with Java technology. He has spoken at numerous industry forums and events. He has chaired the SNIA Object Drive, Cloud Storage, NDMP and XAM SDK technical working groups and serves as Co-Chairman on the SNIA Technical Council.

Jonathan Hinkle is Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he creates and helps foster adoption of new data center systems architectures and technologies. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 20 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors, is Vice-Chair of Marketing and Chairs the Hybrid DIMM Task Group standardizing NVDIMMs. He also invented and drove first development of the EDSFF 1U Short (E1.S) NVMe drive, VLP DIMM and the NVDIMM Persistent Memory. He has over 30 patents granted or pending and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Wednesday, August 7th
3:20-5:45 PM
SOFT-202-1: Key-Value Store and Linux Technologies (Software Track)
Chairperson: Rich Fetik, CEO, Data Confidential

Organizer: Matias Bjorling, Director of Emerging System Architectures, Western Digital

Organizer: Renu Raman, VP Cloud Architecture and Engineering, VMware

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Approaching 10M I/Ops on a Single CPU Core
Ben Walker, Storage Solutions Architect, Intel

Distributed Key-Value Stores: Performance and Scalability for Flash Media
Richard Elling, Principal Arcihtect, Viking Enterprise Solutions

Smart Key-Value Storage for 3D XPoint and 3D QLC SSDs
Jack Zhang, Software Engineering Manager, Intel

Key-Value SSDs: Design Overview and Use Cases
Stanley Miao, Chief Engineer, Shannon Systems

Improved Flash Performance Using the New Linux Kernel I/O Interface
Vishal Verma, Performance Engineer, Intel

The Coming Revolution to Deploy Storage Processors for Application Acceleration
Mark Mokryn, Vice President of Product Architecture, Pliops

Session Description:
Key-value (K-V) store is a data storage technique that can be as simple as a hash table, and which is often a distributed storage technique. A popular K-V store system is RocksDB, which was developed by Facebook. The LSM-Tree (Log-Structured Merge Tree) technique is used by K-V databases such as RocksDB, MongoDB and Cassandra. Clusters rely on distributed K-V stores for service and configuration discovery, and for sharing consistent state across the members and clients and for distributed locking. This session will explore issues including the impact of network performance as well as different kinds of memory used to support Persistent Memory in order to facilitate effective K-V databases.
Intended Audience:
Software and hardware engineers and engineering managers; software specialists; systems analysts and engineers; product planners and managers; software managers; technical marketing engineers and managers.

About the Organizer/Chairperson:
Richard, CISSP, a systems architect, is the inventor and patent owner of applying storage intelligence for application acceleration, commonly referred to as Computational Storage. He is also a recognized storage and distributed system security expert. His firm is Data Confidential, which provides consulting, services, and technology licensing for the storage, embedded, IoT, and cloud spaces. Richard is the inventor of Data Confidential’s innovative technologies such as the Storage Firewall, secure container objects for cloud computing and secure IoT-to-cloud interactions, database-based credentialing for cloud access, a customizable storage controller architecture, built on a security framework, that accelerates application performance, and automated remote management including device and system monitoring as well as software and firmware provisioning and update. He is an expert at designing security into the real world, including embedded systems and devices as well as IT systems and data centers, and has broad product experience from design and development through market introduction and evangelism.

Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

Renu Raman is VP and Chief Architect of Cloud Architecture & Engineering at SAP. He is responsible for the architecture, design, and development of SAP’s groundbreaking HANA cloud infrastructure compute and storage. He also has devised a high-performance persistence architecture for in-memory databases which he described at a previous Flash Memory Summit. He was previously Founder/CEO at Unity Microsystems, a developer of memory virtualization technology. He also had a long career at Sun Microsystems where he focused on developing many highly successful SPARC processors and associated devices. He was also an executive-in-residence at Tallwood Venture Capital for several years. He earned an MSEE from Northwestern University.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Wednesday, August 7th
4:35-5:40 PM
AUTO-202B-1: Auto Roundtable (Automotive Applications Track)
Chairperson: Greg Basich, Associate Director, Automotive Infotainment and Telematics and Connected Mobility Services, Strategy Analytics

Organizer: Andy Marken, President, Marken Communications

Panel Members:
Panelist: Doug Mitchell, Product Marketing Engineer MPS, Cypress Semiconductor

Panelist: Ivan Ivanov, Distinguished Engineer, CoC Systems, Harman

Panelist: Bernd Niedermeier, Sales Director Automotive, Europe, Tuxera

Panelist: Michael Huonker, Engineer Advanced Head Unit, Daimler AG

Panelist: Alan Messer, Chief Strategy & Technology Officer, InnovationShift

Session Description:
The Storage/management challenges of the autonomous transportation ecosystem – What types of data do vehicles need when they are in motion from the physical environment – streets, roads, signals, signs – and in what form? How much of the data needs to be saved by the vehicle to “learn” so it can anticipate wants/needs of the people/products being transferred? Will most of the data be held in the cloud and used/discarded while the vehicle is in motion or should it be retained in the vehicle? Who will have access to that data and who will be responsible for keeping it safe, secure, private?
Intended Audience:
IoT, environment planners, developers, vehicle/system developers/planners, senior and engineering management for storage firms, Tier 1 and automotive producers. City, state transportation planners, solution providers

About the Organizer/Chairperson:
Greg is Associate Director with Strategy Analytics’ Automotive Infotainment & Telematics service and the company’s Automotive Connected Mobility service. He has been with Strategy Analytics for more than 5 years after a previous 13-year career as a business-to-business automotive journalist. At Strategy Analytics, Greg focuses on a number of topics, including connected car technologies and business models, automotive infotainment, mobility services such as car sharing and ride hailing, and automotive cyber security.

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Wednesday, August 7th
4:35-5:40 PM
CTRL-202B-1: Gen-Z Interface (Controllers Track)
Chairperson: Nathan Brookwood, Research Fellow, Insight 64

Organizer: Michael Krause, Lead Architect, Gen Z Consortium

Paper Presenters:
Gen-Z: Built-in Security for the Data-Centric World
Michael Krause, Lead Architect, Gen Z Consortium

Integrating the Gen-Z Interface into Your Applications
Bastien Heneffe, , PLDA

Session Description:
Gen-Z is a new data-access technology that provides high-speed, low-latency access to data and devices via direct-attached, switched, or fabric topologies. It utilizes memory-semantic communications to move data between memories on different components with minimal overhead. Gen-Z components use low-latency read and write operations to access data directly, and can move data with minimal application or processor involvement. Gen-Z delivers maximum performance in a modular architecture without sacrificing flexibility, and offers built-in, component-level security.
Intended Audience:
Hardware design engineers and managers, interface specialists, product planners, system engineers and managers, security architects

About the Organizer/Chairperson:
Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. During his 40 year career in the industry, Mr. Brookwood has experience with Micronics Computers, Intergraph, Convergent Technologies, Prime Computer, and Digital Equipment. He is a graduate of MIT and has taken classes at Harvard Business School.

Michael Krause is an HPE VP and Fellow responsible for interconnect technology development and strategy. Within the Gen-Z Consortium, Michael is the lead architect, has co-authored multiple specifications, and has described the architecture and technology in multiple industry forums including the Supercomputing (SC) conference and Persistent Memory Summit. He has previously worked on the creation and development of InfiniBand, iWARP, PCI Express, iSCSI, and FCoE. He has authored many specifications, co-chaired multiple technical workgroups, and acted as the HPE technical lead for many interface standards. He has worked on creating new technologies to advance computer, I/O, network, and storage architectures for over 30 years.

Wednesday, August 7th
4:35-5:40 PM
FTEC-202B-1: Annual Update on Flash Memory for Non-Technologists (Business/Marketing Track)
Organizer: Jay Kramer, President, Network Storage Advisors

Chairperson: Xinde Hu, Principal Engineer, Western Digital

Paper Presenters:
Annual Update on Flash Memory for Non-Technologists
George Crump, Chief Marketing Officer, StorONE

Session Description:
"Why a four-year-old child could understand this report. Run out and find me a four-year-old child. I can't make head nor tail out of it."- Groucho Marx in Duck Soup Do you feel like the storage industry in which you participate every day is passing you by? Are you not sure about the meaning of QLC, NVDIMM, RoCE, and SDS ? and afraid to ask? Do you think I/O determinism might have something to do with Darwin? If so, come let an expert speaker tell you what you really need to know about the very latest flash technologies. You?ll then be ready for the next round of revolutionary, disruptive, transformative, paradigm-shifting, and singularity-destroying advances that will come our way next year!
Intended Audience:
Marketing, sales, marketing communications, management, financial, public relations, legal, human relations, and other professionals who work in the storage industry. For those who want to have a picture of the latest technologies without getting into the gory details.

About the Organizer/Chairperson:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Xinde Hu is currently Director of System Architecture @eSSD at Western Digital. His responsibility includes creating, designing, and evaluating innovative system architecture concepts and implementations for the next generations of non-volatile memory based storage systems. Before joining Western Digital, Dr. Hu held architectural leader positions in STEC and STMicroelectronics. Dr. Hu has authored more than a dozen technical papers on data storage systems and has 38 patents issued. He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.

Wednesday, August 7th
4:35-5:40 PM
ENST-202B-1: Flash in Cloud Computing (Enterprise Storage Track)
Organizer + Chairperson: Jean Bozman, President, Cloud Architects

Organizer: Camberley Bates, Managing Director/Analyst, Evaluator Group

Paper Presenters:
The Future of Data-Center Infrastructure
Rajan Goyal, Chief Technology Officer, Fungible

IBM Storage: A Lighthouse for the Data-Driven Multicloud World
Eric Herzog, CMO VP Worldwide Storage Channels, IBM

2019: The Year of NVMe
Narayan Venkat, VP, Data Center Systems, Western Digital

Open Composable Disaggregated Infrastructures for the Edge
Mark Miquelon, Director of Platform Partner Alliances, Western Digital

Expanding Non-volatile Memory In Heterogeneous Systems Using the CCIX Standard
Ravi Kiran Gummaluri, , CCIX/Xilinx

Session Description:
Storage is a crucial part of any cloud, regardless of its type or ownership. Cloud service providers have become major players in buying flash storage technology, looking for more IOPS even at higher cost to provide better performance. Providers also advertise SSDs as being available to users at extra cost Cloud providers also like the higher reliability of flash memory and its operating efficiency (space, power, and cooling requirements). However, the extra cost remains an issue, particularly in the amounts needed in cloud environments, as do the issues of wear and endurance.
Intended Audience:
Cloud developers and managers; data center managers and engineers; hardware and software designers; network engineers and managers; communications and networking specialists; system architects and engineers

About the Organizer/Chairperson:
Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

Camberley Bates is Managing Director/Analyst at Evaluator Group, a leading analyst firm covering IT infrastructure and services. She has dedicated Evaluator Group to delivering unbiased in-depth research on information management and data storage - and helping customers use that research to develop the infrastructure they need. She is responsible for corporate leadership and coverage of go-to-market and channel strategies. She has over 20 years of executive experience leading sales and marketing teams at VERITAS, GE-Access, EDS, and IBM. Her achievements include developing a new market category at Copan Systems, restructuring channel programs at Veritas, and growing a new division of GE Access from $14 million to $500 million in revenue through a solution-practice methodology. Camberley is a frequent panelist and chairperson at such events as Interop and Flash Memory Summit, as well as being frequently quoted in the trade and technical press. She holds a BS degree in International Business from California State University Long Beach and executive certificates from Wellesley and Wharton School of Business.

Wednesday, August 7th
4:35-5:40 PM
INVT-202B-1: Flash Solutions for the Skyrocketing AI/ML Applications Market (AI/Machine Learning Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Paul Lassa, Principal Systems Engineer, ICH Consulting

Paper Presenters:
Flash Solutions for the Skyrocketing AI/ML Applications Market
Radoslav Danilak, CEO, Tachyum

Session Description:
The massive and growing demand for AI/ML applications across all industries is generating requirements for a broad spectrum of storage solutions across multiple use cases. In this rapidly changing environment, storage designers must address an entirely new series of challenges and problems. AI/ML programs require huge data sets and present increasingly challenging bandwidth and latency needs. Training, inference, and computation have their own unique issues, including large numbers of small files, and the emerging requirement for at least an order of magnitude increase in I/O performance from storage systems. New AI chips, as well as GPUs and other high performance processors, will put tremendous pressure on such systems to fill their pipelines and keep them busy. New architectures, new interconnects, and new memory types will all be needed to capitalize fully on opportunities in this multi-billion dollar market. The industry must rise to the occasion with new approaches and capabilities to unleash the full power of AI in tomorrow's marketplace.
Intended Audience:
Hardware and software design engineers, engineering managers and CTOs, storage engineers and managers, system engineers and managers, data center managers and engineers, product planners, AI/ML specialists

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Paul Lassa is a consultant with ICH Consulting where he is a versatile designer in engineering development of high-volume consumer products and storage. Technical strategy and project execution in hardware, system, ASIC / SoC, and embedded software development is a hallmark of his work, and he specializes in the desgin of performance-, power- and cost-optimized devices, from concept through volume deployment. Paul's passion is to deliver utility, performance, and craftsmanship in amazing and powerful electronic products and infrastructure. He is a member of IEEE-CNSV which has a booth on the show floor.

Speaker Bio: Dr. Radoslav Danilak has over 25 years of industry experience and over 100 patents designing state-of-the-art processing systems. In 2016, he founded Tachyum to disrupt markets by solving the processing performance plateau of nanometer class chips. Rado was founder and CEO of Skyera, a supplier of ultra-dense solid-state storage systems, acquired by WD in 2014. He won the 2013 Gold Tech Awards Circle for Emerging Company Executive of the Year. At Wave Computing, Rado architected the 10GHz Processing Element of a deep learning DPU. Rado was cofounder and CTO of SandForce acquired by LSI in 2011 for $377M. Rado pioneered enterprise and consumer MLC flash controllers and solved endurance limited by device physics. He was a chipset and GPU architect at nVidia, a CPU architect at Nishan Systems and Toshiba, and chief architect of 64b x86 CPU at Gizmo Tech. Besides being an industry leader in America, Dr. Danilak serves on the Slovak government's Innovation Advisory Board. He is also a member of the IDC Technical Computing Advisory Panel and the Forbes Technology Council, and a contributor to TechTarget. He earned a PhD in Computer Science and an MSEE from the Technical University of Kosice (Slovakia), where he taught compiler courses.

Wednesday, August 7th
4:35-5:40 PM
NEWM-202B-1: MRAM (New Memory Technologies Track)
Organizer + Chairperson: Dave Eggleston, Principal, Intuitive Cognition Consulting

Paper Presenters:
Overcoming Challenges in MRAM High-Volume Manufacturing
Kevin Moraes, Vice President, Applied Materials

STT-MRAM: A High Density Persistent Memory Solution
Sanjeev Aggarwal, Vice President of Technology, Everspin Technologies

Enabling MRAM for Applications
Danny Sabour, VP of Marketing, Avalanche Technology

MRAM: Memory for the Edge – And Beyond!
Jeff Lewis, SVP Business Development, Spin Memory

Session Description:
MRAM is rapidly entering the marketplace with the production of 64Mb standalone STT-MRAM, and the integration of embedded MRAM integrated with 28nm logic. The world?s fastest SSDs leveraging a MRAM cache have been announced, and non-volatile (NV) logic with MRAM elements has been proposed. The distinguished panelists will discuss the enormous range of MRAM applications, the current state of development and commercialization, and the disruption and opportunities MRAM creates.
Intended Audience:
Hardware design engineers, engineering managers, systems analysts and engineers, product and technology planners, CTOs, consultants, and memory specialists

About the Organizer/Chairperson:
Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Wednesday, August 7th
4:35-5:40 PM
NVME-202B-1: Leveraging NVMe-oF for Existing and New Applications (NVMe Track)
Session Sponsor: NVM Express
Chairperson: Sagi Grimberg, Principal Architect, Lightbits Labs

Organizer: Cameron Brett, Director SSD Product Marketing, Kioxia

Panel Members:
Panelist: Erez Scop, Sr Product Marketing Mgr, Mellanox

Panelist: Marcus Thordal, Director Technical Solutions, Broadcom

Panelist: Nishant Lodha, Product Marketing Manager, Marvell

Panelist: Bryan Cowger, VP Sales/Marketing, Kazan Networks

Session Description:
In this panel session we will discuss application and use case examples leveraging NVMe-oF. Which improvements should you expect with NVMe-oF and how does this apply to different types of applications? Learn from early adopters’ implementations of NVMe-oF, and what you need to consider when planning to migrate existing applications from SCSI to NVMe or deploying new applications with NVMe-oF. We will complete the session with a peek into the future of how NVMe-oF can enable new application use cases.
Intended Audience:
Hardware and software designers, engineering managers, storage designers, storage engineers and specialists, product planners, product managers and

About the Organizer/Chairperson:
Sagi Grimberg is a co-founder and principal architect at LightBits Labs, as well as an active Linux Kernel maintainer. He leads the protocol standardization for NVMe over TCP/IP and contributed all the open-source code. Sagi is also an active contributor to the Linux kernel as well as co-maintaining the NVMe subsystem and maintaining the iSER subsystem. He has been working on storage and networking technologies for over a decade. Before founding Lightbits Labs, Sagi led the Linux storage software activity at Mellanox. He has written technical articles, made conference and meetup presentations, and participated in other standards work. He earned his BSc in computer engineering cum laude from Bar-Ilan University (Israel).

Cameron Brett is the Director of Enterprise SSD Marketing at Toshiba America Electronic Components, Inc. where he manages a team of product line managers to drive product strategy and revenue growth. Cameron have over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.

Wednesday, August 7th
7:00-9:00 pm
IEEE AI, ML, and Storage Seminar (AI/Machine Learning Track)
Organizer + Chairperson: Kiran Gunnam, Distinguished Engineer - Machine Learning & Computer Vision, Western Digital

Paper Presenters:
Using RISC-V to Accelerate Machine Learning
Zvonimir Bandic, Sr Director of Next Generation Platform Technologies, Western Digital

Understanding Data at Storage Edge: An AI / ML Perspective
Ned Varnica, Director, Marvell Semiconductor

Analog Computing for AI/ML Using Embedded Flash
Seung-hwan Song, CTO and Co-Founder, ANAFLASH

Session Description:
This session covers how the RISC-V revolution is enabling new accelerators for machine learning (ML), the importance of the computation engines that understand the stored data, the new implementations of these computation engines at the storage edge, and a different approach than the digital logic-based computation units for artificial intelligence (AI) accelerators. This approach allows flash memory-based analog computing applications to reduce the cost and power of AI and ML accelerators. AI in its current nascent form of Artificial Narrow Intelligence is the third era of computing. The ML and AI workloads are computationally very expensive, and need radical compute, memory and storage architectures to reduce cost and power dissipation, and to enable wide-scale deployment both in the cloud and at the edge. At the same time, these architectures need to be scalable and flexible to be relevant for emerging AI and ML workloads. This seminar was organized by IEEE and ValleyML.ai, and is hosted as an FMS free event/open session. It features three talks from industry leaders who are working at the intersection of ML and AI with storage.
Intended Audience:
Data center engineers/managers; storage architects/managers; hardware and software infrastructure designers; systems engineers/analysts; engineering managers; marketing and product managers; solution providers and consultants; VARs, OEMs and system integrators.

About the Organizer/Chairperson:
Kiran Gunnam is a Distinguished Engineer for Machine Learning and Computer Vision at Western Digital, where he provides technical leadership in algorithms, architectures, and hands-on development for data and video analytics and autonomous systems. He was previously Technical Director for Algorithms and DSP at Velodyne LiDAR, a startup focused on computer vision for self-driving cars, and held engineering and R&D positions at Violin Memory, NVIDIA, Marvell, and Intel. An expert in IC implementation of communications and signal processing systems, he contributed several key innovations in advanced error correction systems which led to successful industry designs. Dr. Gunnam has over 60 patents with several others pending. He earned a PhD in Computer Engineering from Texas A&M University. He has presented at several previous Flash Memory Summits.

Speaker Bio: Ned Varnica received the B.S. degree in Electrical Engineering in 2000 from School of Electrical Engineering, University of Belgrade, Serbia, the M.S. degree in 2001 and Ph.D. in 2005 both from Harvard University, Cambridge, Massachusetts. Since 2005 he has been with Marvell Semiconductor in Santa Clara, California. He held short-term research positions at Maxtor Corporation, Shrewsbury, Massachusetts in 2002 and Lucent Bell Labs, Murray Hill, New Jersey in 2004. He spent the summer of 2003 as a visiting researcher at the University of Hawaii at Manoa, Honolulu. His research interests are in the areas of communication theory, information theory, channel and source coding and their applications to digital data storage and wireless communications. Dr. Varnica received the Best Student of the Class Award from the Department of Communications at the School of Electrical Engineering, University of Belgrade in 2000. He is a co-recipient, with A. Kavcic and X. Ma, of the 2005 IEEE Best Paper Award in Signal Processing and Coding for Data Storage.

Speaker Bio: Dr. Seung-hwan Song is a CTO and Co-Founder of Anaflash (www.anaflash.com), that develops embedded flash memory based AI solution since 2017. Previously, he has held various research and development positions at HGST (acquired by WD), Seagate, Qualcomm, Broadcom, and Samsung. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University, in 2004 and 2006, and the Ph. D. degree in electrical engineering (with a minor in biomedical engineering) from University of Minnesota, in 2013. Dr Song has 45+ US patents granted around SSD, NVM, and Flash memory, and has received a best paper award at IEEE ICC 2016 and a low power design contest award at IEEE ISLPED 2012.

Speaker Bio: Zvonimir Z. Bandić is a research staff member and senior director of Next Generation Platform Technologies at Western Digital in San Jose, Calif. He received his Bachelor of Science in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his Master of Science (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid-state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. He is also Board of Directors member of RISC-V foundation.

Wednesday, August 7th
7:00-9:00 pm
Persistent Memory Meetup (Persistent Memory Track)
Paper Presenters:
Session Description:
Join SNIA for a lively gathering of Persistent Memory enthusiasts to share results of the two day FMS Persistent Memory Hackathon, where software developers gathered in a live coding exercise to better understand the various tiers and modes of persistent memory and explore existing best practices. All are welcome!
Intended Audience:
Data center engineers/managers; storage architects/managers; hardware and software infrastructure designers; systems engineers/analysts; engineering managers; marketing and product managers; solution providers and consultants; VARs, OEMs and system integrators.

About the Organizer/Chairperson:
Thursday, August 8th
Thursday, August 8th
8:30-9:35 AM
COMP-301A-1: Computational Storage - Controllers & Technology (Computational Storage Track)
Session Sponsor: SNIA
Organizer: Thad Omura, VP Marketing – Flash Business Unit, Marvell

Organizer: Stephen Bates, CTO, Eideticom

Chairperson: Tim Stammers, Senior Analyst, 451 Research

Organizer: Scott Shadley, VP Marketing, NGD Systems

Paper Presenters:
Transforming Storage Controllers With Low-Cost, Low-Power Compute
Neil Werdmuller, Director, Storage Solutions, Arm Holdings

Jason Molgaard, Principal Storage Solutions Architect, Arm
Using Native NVMe-oF SSDs to Advance Computational Storage
Shahar Noy, Sr Director Product Marketing, Marvell

Implementing Computational Storage with Existing SSD Controller Resources
Ramyakanth Edupuganti, Staff Applications Engineer, Microchip

Session Description:
Computational Storage is a paradigm shift in data center infrastructure that addresses the market demand to process huge datasets with minimal latency. Computational Storage use cases range from database, big data, AI/ML and Edge applications where there are traditionally large gaps in compute vs. the amount of data that needs to be processed. The framework for Computational Storage is driven by SNIA and the NVM Express standards groups. You will hear from vendors who will discuss their current and future offerings and end results from real usage models with real customer discussions.
Intended Audience:
Data center infrastructure and storage technologists eager to optimize performance, cost, power, and delivery of optimized application-level results that are currently bottle-necked by traditional compute, memory and storage architectures.

About the Organizer/Chairperson:
Thad Omura is an accomplished technology business executive that has been instrumental in driving startups to IPO and high-value acquisitions, while also having public company experience as a corporate executive. Since April 2015, Thad has served as EVP of Marketing and Operations for ScaleFlux responsible for all business, marketing, operations and expanding the growth opportunities for Computational Storage. Prior to ScaleFlux, Thad was VP of Product & Customer Management for Seagate Technology’s Flash and SSD business. He stepped into that role through Seagate’s acquisition of the LSI Flash products in 2014, including SandForce Flash Processors, and PCIe SSDs. Thad was an early executive at SandForce in 2008 as VP of Marketing, and remained with the organization through the LSI and Seagate acquisitions. Prior to SandForce, Thad was with Mellanox Technologies as VP of Product Marketing, and helped drive the company to an IPO in 2007 based on success of its industry-leading networking solutions. Prior to Mellanox, Thad served in various marketing and sales roles at Motorola SPS, Marvell, Galileo Technology, and Quality Semiconductor. Thad holds a BS degree in EECS from the UC Berkeley.

Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Tim Stammers is a Senior Analyst at 451 Research, where he covers flash- and disk-based primary storage. Before joining 451 Research in 2013, Tim was Senior Storage Analyst at Ovum. He has over 20 years of experience as an IT industry analyst and journalist, and has also worked as a gas turbine development engineer at Rolls-Royce, and a mainframe systems engineer at the London Electricity Board.

Scott Shadley is the VP Marketing at NGD Systems, a developer of computational storage. He focuses on brand, go-to-market, and product management and development, as well as customer adoption, acquisition, and support. He was previously Principal Technologist at Micron, where he focused on future technologies such as form factors, interfaces, and connectivity options with a particular emphasis on giving customers more freedom with their uses. He has spent over 20 years in the semiconductor and storage industries, and his efforts have been important in developing and marketing products with over $300M revenue. He has also been active as a conference presenter and organizer, particularly at Flash Memory Summit. He earned an MBA from the University of Phoenix and a BS in Semiconductor Device Physics from Boise State University (ID).

Thursday, August 8th
8:30-9:35 AM
FSOL-301A-1: Flash Solutions for Oracle (Flash Solutions Track)
Organizer: Jay Kramer, President, Network Storage Advisors

Chairperson: Jillian Coffin, VP/Publisher Storage Virtualization and Cloud, TechTarget

Panel Members:
Panelist: Dave Montgomery, Platforms Marketing Director, Western Digital

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Michael Bradburn, Lead Senior Technical Solutions Architect, Cisco

Panelist: Erik Kaulberg, Vice President, Infinidat

Session Description:
All enterprise storage is not the same. Oracle has unique performance characteristics along with customer requirements with SLAs that can achieve the highest levels of availability, capacity optimization and scalability. Find out the unique capabilities of these vendors and how they meet these requirements for enterprise database deployment.
Intended Audience:
Channel Marketing Managers, Distributors, VARs, System Integrators, OEMs and Solution Providers, Marketing Professionals, Sales Representatives and Managers, Business Development Executives, PR Specialists, Product and Project Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Outsourcers, Financial Analysts and Executives, Venture Capitalists, Media Representatives.

About the Organizer/Chairperson:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Jillian Coffin is VP/Group Publisher for TechTarget’s Storage, Cloud, and Data Center business units. She oversees the editorial, audience development, and sales and consulting efforts across website communities including SearchStorage.com, SearchCloudComputing.com, and SearchITchannel.com. Jillian has been a leader in the data storage community for 12+ years, sharing purchase intent data with storage vendors who want to maximize growth opportunities. She has helped establish TechTarget as the leading source of independent enterprise storage and flash technology content on the web and helped make it into a trusted resource to aid IT and business leader decision making. The Websites she manages have achieved first-page in ranking in organic search across many specific topics, and her market consulting activities are vital to a wide range of companies.

Thursday, August 8th
8:30-9:35 AM
INVT-301A-1: Memory-Centric Computing in the Big Data Era (Enterprise Applications Track)
Chairperson: Mark Seligman, Principal, InPredict

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Memory-Centric Computing in the Big Data Era
Onur Mutlu, Professor, ETH Zurich and Carnegie Mellon University

Session Description:
Ever-increasing amounts of data create a major challenge for computing systems. How can data centers meet the current and future demands of real-time analysis, AI/ML, image and video processing, cloud computing, graph analytics, genomics, and other data-intensive applications at reasonable cost? A key problem is that simply moving data around, such as from storage/memory to a CPU or from local sources to a cloud, can take a very long time. Just try moving a petabyte to another computer or to backup! Or try copying a few huge pages within main memory! Promising ways to reduce the number and size of large data transfers include: 1) adding processing capabilities to storage/memory devices to handle common functions locally, and 2) using new memory technologies to accelerate data-intensive applications and operations. The resulting in-memory processing designs can provide high-bandwidth, low-latency, low-energy, and low-cost solutions across a wide range of applications.
Intended Audience:
Data center managers and engineers, applications specialists, systems engineers, storage engineers and managers

About the Organizer/Chairperson:
Mark Seligman has over 20 years of experience in the development of compiler back-ends for high-performance chip and system vendors, as well as application tuning for GPUs and multicore processors (CPUs). He has over ten years of experience in computational statistics and workflow acceleration for scientific applications, and is a member of IEEE-CNSV which has a booth on the show floor. As a consultant with InPredict, Mark's projects include smoothing the transition from a working prototype or in-house solution to a scalable, high-performance application. He offers refactoring and rescaling services, as well as consultation, to facilitate redeployment, and he specializes in parallelization, whether across a cloud implementation or within a GPU. Mark can also tailor applications to run in embedded environments and SOCs.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Speaker Bio: Onur Mutlu is a Professor of Computer Science at ETH Zurich and a faculty member at Carnegie Mellon University. His current research interests are computer architecture, systems, hardware security, and bioinformatics. Several techniques he and his collaborators have invented have influenced industry and have been employed in commercial microprocessors and memory/storage systems. . He started the Computer Architecture Group at Microsoft Research, and held product and research positions at Intel, Advanced Micro Devices, VMware, and Google. He has received an IEEE Computer Society Young Computer Architect Award, an Intel Early Career Faculty Award, a US National Science Foundation CAREER Award, and many best paper or "Top Pick" awards at computer systems, architecture, and hardware security events. He is an ACM Fellow, an IEEE Fellow, and an elected member of the Academy of Europe (Academia Europaea). He earned a PhD and MS in electrical and computer engineering from the University of Texas at Austin

Thursday, August 8th
8:30-9:35 AM
INDT-301A-1: CTO Panel (Industry Trends Track)
Organizer + Chairperson: Rob Peglar, President, Advanced Computing and Storage

Panel Members:
Panelist: Richelle Ahlvers, Storage Mgmt Software Architect, Broadcom

Panelist: Stephen Bates, CTO, Eideticom

Panelist: Jonathan Hinkle, Principal Researcher, Lenovo

Panelist: Wendy Elsasser, Principal Design Engineer, ARM

Session Description:
CTOs and their staff do not have an easy life in the flash memory industry. Things are changing rapidly, and the road ahead is almost impossible to discern or understand. So what are these people thinking currently? What do they see as basic trends that will determine the course of nonvolatile memory technology? And what do they think are just transient issues that will soon be forgotten? What prized techniques can they recommend (such as crystal balls, Ouija boards, and tarot cards) for gauging the future?
Intended Audience:
Hardware and software design engineers; engineering managers; marketing and product marketing engineers and managers; systems analysts and engineers; storage managers and engineers

About the Organizer/Chairperson:
Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Thursday, August 8th
8:30-9:35 AM
MEDE-301A-1: Volumetric: True 3D Capture Is Upon Us (Media & Entertainment Track)
Organizer: Andy Marken, President, Marken Communications

Chairperson: Allan McLennan, Chief Executive / Analyst, PADEM Media Group

Panel Members:
Panelist: Andrew Cochrane, , Filmmaker

Panelist: Andrew Shulkind, , Cinematographer

Session Description:
Volumetric video, LiDAR, photogrammetry, and even light fields are storming onto the stage as they exit the R&D lab and move into production. This session will walk through the technologies, the strengths/weaknesses, and show examples of their use in real world productions. The technology produces creative/technical challenges many orders of magnitude beyond 4k vs. 8k and VR/volumetric creation can “quickly and easily” produce more than 10TB of content data that must be instantly captured, stored, used, saved.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Allan McLennan is a Technologist/Analyst of the US based PADEM Media Group, one of the world’s recognized voices* in the advancement of IP (web/broadband/mobile) based television/OTT/VOD, video streaming and AI/ML engagement through connected devices. Allan is an established IP market technology executive in next generation digital media innovations/networks, consumer products and market capitalization deployments worldwide. His current work with global corporations and innovators addresses the deployments and acquisitions across multi-device IP networks, OTT/TV/VOD network programming and multi-platform video distribution. He actively participates in the advancement of data analytics, advanced advertising (ACR, RTB, Programmatic APIs) and the overall revision of the entertainment/media multi-platform video consumption models being explored today. He has participated in the creation/innovation, packaged and/or sold multiple new offerings throughout the world in 17 countries with close to four billion households as both a corporate executive and innovator. Allan has held five patents in targeted advertising and worked with corporations such as Ericsson, Siemens, Microsoft, TIVO, COMCAST, APPLE, Universal, Disney and more involving the advancement of IP/digital media distribution. Additionally, he was the founding AMI divisional president of the US publicly traded entertainment data analytics corporation – RENTRAK (NASDAQ: RENT), serving 100% of the studio and network marketplace.

Thursday, August 8th
8:30-9:35 AM
NEWM-301A-1: Life Beyond Flash - New Non-Volatile Memory Technologies (New Memory Technologies Track)
Organizer: Dave Eggleston, Principal, Intuitive Cognition Consulting

Chairperson: Jim Cantore, President, JLC Associates

Paper Presenters:
Emerging Memories Find New High-Performance Applications
Jim Handy, Director/Chief Analyst, Objective Analysis

Tom Coughlin, President, Coughlin Associates
DDR5 NVRAM: A Non-Volatile DRAM Replacement Specification
Bill Gervasi, Principal Systems Architect, Nantero

Challenges and Strategies for Mass Adoption of Emerging Non-Volatile Memories
Simone Bertolazzi, Engineer Analyst, Yole Developpement

When It Comes to Emerging Embedded Memories, One-Size-Doesn't-Fit-All!!
Jack Guedj, Co-Founder and CEO, Numem

Computing In Memory with tri-gate SONOS Nonvolatile Multi-level Memory
Yasuhiro Taniguchi, CTO, Floadia

Session Description:
Is there life after flash? Or will flash memory keep improving and dominate all NVM technology into the next decade? The panelists will peer into their crystal balls, and provide perspective on the great non-volatile beyond. They will provide insight and analysis on technology trends, disruption, singularities, product roadmaps and completion dates, and other memory issues that may go beyond human predictive capabilities. Bring your opinions, comments or Ouija board, tarot cards, fortune cookies, astrological instruments, tea leaves, or magic lamps and join in the discussion!
Intended Audience:
Anyone who wants to guess about the long-term future of non-volatile memory technology (say, out beyond two or three years).

About the Organizer/Chairperson:
Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Jim Cantore has been the President and Chief Analyst with JLC Associates, a high technology consulting firm since September 2003. Mr. Cantore consults in high technology, business development, strategic marketing and market intelligence to financial and high technology companies. He has over 29 years' combined experience in semiconductor, computer and solar industries. Mr. Cantore specializes in microprocessors, Intel; computer virtualization, graphics, nVidia, storage and network processors; DSP; power and analog chips; semiconductor business cycle analysis; DRAM; 3D NAND ReRAM, Storage Class Memory, SCM and NOR flash; solid state drives, SSD based systems; advanced non-volatile memory; STTRAM; CBRAM; 3D-Xpoint; Micron; Samsung; SK Hynix; Wafer procurement and supply, polycrystalline silicon, thin film PV; intellectual property; wafer foundry; 450 mm wafer fabs; semiconductor process roadmaps; EUV; optical critical dimensioning; front-end and back-end semiconductor manufacturing capital equipment; AMAT, ASML, LRCX; wafer scale and TSV packaging; back end assembly, OSATs; Data Center storage systems; Cloud technology; laptop PCs; tablet PCs; smart phones; advanced integrated fan-out wafer-level packaging (FO-WLP); advanced motion control; PCB laminate industry; Flexible PCBs; machine vision; flexible electronics and advanced ceramics semiconductor applications; motion control; wearable electronic devices; Cloud Systems; ioT.

Thursday, August 8th
8:30-10:50 AM
AIML-301-1:Using AI/ML for Flash Performance Scaling, Part 1 (AI/Machine Learning Track)
Chairperson: Ali Keshavarzi, Adjunct Professor, Stanford University

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
A Scalable AI Data Pipeline for Storing and Processing Ingested Data
Sanhita Sarkar, Global Director, Analytics Software Development, Western Digital

Accelerating NVM to GPU Transfer Rates Using PCIe Fabrics and Logical Volumes
Vincent Hache, Principal Applications Engineer, Microsemi

Managing Massive Input Data in Flash for AI and Deep Learning Applications
Dejan Kocic, Sr. SE, NetApp

ReRAM for Implementing Neural Network Synapses
Amir Regev, CTO, Weebit-nano

Exploring the Impact of System Storage on AI/ML Workloads via MLPerf
Wes Vaske, Principal Solutions Engineer, Micron Technology

Search Acceleration and Learning at the Edge with Crossbar ReRAM
Sylvain Dubois, , Consultant

Session Description:
AI and machine learning (ML) are being used in many areas of the NVM industry. For example, various storage device health indicators can be monitored, and an ML model can be used to identify the drive's health by utilizing a deep neural network. However, such techniques require processing power and adequate storage apart from the storage that they are monitoring, and a Deep Learning (DL) approach requires the subsystem to learn by itself. This is just a sampling of the kind of issues addressed by the talks in this track.
Intended Audience:
Datacenter engineers/managers; storage architects/managers; hardware and software infrastructure designers; systems engineers/analysts; engineering managers; marketing and product managers; solution providers and consultants; VARs, OEMs and system integrators.

About the Organizer/Chairperson:
Ali Keshavarzi, Ph.D. is an Adjunct Professor in Electrical Engineering at Stanford Univ., is involved in scholarly research, and is an advisor to Stanford SystemX IoE Research. He works with DARPA as an advisor and subject matter expert on the Electronic Resurgence Initiative (ERI) and is a member of DARPA MTO Investor Working Board (IWB). Ali is a principal and the founder of Leading Edge Research LLC, Los Altos, CA. Dr. Keshavarzi is a technology visionary and a leader who has been at the forefront of technology innovation with a track record of delivering critical process technologies, devices, circuits, SoCs, and modules to the semiconductor industry. He was the VP of R&D and a Fellow at Cypress Semiconductor, and he held various positions at Intel, TSMC, and GLOBALFOUNDRIES in a variety of technical and leadership roles over 25 years. Ali was a visiting research professor at UC Berkeley from 2017 to 2018.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Thursday, August 8th
8:30-10:50 AM
CTRL-301-1: Flash Controller Design Innovations (Controllers Track)
Chairperson: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Paper Presenters:
Tunable Flash Translation Layer Improves Storage System Performance
Chris Bergman, Sr Firmware Architect, Burlywood

Improving the locality of generalized integrated interleaved codes
Xinmiao Zhang, Associate Professor, Ohio State University ECE Department

A novel HW/FW co-designed SSD controller archtecture to boost up SSD performance
Wei Xu, Vice President, Maxio Technology

Raw Access to Flash Memory Meets Special System Needs
Kenneth Pillay, CEO and Director, YALLIP

Table-less Controllers for Persistent Memory in Datacenter Applications
Bernard Shung, President, Wolley

Session Description:
NAND flash technology has produced continuously new records in the last years which have consolidated its position as the leading type of nonvolatile memory. Despite all advances, flash management demands increasing efforts from controllers. How can we unleash the full NAND flash bandwidth with minimal controller overhead? Can firmware designs keep up? Where do application and workload profiles meet controller design options? What controller breakthroughs are required for even faster non-volatile technologies such as MRAM, RRAM, 3D XPoint, and memristors? There are many possibilities out there, but the investment is high and the simple concepts have already been developed.
Intended Audience:
Design engineers, engineering managers and directors, hardware and firmware architects, field application engineers, software developers, test engineers, system designers and analysts, storage engineers and managers

About the Organizer/Chairperson:
Roman Pletka is a research staff member for cloud storage and security at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He has published 20 articles and obtained over 50 patents in security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over ten years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).

Thursday, August 8th
8:30-10:50 AM
NVME-301-1: PCIe/NVMe Technology Update (NVMe Track)
Organizer + Chairperson: Deepankar Das, CTO, Sureline Systems

Organizer + Chairperson: Rakesh Cheerla, Software Product Line Manager - SmartNICs, Intel

Paper Presenters:
The New Generation of Storage: PCI Express 4.0 and 5.0
Debendra Das Sharma, Chair, PCI-SIG Marketing Workgroup, Intel

Extend the usage of Namespace: managing multi-media to improve app performance
Ron Yuan, R&D Vice President, Memblaze

Offloading the NVMe SSD Datapath to Intelligent Controllers
Ziv Serlin, VP System Architecture, E8 Storage

VMware's NVMe Support, and Forward Looking Plans
Murali Rajagopal, Storage Architect, VMware

The Interconnect Dilemma: Next-gen Fabrics
Niraj Mathur, VP of Product, GigaIO Networks

Scott Taylor, Director Software Engineering, GigaIO
Video Processing Secrets for NVMe
Daniel Zhou, ,

NVMe Use Case: Surveillance Video Processing
Tao Zhong, CTO, NETINT Technologies

Session Description:
PCIe SSDs have rapidly emerged as the devices of choice in the enterprise because of their high speed, well-understood and widely used interface, and extensive support from major vendors. The NVMe standard for storage operations over PCIe offers a base platform comparable to those available for disk interfaces such as SAS and SATA. A further step in its acceptance is the development of a wide variety of added facilities. They include more efficient I/O frameworks (typically open-source), solutions for performance and power tradeoffs, ways to handle latency problems, and specially designed software such as file systems. Obviously, such added facilities grow the PCIe/NVMe ecosystem, further encouraging developers to use it in their storage systems.
Intended Audience:
Design engineers, hardware engineers, engineering managers, product and product marketing engineers, applications engineers, storage specialists and managers, storage technologists, systems engineers and analysts

About the Organizer/Chairperson:
Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Rakesh is a Solutions Planner at Intel, working with customer on SmartNIC solutions, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Thursday, August 8th
8:30-10:50 AM
NVMF-301-1: Demystifying NVMe over Fabrics (NVMe-oF Track)
Organizer + Chairperson: Vishal Shukla, Senior Director, Mobileiron

Paper Presenters:
Designing Fabric accelerators for NVMe storage arrays by using MRAM
Pankaj Bishnoi, Director of Applications, Everspin

A Journey into NVMe-oF: Options, Trade-offs, and Challenges
Ihab Hamadi, Fellow, Western Digital

Achieving Scalable 5M+IOPS on NVMe/FC with Ultra Low Latency
Jayamohan Kallickal, Sr Principal Engineer, Broadcom

Wenhua Liu, Staff 2 Engineer, VMware
End to End Gen4 NVMe-oF through PCIe Fabric and Smart NIC
Brian Pan, General Manager, H3 Platform

Why cache in DRAM if you use NVMe-oF
Radu Stoica, Researcher, IBM

Fabrics/NVMe-oF's Storage's New Magic Wand
Arindam Sarkar, Director - Storage Engineering, MSys Technologies

NVMe-oF SAN telemetry with programmable switches
Surendra Anubolu, Distinguished Engineer, Broadcom

Leading Early Adopter Markets for NVMe-oF
Walter Hinton, CMO, Pavilion Data Systems

Session Description:
The new NVMe SSD interface can be connected across a Fabric. In fact it can be connected across lots of different fabrics: Ethernet (3 approaches), Fibre Channel, InfiniBand, and PCIe to date. Data Centers want to share storage readily among multiple compute nodes and be able to perform clustering, failover, and other system-wide operations at NVMe SSD speeds. NVMe over Fabrics (NVMe-oF) is the solution. This talk will describe the technology in its many forms. Describe use cases, for both Enterprise and cloud, where it is being applied. Then finish with potential future directions it is heading.
Intended Audience:
Design engineers, hardware engineers, engineering managers, product and product marketing engineers, applications engineers, storage specialists and managers, storage technologists, systems engineers and analysts

About the Organizer/Chairperson:
Vishal Shukla is Director Ethernet Switch Business at Mellanox Technologies. A thought leader in networking, cloud, and deep learning solutions, he has written multiple papers, authored books, and obtained over 15 patents. He has over 10 years proven experience in developing and leading global teams in functions such as technical sales, solutions architecture, technical alliances, and customer support. He has worked for Mellanox, NVXL Technologies, IBM Cloud, Blade Network Technologies, Cisco, and Nortel. He earned an MBA from Duke University and a BS in Information Technology from Uttar Pradesh Technical University (India).

Thursday, August 8th
8:30-10:50 AM
SOFT-301-1: Kubernetes and Cloud Software (Software Track)
Organizer + Chairperson: Matias Bjorling, Director of Emerging System Architectures, Western Digital

Organizer: Brian Berg, President, Berg Software Design

Organizer: Renu Raman, VP Cloud Architecture and Engineering, VMware

Paper Presenters:
Leveraging Linux's Native Storage Functionalities via Open-Source
David Hay, Cluster Engineer, LINBIT

Autonomous Kubernetes Flash Management with Multi-Cloud Application Awareness
Venkat Ramakrishnan, VP Engineering, Portworx

Running Stafeful Workloads on Flash and Kubernetes: Challenges and Solutions
Jagadish Mukku, Sr Architect, Robin.io

Co-Design Software and Hardware for SSD Storage
James Liu, Storage Architect, Alibaba

Data Orchestration for Kubernetes Stateful Tier-1 Primary Workloads
Marc Fleischmann, President & Founder, Datera

Session Description:
Kubernetes is an open source system for management and automation of containerized applications. Container Storage Interface (CSI) provides a standard plug-in interface to expose block and file storage systems to container applications. OpenSDS (Linux Foundation project) provides a unified software-defined storage control plane for managing wide variety of storage backends such as Ceph, DRBD, NVMeoF targets. OpenSDS provides CSI based integration to expose flash block storage to Kubernetes container workloads. Running stateful workloads such as databases and big data on Kubernetes is hard. However, there is a universal need to complement its application-driven compute orchestration with complementary data orchestration. Storage stacks need to support more than the basic ability to provision storage volumes to Pods inside which stateful workloads run. Stateful workloads are performance-sensitive, requiring the correct binding between apps and flash storage to ensure predictable performance and higher utilization in a multi-tenant consolidated Kubernetes environment. The design of Kubernetes makes storage and data management very difficult for deploying stateful workloads such as Hadoop, Oracle, Splunk, Mongo, Elastic, SAP HANA, etc. This session will explore these and many other issues that are critical for supporting the Cloud.
Intended Audience:
Software and hardware engineers and engineering managers; software specialists; systems analysts and engineers; product planners and managers; software managers; technical marketing engineers and managers.

About the Organizer/Chairperson:
Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Renu Raman is VP and Chief Architect of Cloud Architecture & Engineering at SAP. He is responsible for the architecture, design, and development of SAP’s groundbreaking HANA cloud infrastructure compute and storage. He also has devised a high-performance persistence architecture for in-memory databases which he described at a previous Flash Memory Summit. He was previously Founder/CEO at Unity Microsystems, a developer of memory virtualization technology. He also had a long career at Sun Microsystems where he focused on developing many highly successful SPARC processors and associated devices. He was also an executive-in-residence at Tallwood Venture Capital for several years. He earned an MSEE from Northwestern University.

Thursday, August 8th
9:45-10:50 AM
BMKT-301B-1: VC Forum (Business/Marketing Track)
Organizer + Chairperson: Wayne Rickard, CEO, Terecircuits

Panel Members:
Panelist: Eric Buatois, , Benhamou Global Ventures

Panelist: John Rotchford, Managing Director, SASI

Panelist: Angel Orrantia, General Partner, Vonzos Partners

Panelist: Chris Rust, Founder & General Partner, Clear Ventures

Panelist: Shahin Farschi, Partner, Lux Ventures

Session Description:
The flash memory area is bursting out all over with many startups and high-priced acquisitions. What are the short-term and long-term investment prospects? What are VCs looking for in funding flash storage companies and what do they think will be the key factors in achieving success? Is there enough room for all the current flash storage companies? Do the current and projected revenues justify the valuations? Which companies are most likely to succeed? When (if ever) will MRAM, RRAM, and other alternative NVM technologies be ready for prime time? What effect will the current industry storage industry slowdown have? How do such current hot topics as NVMe (and NVMe over fabrics), persistent memory, NVDIMM, and 3D XPoint? look as investment prospects?
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Wayne Rickard is VP of Business Development at Radian Memory Systems. Prior to taking on this role, Wayne was Radian’s first advisor and helped build out the company’s extended leadership team and strategic initiatives. Wayne has been a pioneer in storage networking, working hands on with the early versions of fibre channel and initiating standardization efforts through industry consortiums such as SNIA and FCIA. He was Co-Founder and held VP of Engineering and CTO roles at Gadzoox Networks, an early leader in fibre channel SAN switches. As a Director of Engineering at Emulex, Wayne led an Advanced Technology group that developed the industry’s first fibre channel HBA. He has held VP and division Chief Technologist positions at Seagate and been an Advisory Board member at PMC Sierra.

Thursday, August 8th
9:45-10:50 AM
COMP-301B-1: Computational Storage - Deploying Solutions (Computational Storage Track)
Session Sponsor: SNIA
Organizer: Stephen Bates, CTO, Eideticom

Chairperson: Tim Stammers, Senior Analyst, 451 Research

Organizer: Scott Shadley, VP Marketing, NGD Systems

Organizer: Thad Omura, VP Marketing – Flash Business Unit, Marvell

Paper Presenters:
Computational Storage Solves Big Problems with Big Data
Eli Tiomkin, VP Business Development, NGD Systems

Computational Storage Is the Answer for Huge Data and Deep Problems
Andrew Maier, Software Engineer, Eideticom

Bring Intelligence to Your Database Storage
Tong Zhang, Chief Scientist, ScaleFlux

Session Description:
Computational Storage is a paradigm shift in data center infrastructure that addresses the market demand to process huge datasets with minimal latency. Computational Storage use cases range from database, big data, AI/ML and Edge applications where there are traditionally large gaps in compute vs. the amount of data that needs to be processed. The framework for Computational Storage is driven by SNIA and the NVM Express standards groups. You will hear from vendors who will discuss their current and future offerings and end results from real usage models with real customer discussions.
Intended Audience:
Data center infrastructure and storage technologists eager to optimize performance, cost, power, and delivery of optimized application-level results that are currently bottle-necked by traditional compute, memory and storage architectures.

About the Organizer/Chairperson:
Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Tim Stammers is a Senior Analyst at 451 Research, where he covers flash- and disk-based primary storage. Before joining 451 Research in 2013, Tim was Senior Storage Analyst at Ovum. He has over 20 years of experience as an IT industry analyst and journalist, and has also worked as a gas turbine development engineer at Rolls-Royce, and a mainframe systems engineer at the London Electricity Board.

Scott Shadley is the VP Marketing at NGD Systems, a developer of computational storage. He focuses on brand, go-to-market, and product management and development, as well as customer adoption, acquisition, and support. He was previously Principal Technologist at Micron, where he focused on future technologies such as form factors, interfaces, and connectivity options with a particular emphasis on giving customers more freedom with their uses. He has spent over 20 years in the semiconductor and storage industries, and his efforts have been important in developing and marketing products with over $300M revenue. He has also been active as a conference presenter and organizer, particularly at Flash Memory Summit. He earned an MBA from the University of Phoenix and a BS in Semiconductor Device Physics from Boise State University (ID).

Thad Omura is an accomplished technology business executive that has been instrumental in driving startups to IPO and high-value acquisitions, while also having public company experience as a corporate executive. Since April 2015, Thad has served as EVP of Marketing and Operations for ScaleFlux responsible for all business, marketing, operations and expanding the growth opportunities for Computational Storage. Prior to ScaleFlux, Thad was VP of Product & Customer Management for Seagate Technology’s Flash and SSD business. He stepped into that role through Seagate’s acquisition of the LSI Flash products in 2014, including SandForce Flash Processors, and PCIe SSDs. Thad was an early executive at SandForce in 2008 as VP of Marketing, and remained with the organization through the LSI and Seagate acquisitions. Prior to SandForce, Thad was with Mellanox Technologies as VP of Product Marketing, and helped drive the company to an IPO in 2007 based on success of its industry-leading networking solutions. Prior to Mellanox, Thad served in various marketing and sales roles at Motorola SPS, Marvell, Galileo Technology, and Quality Semiconductor. Thad holds a BS degree in EECS from the UC Berkeley.

Thursday, August 8th
9:45-10:50 AM
ENAP-301B-1: How Flash Will Transform Enterprise Applications (Enterprise Applications Track)
Organizer: Tom Burniece, President, Burniece Consulting Services

Chairperson: Rob Peglar, President, Advanced Computing and Storage

Panel Members:
Panelist: Mike Gluck, Principal, Gluck Enterprises

Panelist: Peter Nam, CTO, FADU

Panelist: Chadd Kenney, VP Products and Solutions, Pure Storage

Panelist: Josh Goldenhar, VP Product Marketing, LightBits Labs

Session Description:
Flash memory has already increased the performance of enterprise applications tremendously. However, we have just begun to see the long-term effects. Flash will find even more uses with all-flash arrays dominating local storage, server-side and storage-side caches providing higher performance, and even cold storage moving to flash rather than disk or tape. Real-time analytics will be a key area of interest with both computational performance and access to big data being essential. New developments such as flash on the memory bus and persistent and storage-class memory will maker flash even more important. Data centers will need to take full advantage of flash memory at every level ? in computers, in servers, in networks, and in storage systems.
Intended Audience:
Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Storage Managers, Network Engineers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, Application Administrators, Database Administrators, Application Developers, and Data Center Architects

About the Organizer/Chairperson:
Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Thursday, August 8th
9:45-10:50 AM
FSOL-301B-1: Flash Solutions for SAP (Flash Solutions Track)
Chairperson: Jillian Coffin, VP/Publisher Storage Virtualization and Cloud, TechTarget

Organizer: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Saroj Mohapatra, SAP SME, Cisco

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Erik Kaulberg, Vice President, Infinidat

Panelist: Matt Morris, Sr Solutions Marketing Manager, Western Digital

Session Description:
Storage for SAP customer environments have unique requirements that go beyond just fast storage. Multi-tenancy, QoS, security and overall data protection must be considered as key building blocks of an SAP storage solution. Discover the unique and different approaches to these customer needs from innovative storage solution vendors.
Intended Audience:
Channel Marketing Managers, Distributors, VARs, System Integrators, OEMs and Solution Providers, Marketing Professionals, Sales Representatives and Managers, Business Development Executives, PR Specialists, Product and Project Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Outsourcers, Financial Analysts and Executives, Venture Capitalists, Media Representatives.

About the Organizer/Chairperson:
Jillian Coffin is VP/Group Publisher for TechTarget’s Storage, Cloud, and Data Center business units. She oversees the editorial, audience development, and sales and consulting efforts across website communities including SearchStorage.com, SearchCloudComputing.com, and SearchITchannel.com. Jillian has been a leader in the data storage community for 12+ years, sharing purchase intent data with storage vendors who want to maximize growth opportunities. She has helped establish TechTarget as the leading source of independent enterprise storage and flash technology content on the web and helped make it into a trusted resource to aid IT and business leader decision making. The Websites she manages have achieved first-page in ranking in organic search across many specific topics, and her market consulting activities are vital to a wide range of companies.

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Thursday, August 8th
9:45-10:50 AM
INVT-301B-1: Hot Topics in Academic Flash and NVM Research (New Memory Technologies Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Steve Bachmann, President, Bachmann Law Group

Paper Presenters:
Hot Topics in Academic Flash and NVM Research
Saugata Ghose, Special Faculty Systems Scientist, Carnegie-Mellon University

Session Description:
Every year, hundreds of researchers in academia push the frontier of new ideas in the field of NAND flash memory, non-volatile memories, and storage architectures. This year, we are presenting a summary of the top works and trends in academia. A committee consisting of both industrial and academic experts have selected three standout works that were published in the last year, based on a combination of the future potential of the work and its research area, the novelty of the work, and the relevance of the work to industry. This talk will briefly discuss the selected works, put them in the context of larger projects and topics that are being worked on actively at universities across the world, and provide additional resources and contacts for anyone interested in learning more about the works.
Intended Audience:
Hardware and software engineers, R&D engineers, engineering managers and CTOs, and product engineers and planners

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Steve Bachmann is the founder of Bachmann Law Group PC. He has been practicing patent and intellectual property law for 20 years, and his practice is focused on using domestic and international intellectual property acquisition, enforcement, and licensing to provide individualized intellectual property counseling and strategies that are tailored to each client’s business goals. He is a member of IEEE-CNSV which has a booth on the show floor. Steve counsels clients on prosecution of U.S. and foreign patent and trademark applications, implementing trade secret programs, licensing and technology transfer negotiation and drafting, and open source counseling. He has a broad range of experience obtaining patents in technologies including solid state storage systems, IC design, wireless networks and communications, computer architecture, AI and machine learning, and other areas of software and hardware.‎

Speaker Bio: Saugata Ghose is a Systems Scientist in the Department of Electrical and Computer Engineering at Carnegie Mellon University. His research spans a wide range of topics in the area of memory and storage systems, including data-driven architectures, NAND flash reliability, processing-in-memory, GPU memories, and emerging memory technologies. He has published several highly-cited works in top-tier conference venues and journals (including multiple works on experimentally characterizing error sources in both 2D and 3D NAND flash memories), has won a best paper award for his work on NAND flash memory forensics, and has written book chapters on NAND flash memory reliability and on processing-in-memory. He serves as Flash Memory Summit's Academic Coordinator. He earned his MS and PhD in computer engineering from Cornell University, and dual BS degrees from the State University of New York Binghamton.

Thursday, August 8th
9:45-10:50 AM
MEDE-301B-1: VR – Virtual Stories, Experiences You Control (Media & Entertainment Track)
Chairperson: Allan McLennan, Chief Executive / Analyst, PADEM Media Group

Organizer: Andy Marken, President, Marken Communications

Paper Presenters:
Immersive Media Filmmaking
Diego Prilusky, Head of Intel Studios, Intel

Practical Considerations of the Volumetric Filmmaking Pipeline
David Hoffman, Business Development Manager, Blackmagic Design

High Performance Computational Storage for Video, Volumetric and VR
John Plasterer, Chief Architect, NETINT Technologies

Session Description:
While the excitement is clear for consumers and developers, we’re also seeing increased adoption of VR for commercial and business applications. The possibilities are endless, but first, we must solve one massive challenge currently being overlooked: What to do with the endless, enormous data files being created by VR platforms. A new video capture approach – volumetric – is poised to enhance and enrich 360- (spherical video) by delivering true realism where viewers actually move around in 3-D virtual spaces, interacting with 3-D video of real people. Think of the potential applications, the experiences, the volumes of data that will be captured/stored/used to make you the director.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Allan McLennan is a Technologist/Analyst of the US based PADEM Media Group, one of the world’s recognized voices* in the advancement of IP (web/broadband/mobile) based television/OTT/VOD, video streaming and AI/ML engagement through connected devices. Allan is an established IP market technology executive in next generation digital media innovations/networks, consumer products and market capitalization deployments worldwide. His current work with global corporations and innovators addresses the deployments and acquisitions across multi-device IP networks, OTT/TV/VOD network programming and multi-platform video distribution. He actively participates in the advancement of data analytics, advanced advertising (ACR, RTB, Programmatic APIs) and the overall revision of the entertainment/media multi-platform video consumption models being explored today. He has participated in the creation/innovation, packaged and/or sold multiple new offerings throughout the world in 17 countries with close to four billion households as both a corporate executive and innovator. Allan has held five patents in targeted advertising and worked with corporations such as Ericsson, Siemens, Microsoft, TIVO, COMCAST, APPLE, Universal, Disney and more involving the advancement of IP/digital media distribution. Additionally, he was the founding AMI divisional president of the US publicly traded entertainment data analytics corporation – RENTRAK (NASDAQ: RENT), serving 100% of the studio and network marketplace.

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Thursday, August 8th
2:10-3:25 PM
COMP-302A-1: Computational Storage: Implementation Methods (Computational Storage Track)
Session Sponsor: SNIA
Organizer: Stephen Bates, CTO, Eideticom

Organizer: Scott Shadley, VP Marketing, NGD Systems

Organizer: Thad Omura, VP Marketing – Flash Business Unit, Marvell

Chairperson: George Crump, Chief Marketing Officer, StorONE

Paper Presenters:
Computational Storage: From Devices to Subsystems
Pankaj Mehra, VP of Product Planning, Samsung Electronics

Alibaba's In-Storage Computing Architecture and Ecosystem
Feng Zhu, Staff Engineer, Alibaba Group

Edge Computing with Advanced ARM based Data Center SOC and NVMe
Rick Carlson, CEO, Agylstor

Use an Intelligent SSD to Accelerate Machine Learning
HungWei Tseng, Assistant Professor, University of California, Riverside

Session Description:
Computational Storage is a paradigm shift in data center infrastructure that addresses the market demand to process huge datasets with minimal latency. Computational Storage use cases range from database, big data, AI/ML and Edge applications where there are traditionally large gaps in compute vs. the amount of data that needs to be processed. The framework for Computational Storage is driven by SNIA and the NVM Express standards groups. You will hear from vendors who will discuss their current and future offerings and end results from real usage models with real customer discussions.
Intended Audience:
Data center infrastructure and storage technologists eager to optimize performance, cost, power, and delivery of optimized application-level results that are currently bottle-necked by traditional compute, memory and storage architectures.

About the Organizer/Chairperson:
Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Scott Shadley is the VP Marketing at NGD Systems, a developer of computational storage. He focuses on brand, go-to-market, and product management and development, as well as customer adoption, acquisition, and support. He was previously Principal Technologist at Micron, where he focused on future technologies such as form factors, interfaces, and connectivity options with a particular emphasis on giving customers more freedom with their uses. He has spent over 20 years in the semiconductor and storage industries, and his efforts have been important in developing and marketing products with over $300M revenue. He has also been active as a conference presenter and organizer, particularly at Flash Memory Summit. He earned an MBA from the University of Phoenix and a BS in Semiconductor Device Physics from Boise State University (ID).

Thad Omura is an accomplished technology business executive that has been instrumental in driving startups to IPO and high-value acquisitions, while also having public company experience as a corporate executive. Since April 2015, Thad has served as EVP of Marketing and Operations for ScaleFlux responsible for all business, marketing, and expanding the growth opportunities for Computational Storage. Prior to ScaleFlux, Thad was VP of Product & Customer Management for Seagate Technology’s Flash and SSD business. He stepped into that role through Seagate’s acquisition of the LSI Flash products in 2014, including SandForce Flash Processors, and PCIe SSDs. Thad was an early executive at SandForce in 2008 as VP of Marketing, and remained with the organization through the LSI and Seagate acquisitions. Prior to SandForce, Thad was with Mellanox Technologies as VP of Product Marketing, and helped drive the company to an IPO in 2007 based on success of its industry-leading networking solutions. Prior to Mellanox, Thad served in various marketing and sales roles at Motorola SPS, Marvell, Galileo Technology, and Quality Semiconductor. Thad holds a BS degree in EECS from UC Berkeley.

George Crump is a leading storage analyst focused on the emerging subjects of big data, solid state storage, virtualization, and cloud computing. He is widely recognized for his blogs, whitepapers, and videos on such current issues as all-flash arrays, deduplication, SSDs, software-defined storage, backup appliances, and storage networking. His popular whiteboard sessions, in which he leads key vendors through their solutions to data center problems, have also gotten tremendous attention. As President and Founder of Storage Switzerland, an analyst firm focused on the storage, virtualization, and cloud markets, he provides marketing, product definition, technical writing, presentation training, and product planning services to storage vendors, integrators, and end users. He has spoken or moderated at many conferences including Flash Memory Summit, StorageVisions, Pure Evolve, and Storage Networking World. He has 25 years of experience designing storage solutions for data centers across the US. Before founding Storage Switzerland, he was CTO at SANZ, a large storage integrator where he led technology testing, integration, and product selection. The “Switzerland” in his firm’s name indicates his pledge to provide neutral analysis of the storage marketplace, rather than focusing on a single vendor or approach.

Thursday, August 8th
2:10-3:25 PM
ENST-302A-1: Designing Storage Systems for the Exabyte Era (Enterprise Storage Track)
Chairperson: Jeff Safire, President, Shadow Cliffs Engineering

Organizer: Rob Peglar, President, Advanced Computing and Storage

Paper Presenters:
Designing Storage Systems for the Exabyte Era
Rob Peglar, President, Advanced Computing and Storage

Session Description:
Storage has moved to center stage in the era of petabytes and exabytes. This little-studied area (who ever heard of a required course on it?) is now the center of attention as processors and networks have moved into a period of tremendous complexity and slow progress. To manage the huge rapid data flows required by key applications such as real-time analytics, AI/ML, virtual and augmented reality, exascale HPC, and IoT, significant system-level design breakthroughs are essential. Storage systems must take full advantage of all the latest technological advances such as persistent memory, high-density NAND (QLC), NVMe, and fabric-based networking. Scalability is obviously essential as datasets continue to grow at breathtaking rates, local stores and processing are necessary to avoid long data transfers, and flexibility is paramount as systems must take full control of both metadata and policies. System complexity must be reduced, particularly to keep the mega clouds manageable. International organizations at all levels must bring together researchers, designers, and users to create the standards, certifications, open-source software, and training required to make the new era of storage successful.
Intended Audience:
Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Hardware Architects and Managers, Software Design Architects, Software Engineers and Managers, Product Managers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, and Data Center Architects.

About the Organizer/Chairperson:
Jeff Safire has 39 years of industry experience, including 20 years as an independent software and firmware consultant. He works primarily in the computer data storage and medical device industries. Jeff also has 19 years experience as an expert witness and forensic expert consultant, and he has developed websites and applications for a variety of business disciplines. Jeff is an IEEE-CNSV At-Large Director. He was a CNSV Director in 2013, an At-Large Director in 2009-2012, and CNSV Treasurer in 2007-2008. Jeff also ran CNSV’s CPP Seminar program in 2009 through 2012.

Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Speaker Bio: Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Thursday, August 8th
2:10-3:25 PM
FSOL-302A-1: Flash Solutions for Analytics (Flash Solutions Track)
Organizer: Jay Kramer, President, Network Storage Advisors

Chairperson: Mike Matchett, TechTarget Research Advisor, Small World Big Data

Panel Members:
Panelist: Denise Shiffman, Chief Product Officer, DriveScale

Panelist: Anu Murthy, VP Marketing, FADU

Panelist: Jeff Sosa, Head of Products, Pavilion Data

Panelist: Matt Miller, Director of Product Marketing,, WekaIO

Session Description:
Data is the most valuable asset in modern enterprises, and data analytics is the key to unlocking critical insights to better service customer needs and to competitively differentiate products and services in the marketplace. Uncover the key selection criteria and storage solution considerations when evaluating all flash storage arrays.
Intended Audience:
Channel Marketing Managers, Distributors, VARs, System Integrators, OEMs and Solution Providers, Marketing Professionals, Sales Representatives and Managers, Business Development Executives, PR Specialists, Product and Project Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Outsourcers, Financial Analysts and Executives, Venture Capitalists, Media Representatives.

About the Organizer/Chairperson:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Mike Matchett is Principal IT industry analyst at Small World Big Data, focusing on technology trends and the intersection where IT enterprise meets emerging markets. He is also a lead consultant and advisor to TechTarget’s Market Research and Development Group. With more than 25 years of high-tech marketing and product management experience, Mike writes across data center, cloud and big data segments predicting that all data will become big, all clouds hybrid, and the converged data center re-imagined from center to edge. Prior to TechTarget, Mike spent 5 years in a Sr. Analyst role w/ the Taneja Group where he provided services for existing and emerging IT enterprise infrastructure markets. Mike has a B.S in electrical engineering from the Massachusetts Institute of Technology.

Thursday, August 8th
2:10-3:25 PM
FTEC-302A-1: The Next Great Breakthrough in Non-Volatile Memory (Flash Technology Track)
Organizer + Chairperson: Leah Schoeb, Sr. Developer Relations Manager, AMD

Panel Members:
Panelist: Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Panelist: Daniel Worledge, MRAM Manager, IBM

Panelist: Rory Bolt, Principal Architect, Sr. Fellow Memory and Storage Strategy, KIOXIA America

Panelist: Jim Handy, Director/Chief Analyst, Objective Analysis

Panelist: Bill Gervasi, Principal Systems Architect, Nantero

Session Description:
Advances in nonvolatile memory keep coming despite warnings about a slowdown or stoppage in technological innovation. Flash remains the dominant technology, and its run is likely to continue. Breakthroughs keep occurring, and advances raise density and speed and decrease costs. What will be next? Will it be multiple levels beyond QLC, a fourth dimension, smaller process dimensions, or something else? Of course, flash technology has been around for a while, and the next great breakthrough could be the long-awaited emergence of a major contender such as MRAM, RRAM, memristors, or carbon nanotubes.
Intended Audience:
Hardware and software design engineers, storage managers and engineers, product planners and designers, enterprise storage system designers and engineers, enterprise flash and SSD product managers and marketing engineers, large-scale systems designers, engineering managers, storage consultants.

About the Organizer/Chairperson:
Leah Schoeb is a Sr. Developer Relations Manager in the platform architecture team at AMD, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, with the last decade in solid state technology. She is also the Founding Data Architect at Data Glass, where she assists systems companies with performance engineering and optimization, market positioning, and benchmarking. She was previously Acting Director Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as the Industry Trends Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC), and Storage Networking Industry Association (SNIA). She is a member of the SNIA Technical Council and a co-founder of their Solid State Storage System Technical Work Group. She earned an MBA at the University of Phoenix and a BSEE at the University of Maryland, College Park.

Thursday, August 8th
2:10-3:25 PM
INDT-302A-1: Zettabyte Alert - Designing Storage for the Big Bang in Data (Industry Trends Track)
Chairperson: Ben Woo, Director Product Marketing, Amazon

Organizer: Marc Staimer, President, Dragon Slayer Consulting

Paper Presenters:
Session Description:
IDC’s Digital Universe Study predicts that the amount of data generated will increase from 0.1 ZB in 2005 to 44 ZB in 2020 – and will grow further to 163 ZB by 2025. How will storage systems handle all that data while maintaining performance and keeping costs under control? What are the best ways for data centers to develop systems that are scalable yet feasible in an era of static budgets and headcount? What general guidelines must the storage designer consider? What are the key hints, warnings, tips, and tricks that will help product designers and data center managers alike prepare for the data onslaught?
Intended Audience:
General

About the Organizer/Chairperson:
Coming soon..

Marc Staimer is the founder, senior analyst and CDS at Dragon Slayer Consulting in Beaverton, Oregon. The consulting practice has focused on the areas of strategic planning, product development and market development. With more than 30 years of marketing, sales and business experience in infrastructure, storage, server, software and virtualization, Marc is considered one of the industry's leading experts.

Thursday, August 8th
2:10-3:25 PM
INVT-302A-1: Life After RAID: Big Data Requires a Better Approach (Enterprise Storage Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Steve Bachmann, President, Bachmann Law Group

Paper Presenters:
Life After RAID: Big Data Requires a Better Approach
Mike McWhorter, Senior Technologist, Western Digital

Session Description:
RAID has become a standard way of protecting data integrity. The various RAID levels provide many options for data centers to use with a wide range of cost/performance tradeoffs. However, traditional RAID is no longer capable of handling centers' needs now that data stores in the petabyte range are commonplace. Rebuild times have become way too long, and capacity requirements have become far too large. Furthermore, triple replication simply takes too much space to be economically feasible. The solution is erasure coding, which can survive more disk failures than RAID while using only a fraction of the space of triple replication. It allows users to keep rebuild times and storage costs under control for today's big data applications and for the zettabyte future.
Intended Audience:
Data center managers and engineers, product planners, storage managers and engineers, product marketing engineers, system managers and engineers; CIOs and CTOs

About the Organizer/Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Steve Bachmann is the founder of Bachmann Law Group PC. He has been practicing patent and intellectual property law for 20 years, and his practice is focused on using domestic and international intellectual property acquisition, enforcement, and licensing to provide individualized intellectual property counseling and strategies that are tailored to each client’s business goals. He is a member of IEEE-CNSV which has a booth on the show floor. Steve counsels clients on prosecution of U.S. and foreign patent and trademark applications, implementing trade secret programs, licensing and technology transfer negotiation and drafting, and open source counseling. He has a broad range of experience obtaining patents in technologies including solid state storage systems, IC design, wireless networks and communications, computer architecture, AI and machine learning, and other areas of software and hardware.‎

Speaker Bio: Mike McWhorter is a senior technologist at Western Digital. He specializes in performance tuning and storage optimization for big data customers with a focus on testing and benchmarking applications, and optimizing them for a variety of storage technologies. He has almost 20 years of experience in the technology industry and has emphasized the deployment of flash memory arrays in enterprise applications. He has published many technical articles and holds a patent for a forensic data transfer algorithm. McWhorter received a Bachelor’s degree in Computer Science from Longwood University in Virginia. He is a frequent blogger on big data issues.

Thursday, August 8th
2:10-3:25 PM
MEDE-302A-1: Living the Ready Player One Virtual Experience (Media & Entertainment Track)
Organizer: Andy Marken, President, Marken Communications

Chairperson: Allan McLennan, Chief Executive / Analyst, PADEM Media Group

Panel Members:
Panelist: David Hoffman, Business Development Manager, Blackmagic Design

Panelist: Nigel Tierney, Head of Content, RYOT

Panelist: John Plasterer, Chief Architect, NETINT Technologies

Panelist: Diego Prilusky, Head of Intel Studios, Intel

Panelist: Andrew Shulkind, , Cinematographer

Panelist: Andrew Cochrane, , Filmmaker

Panelist: Richard Kerris, Senior Director - Worldwide Developer Relations, NVIDIA

Session Description:
Find out what the entertainment and general business have in store for VR. Learn how the technology will prove to be a major asset in real estate, defense, healthcare, education and technology development. Architects, builders can enable clients to walk around and through projects even before ground has been broken. Military and aerospace organizations enable personnel to experience combat, equipment/systems and even venture through the space activities and worst-case scenarios safely. The enriched technology will help engineers to develop, test, work with, refine minute chips or entire systems in a virtual world they produce, refine without building/destroying a single solution. The technology will enable sporting enthusiast to be involved in all of the football, basketball, soccer action. Find out how our experts envision VR being used and explore how soon it can be part of your professional/personal life.
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Allan McLennan is a Technologist/Analyst of the US based PADEM Media Group, one of the world’s recognized voices* in the advancement of IP (web/broadband/mobile) based television/OTT/VOD, video streaming and AI/ML engagement through connected devices. Allan is an established IP market technology executive in next generation digital media innovations/networks, consumer products and market capitalization deployments worldwide. His current work with global corporations and innovators addresses the deployments and acquisitions across multi-device IP networks, OTT/TV/VOD network programming and multi-platform video distribution. He actively participates in the advancement of data analytics, advanced advertising (ACR, RTB, Programmatic APIs) and the overall revision of the entertainment/media multi-platform video consumption models being explored today. He has participated in the creation/innovation, packaged and/or sold multiple new offerings throughout the world in 17 countries with close to four billion households as both a corporate executive and innovator. Allan has held five patents in targeted advertising and worked with corporations such as Ericsson, Siemens, Microsoft, TIVO, COMCAST, APPLE, Universal, Disney and more involving the advancement of IP/digital media distribution. Additionally, he was the founding AMI divisional president of the US publicly traded entertainment data analytics corporation – RENTRAK (NASDAQ: RENT), serving 100% of the studio and network marketplace.

Thursday, August 8th
2:10-3:25 PM
NVMF-302A-1: Understanding NVMe over Fabrics on TCP (NVMe-oF Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology, Mellanox

Paper Presenters:
NVMe/TCP Interop
David Woolf, Sr Engineer Datacenter Technology, UNH-IOL

An NVMe/TCP Software-Defined Platform for Guaranteed QoS
Alex Shpiner, System Architect, Lightbits Labs

Accelerating NVMe over TCP for Disaggregated Storage Applications
Tom Spencer, Senior Director Product Marketing, Solarflare

Using SmartNICs and Buffer Management to Improve NVMe over TCP Performance
Ron Renwick, VP of Products, Netronome

Comparing NVMe-oF on RoCE vs. TCP
John Kim, Director Storage Marketing, NVIDIA

Session Description:
NVMe over Fabrics has been in the market over RDMA with Ethernet RoCE and InfiniBand since 2016 and Fibre Channel since last year. New to the market this year is NVMe over Fabrics on Ethernet TCP. This talk will describe the technology in its many forms. Describe use cases, for both Enterprise and cloud, where it is being applied. Then finish with Q/A to the four presenters.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 8th
2:10-3:25 PM
PMEM-302A-1: What’s the Best Approach to Persistent Memory Today…and Tomorrow? (Persistent Memory Track)
Organizer + Chairperson: Mark Webb, President, MKW Ventures

Organizer: Rahul Advani, Director Global Procurement, NetApp

Panel Members:
Panelist: Shai Fultheim, Founder, President and CEO, ScaleMP

Panelist: Arthur Sainio, Director Product Marketing, SMART Modular Technologies

Panelist: Pankaj Bishnoi, Director of Applications, Everspin

Panelist: Rahul Advani, Director Global Procurement, NetApp

Panelist: Bill Leszinske, VP Non-Volatile Memory Solutions Group, Intel

Session Description:
Coming soon..
Intended Audience:
Coming soon..

About the Organizer/Chairperson:
Mark Webb is Principal/Consultant at MKW Ventures Consulting where he provides consulting services in SSDs, NAND, NVM, and semiconductor technology and competitive analysis. With over 25 years experience in semiconductor and system engineering and manufacturing, Mark consults with SSD OEM and ODM companies, memory manufacturers, and investment firms. Before founding MKW Ventures, Mark was Director of Manufacturing for the NVM Solutions Group at Intel, where he was responsible for SSD system and NAND component manufacturing. He also has been Corporate Product Quality and Reliability Manager for IM Flash Technologies, the widely publicized joint venture between Intel and Micron that became an industry leader in NAND technology. Mark is a frequent presenter at Flash Memory Summit and other key venues, and his analysis of technology adoption and product costs are often referenced by investment firms, analysts, technology training firms and major OEMs. He earned a BSEE at California State University, Chico.

Rahul Advani is VP Marketing at Netlist, a maker of non-volatile memory DIMMs. He manages all marketing activities for the company, as well as product management and business development. He was previously Director of Flash Product Marketing at Microsemi, where he was responsible for PCIe controller product marketing as well as the Memory Program Office that handled a wide range of enterprise storage products. He also worked at Micron, where he was directly responsible for over $1B in annual revenue as well as the definition, introduction, and volume ramp of RLDRAM3 and server DDR3 modules. His more than 15 years of experience in the semiconductor industry has thus spanned product marketing, product definition, and ecosystem development. Rahul earned a PhD in Engineering from MIT and a BSEE from Cornell.

Thursday, August 8th
2:10-5:00 PM
AIML-302-1: Using AI/ML for Flash Performance Scaling, Part 2 (AI/Machine Learning Track)
Chairperson: Ali Keshavarzi, Adjunct Professor, Stanford University

Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
NVM Usage in the AI Era
Dave Eggleston, Principal, Intuitive Cognition Consulting

Flash Memory, Storage and Data Challenges for Production Machine Learning
Nisha Talagala, CEO, Pyxeda AI

An Analog Neuromorphic Compute System Based on SuperFlash
Mark Reiten, Vice President Licensing Division, Microchip

Non-Volatile Neural Network Accelerator in Your SoC
Sangsoo Lee, CEO, ANAFLASH

Computation and Machine Learning in Flash Memory: Opportunities and Challenges
Jeremy Holleman, CTO, Syntiant

Predicting I/O Patterns Using LSTM Neural Networks in Storage Systems
Ken Qing Yang, Chief Scientist, Dapu Microelectronics

Session Description:
AI and machine learning (ML) are being used in many areas of the NVM industry. For example, various storage device health indicators can be monitored, and an ML model can be used to identify the drive's health by utilizing a deep neural network. However, such techniques require processing power and adequate storage apart from the storage that they are monitoring, and a Deep Learning (DL) approach requires the subsystem to learn by itself. This is just a sampling of the kind of issues addressed by the talks in this track.
Intended Audience:
Data center engineers/managers; storage architects/managers; hardware and software infrastructure designers; systems engineers/analysts; engineering managers; marketing and product managers; solution providers and consultants; VARs, OEMs and system integrators.

About the Organizer/Chairperson:
Ali Keshavarzi, Ph.D. is an Adjunct Professor in Electrical Engineering at Stanford Univ., is involved in scholarly research, and is an advisor to Stanford SystemX IoE Research. He works with DARPA as an advisor and subject matter expert on the Electronic Resurgence Initiative (ERI) and is a member of DARPA MTO Investor Working Board (IWB). Ali is a principal and the founder of Leading Edge Research LLC, Los Altos, CA. Dr. Keshavarzi is a technology visionary and a leader who has been at the forefront of technology innovation with a track record of delivering critical process technologies, devices, circuits, SoCs, and modules to the semiconductor industry. He was the VP of R&D and a Fellow at Cypress Semiconductor, and he held various positions at Intel, TSMC, and GLOBALFOUNDRIES in a variety of technical and leadership roles over 25 years. Ali was a visiting research professor at UC Berkeley from 2017 to 2018.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Thursday, August 8th
2:10-5:00 PM
NVMF-302-1: Benefits and Use Cases for NVMe-oF (NVMe-oF Track)
Organizer + Chairperson: Vishal Shukla, Senior Director, Mobileiron

Organizer: Muli Ben-Yehuda, CTO and Co-Founder, Lightbits Labs

Paper Presenters:
NVMe-oF: Benefits and Use Cases for Production Applications
Steve McQuerry, Sr. Technical Marketing Engineer, Pure Storage

Deep Dive on Disaggregated Storage Architectures: Challenges and Solutions
Vaidyanathan Krishnamoorthy, Cloud Solutions Architect, Intel

Mrittika Ganguli, Network Architect, Intel
SmartNICs for E2E NVMe Disaggregation in a Software Defined Datacenter
Fazil Osman, Distinguished Engineer, Broadcom

Developing NVMe-oF Composable Infrastructure with Virtual All-Flash Appliances
Alan Lin, Chief Solution Architect, AccelStor

Implementing Computational Storage in an NVMe-oF-Based System
Patrice Couvert, Technical Product Manger, Kalray

Using SmartNICs to build an NVMeoF Target Systrem
Ziv Serlin, VP System Architecture, E8 Storage

What NVMe-Over-Fabrics Means to Software Defined Storage
Tom Lyon, Chief Scientist, DriveScale

Bringing NVMe-oF to Hyperscalers with SmartNICs
Idan Burstein, Staff Silicon Architect, Mellanox

Session Description:
NVM Express over Fabrics (NVMe-oF) enables users to connect remote subsystems with a flash appliance to achieve faster application response times and better scalability across virtual data centers. NVMe over fabrics offers high transfer speeds, low latency, full standardization, and access to a large ecosystem. Data centers can employ it to get higher utilization, huge performance benefits, and high levels of scalability over hundreds or thousands or local and remote SSDs. It is thus well-suited to large sites such as clouds, megawebsites, and hyperconverged data centers.
Intended Audience:
Design engineers, hardware engineers, engineering managers, product and product marketing engineers, applications engineers, storage specialists and managers, storage technologists, systems engineers and analysts

About the Organizer/Chairperson:
Vishal Shukla is Director Ethernet Switch Business at Mellanox Technologies. A thought leader in networking, cloud, and deep learning solutions, he has written multiple papers, authored books, and obtained over 15 patents. He has over 10 years proven experience in developing and leading global teams in functions such as technical sales, solutions architecture, technical alliances, and customer support. He has worked for Mellanox, NVXL Technologies, IBM Cloud, Blade Network Technologies, Cisco, and Nortel. He earned an MBA from Duke University and a BS in Information Technology from Uttar Pradesh Technical University (India).

Vishal Shukla is Director Ethernet Switch Business at Mellanox Technologies. A thought leader in networking, cloud, and deep learning solutions, he has written multiple papers, authored books, and obtained over 15 patents. He has over 10 years proven experience in developing and leading global teams in functions such as technical sales, solutions architecture, technical alliances, and customer support. He has worked for Mellanox, NVXL Technologies, IBM Cloud, Blade Network Technologies, Cisco, and Nortel. He earned an MBA from Duke University and a BS in Information Technology from Uttar Pradesh Technical University (India).

Thursday, August 8th
3:40-5:00 PM
COMP-302B-1: Computational Storage: Applications (Computational Storage Track)
Session Sponsor: SNIA
Organizer: Scott Shadley, VP Marketing, NGD Systems

Organizer: Thad Omura, VP Marketing – Flash Business Unit, Marvell

Chairperson: George Crump, Chief Marketing Officer, StorONE

Organizer: Stephen Bates, CTO, Eideticom

Paper Presenters:
Creating a Framework for Computational Storage Applications
Nick Adams, Platform Storage Architect, Intel

Design the Right Storage Systems to Accelerate Deep Learning
Jerome Gaysse, Managing Director, Silinnov Consulting

Application System Design From Edge to Data Centers
Rohit Gupta, Segment Manager Devices GTM, Western Digital

Computational Storage Workloads - Implications for Datacenter Architectures
Jamon Bowen, Planning and Segement Marketing Director, Xilinx

Session Description:
Computational Storage is a paradigm shift in data center infrastructure that addresses the market demand to process huge datasets with minimal latency. Computational Storage use cases range from database, big data, AI/ML and Edge applications where there are traditionally large gaps in compute vs. the amount of data that needs to be processed. The framework for Computational Storage is driven by SNIA and the NVM Express standards groups. You will hear from vendors who will discuss their current and future offerings and end results from real usage models with real customer discussions.
Intended Audience:
Data center infrastructure and storage technologists eager to optimize performance, cost, power, and delivery of optimized application-level results that are currently bottle-necked by traditional compute, memory and storage architectures.

About the Organizer/Chairperson:
Scott Shadley is the VP Marketing at NGD Systems, a developer of computational storage. He focuses on brand, go-to-market, and product management and development, as well as customer adoption, acquisition, and support. He was previously Principal Technologist at Micron, where he focused on future technologies such as form factors, interfaces, and connectivity options with a particular emphasis on giving customers more freedom with their uses. He has spent over 20 years in the semiconductor and storage industries, and his efforts have been important in developing and marketing products with over $300M revenue. He has also been active as a conference presenter and organizer, particularly at Flash Memory Summit. He earned an MBA from the University of Phoenix and a BS in Semiconductor Device Physics from Boise State University (ID).

Thad Omura is an accomplished technology business executive that has been instrumental in driving startups to IPO and high-value acquisitions, while also having public company experience as a corporate executive. Since April 2015, Thad has served as EVP of Marketing and Operations for ScaleFlux responsible for all business, marketing, and expanding the growth opportunities for Computational Storage. Prior to ScaleFlux, Thad was VP of Product & Customer Management for Seagate Technology’s Flash and SSD business. He stepped into that role through Seagate’s acquisition of the LSI Flash products in 2014, including SandForce Flash Processors, and PCIe SSDs. Thad was an early executive at SandForce in 2008 as VP of Marketing, and remained with the organization through the LSI and Seagate acquisitions. Prior to SandForce, Thad was with Mellanox Technologies as VP of Product Marketing, and helped drive the company to an IPO in 2007 based on success of its industry-leading networking solutions. Prior to Mellanox, Thad served in various marketing and sales roles at Motorola SPS, Marvell, Galileo Technology, and Quality Semiconductor. Thad holds a BS degree in EECS from UC Berkeley.

George Crump is a leading storage analyst focused on the emerging subjects of big data, solid state storage, virtualization, and cloud computing. He is widely recognized for his blogs, whitepapers, and videos on such current issues as all-flash arrays, deduplication, SSDs, software-defined storage, backup appliances, and storage networking. His popular whiteboard sessions, in which he leads key vendors through their solutions to data center problems, have also gotten tremendous attention. As President and Founder of Storage Switzerland, an analyst firm focused on the storage, virtualization, and cloud markets, he provides marketing, product definition, technical writing, presentation training, and product planning services to storage vendors, integrators, and end users. He has spoken or moderated at many conferences including Flash Memory Summit, StorageVisions, Pure Evolve, and Storage Networking World. He has 25 years of experience designing storage solutions for data centers across the US. Before founding Storage Switzerland, he was CTO at SANZ, a large storage integrator where he led technology testing, integration, and product selection. The “Switzerland” in his firm’s name indicates his pledge to provide neutral analysis of the storage marketplace, rather than focusing on a single vendor or approach.

Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Thursday, August 8th
3:40-5:00 PM
EMBD-302B-1: Flash Memory, IoT, and AI – Bringing It All Together (Embedded Applications Track)
Organizer + Chairperson: Sanhita Sarkar, Global Director, Analytics Software Development, Western Digital

Panel Members:
Panelist: Chanson Lin, Founder/CEO, EmBestor Technology

Panelist: Kiran Gunnam, Distinguished Engineer - Machine Learning & Computer Vision, Western Digital

Panelist: Andy Watson, Cloud Strategies for Startups, Amazon

Panelist: Scott Lawrence, Director Business Development, Virtium Solid State Storage and Memory

Session Description:
The Internet of Things (IoT) will generate far more data than people or even supercomputers can handle effectively with today’s methods. AI systems will make useful information out of continuous streams of IoT data. This capability comes with a significant increase in computational complexity and an increased demand on high-performance storage and processing power. The combination of flash memory, IoT, and AI is the way to produce business value out of this incredible new technology. And, of course, all this has to be done at reasonable cost and with reasonable power consumption. Case studies show the IoT strategy combining AI technologies that companies have developed to meet their business goals.
Intended Audience:
Hardware and Software design architects, Storage Architects, Infrastructure Architects, System Architects, Storage Engineers, Storage Specialists, Software Engineers, Product Managers, Marketing Engineers, Consultants, Analysts, IT Professionals and Managers, and Data Center Architects.

About the Organizer/Chairperson:
Sanhita Sarkar is a Global Director Analytics at Western Digital, where she focuses on software design and development of analytical features and solutions spanning edge, data center, data lake, and cloud. She has expertise in key vertical markets such as the Industrial Internet of Things (IIoT), Defense and intelligence, Financial Services, Genomics, and Healthcare. Sanhita previously worked at Teradata, SGI, Oracle, and several startups. She was responsible for overseeing design, development, and delivery of optimized software and solutions involving large memory, scale-up, and scale-out systems. Sanhita has authored four patents, published several papers, and spoken at several conferences. She received her Ph.D in Electrical Engineering and Computer Science from the University of Minnesota, Minneapolis.

Thursday, August 8th
3:40-5:00 PM
FSOL-302B-1: Flash Solutions for AI/ML (Flash Solutions Track)
Chairperson: Jillian Coffin, VP/Publisher Storage Virtualization and Cloud, TechTarget

Organizer: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Ramnath Sai Sagar, Senior Product Marketing Manager, AI and Deep Learning, Pure Storage

Panelist: VR Satish, CTO, Pavilion Data Systems

Panelist: Mat Gruen, Senior Director Channels, WekaIO

Panelist: Tom Lyon, Chief Scientist, DriveScale

Session Description:
Artificial Intelligence (AI) and Machine Learning (ML) are without a doubt the hottest things happening out there in the technology world. They are changing the way every industry is solving its biggest problems. Implementations stretch from mobile devices all the way to the data center with compute, memory, and storage needing to be balanced to achieve optimal performance. Uncover the key considerations when evaluating flash arrays to address these rapidly emerging applications.
Intended Audience:
Channel Marketing Managers, Distributors, VARs, System Integrators, OEMs and Solution Providers, Marketing Professionals, Sales Representatives and Managers, Business Development Executives, PR Specialists, Product and Project Management, Product Planners, Application and Solutions Engineers, Sales and System Engineers, CIOs and IT Management, Data Center Planners, Consultants, Outsourcers, Financial Analysts and Executives, Venture Capitalists, Media Representatives.

About the Organizer/Chairperson:
Jillian Coffin is VP/Group Publisher for TechTarget’s Storage, Cloud, and Data Center business units. She oversees the editorial, audience development, and sales and consulting efforts across website communities including SearchStorage.com, SearchCloudComputing.com, and SearchITchannel.com. Jillian has been a leader in the data storage community for 12+ years, sharing purchase intent data with storage vendors who want to maximize growth opportunities. She has helped establish TechTarget as the leading source of independent enterprise storage and flash technology content on the web and helped make it into a trusted resource to aid IT and business leader decision making. The Websites she manages have achieved first-page in ranking in organic search across many specific topics, and her market consulting activities are vital to a wide range of companies.

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Thursday, August 8th
3:40-5:00 PM
MRES-302B-1: Top 10 Things You Need to Know about Flash Memory Today (Market Research Track)
Organizer + Chairperson: Jean Bozman, President, Cloud Architects

Panel Members:
Panelist: Tom Coughlin, President, Coughlin Associates

Panelist: Rakesh Radhakrishnan, Director, Product Management, VMware

Panelist: Rob Peglar, President, Advanced Computing and Storage

Panelist: Marc Staimer, President, Dragon Slayer Consulting

Panelist: Adam Roberts, Independent Consultant, Consultant

Session Description:
Flash memory has morphed rapidly from an exciting new technology that had to be justified for specific use cases to a standard part of every data center. What other kind of storage would you be buying today? So what do vendors and users alike need to know about flash? Is it the emergence of 3D technology, the rapid rise of the high-speed NVMe standard, the promise of persistent memory (storage at memory speeds), the role of flash in scalable systems such as clouds and megawebsites, new methods for flash storage networking (such as NVMe-oF), ways to make software take advantage of flash memory, or large, hierarchical storage systems that cover everything from high-speed cache to long-term archiving? Our top industry experts will present a few of their own candidates for the Top Ten list. We will then open nominations to the audience and finish with our vote for the Top Ten for 2019.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Jean S. Bozman is currently Vice-President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, server and storage technology, software-defined storage, and software-defined infrastructure (SDI). She also serves as Program Chairperson for the Software-Defined Infrastructure Summit. Before joining Hurwitz and Associates, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads that leverage SSDs. A well-respected IT professional with over 20 years experience covering the worldwide markets for operating environments, servers and the workloads that run on servers, she was previously a Research VP at IDC. While at IDC, she focused on the worldwide market for server operating systems. She analyzed the worldwide server market and managed the Clustering and Availability Software (CLAS) market research. Ms. Bozman has been widely quoted in business publications, including BusinessWeek and Investor’s Business Daily; in daily newspapers, including the San Jose Mercury News and Los Angeles Times; and in online publications, such as CNET (news.com), Bloomberg, and Reuters. Ms. Bozman holds a B.S. from the State University of New York (SUNY) at Stony Brook and a master's degree from Stanford University.

Thursday, August 8th
3:40-5:00 PM
NVMF-302B-1: Are Ethernet Attached SSDs Happening? (NVMe-oF Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology, Mellanox

Paper Presenters:
NVMe-oF Ethernet SSDs Optimizing eBOF Solutions for Efficient Data Center
Ilker Cebeli, Sr Director Product Planning, Samsung Semiconductor

Building a Better Solution with Native NVMe-oF SSDs
John Kloeppner, Principal Engineer / HW Architect, NetApp

Benefits of Native NVMe-oF SSD
Balaji Venkateshwaran, Sr. Director of Strategy and Product Marketing, Toshiba Memory

Native NVMe-oF SSD
Khurram Malik, Senior Technical Product Marketing Manager, Marvell Semiconductor

Storage System Using NVMe over Fabric SSD-Based Ethernet JBOF
Woo Suk Chung, Storage Software Team Lead, SK hynix

Session Description:
Ethernet-attached SSDs are one of the most interesting new developments in networked storage. Enabled by NVMe-oF, this new architecture removes the bandwidth limitation and lowers the cost of current JBOF designs. Today’s NVMe-oF Ethernet JBOF designs are typically architected with PCIe switches, Ethernet NICs and CPU complexes all there to convert NVMe-oF on Ethernet to NVMe on PCIe and back. Although widely successful to date this approach limits the NVMe SSD performance to the data rate capability of the CPU and NICs on its PCIe bus. It is also not cheap. This session will show how NVMe-oF Ethernet attached SSDs (eSSD) and Ethernet storage enclosures (eBOF) could address both these JBOF limitations.
Intended Audience:
Enterprise Application Designers and Engineers; Data Scientists; Network and Data Center Directors, Managers and Engineers; Enterprise Storage System Designers; Software Designers, Enterprise Flash and SSD Product Managers & Marketing Engineers; Large-Scale Systems Designers; Investors & Analysts

About the Organizer/Chairperson:
Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.