Monday, August 6th
Monday, August 6th
8:30-Noon
Pre-Conference Seminar A: Introduction to 3D NAND (Pre-Conference Seminars Track)
Organizer + Chairperson + Instructor: Chuck Sobey, Chief Scientist, ChannelScience

Speaker(s):
Session Description:
Decades of progress in traditional planar (2D) semiconductor manufacturing enabled the flash industry to replace many established storage technologies. Now 3D semiconductor manufacturing has set the stage for the next wave of data storage disruption. Over half of the NAND flash bits being shipped are now 3D. As NAND manufacturers move beyond their 3rd and 4th generations of 3D NAND, this percentage will continue to grow. What do you need to know about 3D NAND to use it to full advantage in your next design? How is the changing role of the flash translation layer (FTL) in data center appliances changing how 3D NAND is being used, tested, and optimized? If more of the native NAND performance is exposed, what do you do with it? What can you expect to encounter when using 3D NAND in extreme environments like automotive, industrial, and IoT? How should your company position itself for the opportunities and challenges this new technology brings? How does 3D XPoint from Intel or QuantX from Micron (unveiled at Flash Memory Summit 2016) differ from 3D NAND and how might they be used together? Now is the time to prepare yourself, your key staff, and your company. Reliable, unbiased information is critical for making the right decisions! So don't proceed (and spend a lot of development money) without a clear understanding of the fundamentals, opportunities, and challenges of this breakthrough technology! Learn from internationally-respected storage industry consultant and expert instructor, Chuck Sobey, about the benefits and challenges of 3D flash device technologies, alternative array architectures, controller partitioning, algorithm developments, and the problems posed by the technology. This tutorial is a great way to get up-to-speed quickly on this major technology shift. Cut through the hype and confusion surrounding 3D! Conquer the fear and apprehension regarding how 3D NAND might affect you! Build a firm foundation for yourself and your team. Learn how to ask the tough questions and know when you get the right answers! This tutorial is designed for engineers, managers, and executives who must make immediate decisions implementing or optimizing 3D flash technology. It is presented by KnowledgeTek, the world's leading data storage technology training company. Suggested prerequisites include a technical background and an interest in 3D technology; the class does not assume detailed engineering knowledge of flash memory or semiconductor processing. Course Outline 1. The Path from 2D to 3D NAND? 3D: What it is and what it isn't? 2D wraparound and planar floating-gate flash cells? The 2D NAND flash array? Problems and challenges with 2D flash? Charge trapping NAND flash ? Roadmaps for 3D NAND? The device determines the system 2. Competing Technologies and Architectures for 3D Flash? Vertical transistor designs? 3D array architectures ? Accessing data? SLC to TLC and QLC in 3D? Resistive storage technologies (ReRAM) 3. Process, Design, and Test Challenges? Etch and deposition vs. lithography? Logical-to-physical translation in 3D? Testing, characterization, and defects? Controller partitioning 4. Next Steps in 3D? Accessing raw NAND? Parameter setting with machine learning? Opportunities with 3D XPoint? QuantX? A lesson from The Wrath of Khan? What to watch for at the Summit!
About the Organizer/Moderator:
Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer; as well as the Conference Chairperson of the 2018 Flash Memory Summit. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque). As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there. Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara

Monday, August 6th
8:30-Noon
Pre-Conference Seminar B: Introduction to NVM Express (NVMe) (Pre-Conference Seminars Track)
Organizer + Chairperson + Instructor: Hugh Curley, Consultant, HughCurley.com

Speaker(s):
Session Description:
NVM Express (NVMe) is a specification for connecting non-volatile memory devices such as SSDs to computers via the PCIe bus. The idea is to take advantage of the high speed of PCIe (as compared to disk interfaces such as SAS or SATA), while maintaining full standardization and access to a large ecosystem. It has rapidly become a popular interface supported by almost all major SSD makers. Storage designers and end users alike appreciate its combination of low cost, high speed, widespread support, and standardized approach. NVMe started with a clean slate to build a command set and supporting mechanism that would take advantage of the PCIe transport and SSD storage devices. It is scalable from iPads to enterprise and high performance computing. At the Flash Memory Summit, many keynote presentations and breakout sessions assume a basic understanding of NVMe. Be prepared to take full advantage of the Summit by upgrading your background with this pre-conference presentation. It assumes no specific knowledge of either PCIe or NVMe. Outline of Topics: Introduction to NVMe NVMe Operation and Structures Command and status Doorbells Queues Interrupts Data flow Controller Memory Buffer Host Memory Buffer Admin Commands Create/Delete Submission/Completion Queues Set/Get Features DWord parameter passing Passing parameters in memory Identify Namespace Management and Attachment I/O Commands Command List Using RDMA NVMe 1.3 Enhancements New Commands Directive Send/Receive Device Self-test Sanitize NVMe-MI Send/Receive Doorbell Buffer Configuration Virtualization Management New Features Time Stamp Host Controller Thermal Management Non-Operational Power State Configuration New Registers Boot Partition Information Boot Partition Read Select Boot Partition Buffer Location New log pages are covered with the new command or feature NVMe 1.4 Enhancement (if released) IO Determinism
About the Organizer/Moderator:
Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.

Monday, August 6th
8:30-Noon
Pre-Conference Seminar C: Persistent Memory (Pre-Conference Seminars Track)
Speaker(s):
Session Description:
Persistent memory offers the cost and capacity advantages of storage devices at memory speed. It also brings opportunities for architecting software applications to utilize its new capabilities. Of course, the tradeoffs involved in using it are far from simple. NAND flash and other types of non-volatile memory behave quite differently from standard DRAM. Handling the differences requires new methods for system integration, programming, and management. Several solutions to the problems involved are currently in use, and several groups are proposing standards for both software and hardware. The obvious advantages of persistent memory indicate that designers will need to be aware of developments in this promising technology area. This seminar will provide an in-depth look into several leading technologies, current implementations, and applications that take advantage of persistent memory in compute and storage systems. Session PM-1: Introduction to Persistent Memory 8:30 -10:15 am Session PM-2 Current Implementations 10:30 - 12:00 noon
About the Organizer/Moderator:
Monday, August 6th
8:30-Noon
Pre-Conference Seminar D: Flash Storage Networking (Pre-Conference Seminars Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology, Mellanox

Speaker(s):
Session Description:
Large storage systems require more complex connections than simple interfaces to achieve maximum efficiency and scalability. Designers want to share storage readily among multiple compute nodes and be able to perform clustering, failover, and other system-wide operations. They thus need networked storage rather than the traditional direct-attached variety. However, networked storage introduces new tradeoffs in terms of cost, complexity, speed, latency, and other factors. Flash storage makes design even more difficult because of its higher bandwidth and performance, thus placing more strain on switches and adapters. Many connection technologies exist, including Ethernet, Fibre Channel, PCI Express, and InfiniBand. Higher-speed versions are available, as well as lower-latency extensions such as Remote Direct Memory Access (RDMA) and iSCSI extensions for RDMA (iSER). Typical issues governing selection include familiarity with particular approaches, existing use, latency and performance requirements, scalability, ecosystem (including management tools), and cost.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Monday, August 6th
10:15-10:30 AM
Break (Pre-Conference Seminars Track)
Paper Presenters:
Session Description:
Coming soon..
About the Organizer/Moderator:
Monday, August 6th
1:00-5:00 PM
Pre-Conference Seminar E: New Non-Volatile Memory Technologies (Pre-Conference Seminars Track)
Organizer + Chairperson + Instructor: Chuck Sobey, Chief Scientist, ChannelScience

Speaker(s):
Session Description:
NAND flash non-volatile memory (NVM) took over 30 years to emerge as a broad-based data storage alternative. But now that flash has established the path, we can expect other new NVM technologies to emerge more quickly. One key is matching each technology's unique characteristics to applications that can benefit from them the most. This pre-conference tutorial introduces the most popular NVM technologies and explains their principles of operation, their pros and cons, and what new developments to expect. You?ll learn the fundamentals of MRAM, phase change memory, 3D XPoint?, ReRAM, memristor, spin-transfer torque, and other emerging technologies, as well as how they fit into the current landscape. The knowledge you gain will help you understand what it will take for any of these to replace flash or to take the lead in persistent memory computing and storage class memory (SCM)! Many new NVM technologies use sophisticated concepts from quantum physics. Your instructor, Chuck Sobey, is well-known for his ability to make difficult technological concepts clear and useful. You?ll be able to ask this veteran storage R&D consultant your most pressing questions and draw on his technical expertise and industry insight. Reliable, unbiased information is critical for making the right decisions! So don?t proceed (and spend a lot of development money) without a clear understanding of the fundamentals of these rapidly-evolving technologies, and where they can make the biggest impact for your company! Get an insider?s view into what?s happening in the industry and what you?re likely to see both near-term and long-term. New NVM Technologies is a great way to get up-to-date quickly and take maximum advantage of your attendance at the Flash Memory Summit. It is also an excellent stand-alone learning experience for those with limited time. Cut through the hype surrounding new NVM technologies! Conquer the fear and apprehension regarding what might replace flash technology! Learn how to ask the tough questions and know when you get the right answers for your application! This tutorial is designed for engineers, managers, and executives who need to make immediate decisions. It is presented by KnowledgeTek, the world?s leading data storage technology training company. Suggested prerequisites include a technical background and interest in data storage; this introductory class does not assume detailed engineering knowledge of chips, drives, non-volatile memory, or storage systems. Course Outline 1. NVM Overview Memory vs. storage? Why do we need new NVM technologies? NVM approaches: Magnetic, charge, phase, filamentary, bulk, etc. Understanding the incumbent: The pros, cons, and future of NAND flash 2. Architectural Commonalities? Access devices? Cross point arrays? Multi-bit per cell approaches? 3D fabrication compatibility 3. Competing (or Co-Existing) Technologies? Phase change memory (PCM, PC-RAM)? 3D XPoint? and QuantX? ? MRAM: Spin-transfer torque (STT-RAM)? ReRAM: Filamentary, interface, bulk, ion transport, memristor? MRAM: Spin-orbit torque (SOT-RAM) 4. System-level Considerations? Endurance and retention? Signal processing and error correction coding (ECC)? Speed, error rate, and power? Controller partitioning 5. Next Steps to Prepare for New NVM Technologies? Considerations for successful prototyping? Enabling neuromorphic computing? The device determines the system ? What to watch for at the Summit!?
About the Organizer/Moderator:
Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer; as well as the Conference Chairperson of the 2018 Flash Memory Summit. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque). As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there. Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara.

Monday, August 6th
1:00-5:00 PM
Pre-Conference Seminar F: NVMe over Fabrics (Pre-Conference Seminars Track)
Organizer + Chairperson + Instructor: Hugh Curley, Consultant, HughCurley.com

Speaker(s):
Session Description:
NVMe over Fabrics extends NVMe to large fabrics as opposed to the single-computer systems of PCIe. NVMe enables deployments with many SSDs using a network interconnect, such as RDMA over Ethernet or its alternatives. Thanks to an optimized protocol stack, an end-to-end NVMe solution will reduce access latency and improve performance, particularly when paired with a low latency, high efficiency transport. Applications can then access SSDs rapidly, regardless of whether they are attached locally or accessed remotely across enterprise or data center networks. Course Outline: NVMe over Fabrics Overview What are fabrics? What is mapping/binding? Why create NVMe over fabrics? What are the differences between Channel I/O and Memory I/O, and between messages and shared memory? RDMA What is RDMA? How RDMA operates Benefits of RDMA Zero Copy OS Bypass Detail of RDMA defined by IETF Reliable/Unreliable Connection/Datagram RDMA queue pairs with NVMe host and target Verbs RDMA operations InfiniBand InfiniBand is an interface ideally suited to handle SSDs and NVMe. It is used primarily in high performance computing, where the rapid transfer of large data files between computers or between computers and storage arrays is critical. To this end, InfiniBand was designed to use RDMA. Ethernet with iWARP or RoCE Ethernet is ubiquitous and high-speed, making it an ideal candidate for a transport protocol. However, Ethernet is not designed to use RDMA, hence the need for a protocol to add RDMA to it. There are two competing alternatives, and this presentation will describe how they both work. Fibre Channel Fibre Channel is most often used to connect Storage Area Networks (SANs) in the enterprise market. Many of the required services for NVMe Over Fabrics Over FC already exist, e.g. Discovery (Name Server), Link Services, Process Login, and Error Recovery. However, Fibre Channel does not support RDMA.
About the Organizer/Moderator:
Storage industry veterans from around the world seek out Hugh Curley when they need to launch technical teams on new data storage interfaces. Since 1997, Hugh has presented, created, and updated KnowledgeTekʼs popular interface training seminars, including Fibre Channel, USB, SAS, SATA, SCSI, ATA, PCI Express (PCIe), and NVMe. Whether the team is focused on design, testing, compliance, implementation, or interoperability, Hugh has the training experience and know-how to quickly deliver useful insight that makes a difference for interface professionals back on the job. Hugh's classroom attendees consistently rate his presentations at the highest level, with comments such as "very thoroughly and clearly presented!", "He answered all of my questions", and "Great training materials." Hugh began his training work with PCs and peripherals and moved through PCI, PCI-X, PCIe, and NVMe. He has also written the definitive books and reference manuals on the SAS interface (“SAS:Beyond the Basics”) and NVMe (“NVMe: Beyond the Basics”). Hugh is continually involved with the T10 standards committee through KnowledgeTek and is a member of NVM Express. KnowledgeTek clients that Hugh currently trains include Broadcom, Microsemi, Micron, Seagate, EMC (Dell), Western Digital, NetApp, Samsung, and Intel.

Monday, August 6th
1:00-5:00 PM
Pre-Conference Seminar G: Bring Your SSD Testing Up-to-Date (Pre-Conference Seminars Track)
Organizer + Chairperson + Instructor: Eden Kim, CEO, Calypso Systems

Speaker(s):
Session Description:
SSDs have changed rapidly in recent years, and organizations and datacenters must keep their test procedures up-to-date. Understanding of the latest SNIA Performance Test Specification (PTS 2.0.1 for corner case tests) and Real World Storage Workload (RWSW) (PTS 1.0 for datacenter storage) will help organizations update their procedures and make their tests more realistic, more complete, and better able to handle the latest workloads and storage architectures. The new specifications include improved or updated corner case and real world workload test methodologies, Real World Storage Workload capture and analysis, test tool coverage, recommended test environment, and test results reporting. Coverage is extended to include the latest developments such as data center server storage, NVMe, NVDIMMs, and the U.2 and M.2 protocols and form factors. The PTS 2.0.1 specification now covers both client and enterprise devices, while the RWSW PTS 1.0 covers data center logical storage. .
About the Organizer/Moderator:
Eden Kim is CEO of Calypso Systems, a leading SSD test vendor. He has been the unquestioned leader in developing test specifications for SNIA and has lectured on the subject around the world. He is chair of the SNIA SSS Technical Working Group and the SSSI Technical Development Committee. Eden has published several papers on SSD performance testing and SSD product architectures. He has presented frequently at past Flash Memory Summits, at SNIA’s Storage Developer Conference, StorageVisions, and many other events. He has also published whitepapers on SSD workloads.

Monday, August 6th
1:00-5:00 PM
Pre-Conference Seminar H: Flash Controller Design (Pre-Conference Seminars Track)
Speaker(s):
Session Description:
Flash controllers are complex systems that must handle a wide variety of effects and situations in SSDs. They must implement properly the flash translation layer (FTL) which converts system-level commands to instructions suited to the actual flash configuration. They must cope with wear, endurance, write amplification, and other issues. And they must be able to work with a variety of flash types and sizes to avoid getting into repeated design cycles. Error-correction techniques are still another issue with complex codes often being used to deal with failures in the underlying medium. FPGAs provide an obvious way to design initial versions and deal with low-volume situations. ASICs or market-standard chips can increase performance or reduce costs in many situations. Designs must also allow for later upgrades to lengthen their lifetimes.
About the Organizer/Moderator:
Monday, August 6th
2:45-3:00 PM
Break (Pre-Conference Seminars Track)
Paper Presenters:
Session Description:
Coming soon..
About the Organizer/Moderator:
Monday, August 6th
5:00-5:30 PM
Break (Pre-Conference Seminars Track)
Paper Presenters:
Session Description:
Coming soon..
About the Organizer/Moderator:
Monday, August 6th
5:30-7:00 PM
Solid State Storage Reception (Pre-Conference Seminars Track)
Session Sponsor: SNIA and the Solid State Storage Initiative
Paper Presenters:
Session Description:
Coming soon..
About the Organizer/Moderator:
Tuesday, August 7th
Tuesday, August 7th
8:30-9:35 AM
CMOB-101A-1: Consumer/Mobile Applications (Consumer/Mobile Applications Track Track)
Organizer + Chairperson: John Geldman, Director, SSD Industry Standards, Toshiba Memory

Paper Presenters:
New Technologies and New Standards Enable New Mobile Applications
Robert Hsieh, Product Marketing Director, Silicon Motion

A Mobile Market Landscape of Storage Products
Hung Voung, Director of Standards, Memory, Qualcomm

M.2 Evolves to Storage’s Benefit
Anthony Constantine, Platform Architect, Intel

Session Description:
Consumer electronics remains a major market for solid state storage. Manufacturers continue to try to improve every aspect of their products, including performance and test procedures. Security is an area of increasing concern. Devices are constantly wearing out, failing, or being discarded. How do we make sure that data on them is completely erased rather than being available for recovery from a discard or trash pile?
About the Organizer/Moderator:
John Geldman is Director SSD Industry Standards at Toshiba. He focuses on standards for cloud storage, HDD and SSD storage devices, data security, and persistent (storage class) memory. His previous standards committee engagements include INCITS T10 and T13, NVMe, PCI-SIG, SATA-IO, TCG, SFF, SNIA, OSF, OCP, and JEDEC. He is well-known as a storage interface leader adept at guiding standards organizations and architecting groundbreaking technical developments. His specialties include SSD architecture, IP development, storage security, and storage card products. He was previously Director Industry Standards at Micron, where he led the company’s participation in such standards bodies as T10, T13, SATA, IEEE 1667, USB, CompactFlash, and the SD Association. He has also worked for Brecis Communications, Basis Communications, and Cirrus Logic. He holds 9 patents and has been recognized for his standards work by the SD Association and INCITS. A frequent blogger and conference contributor, he has been a speaker, organizer, and chairperson at Flash Memory Summit, as well as being a member of the Conference Advisory Board. He holds an MSCS from Santa Clara University and a BSECE from Clarkson University.

Tuesday, August 7th
8:30-9:35 AM
EMBD-101A-1: Embedded Applications - System Design (Embedded Applications Track Track)
Organizer + Speaker: Tom McCormick, Chief Engineer/Technologist, Swissbit

Chairperson: Bill Wong, Sr Content Director/Editor, Electronic Design Magazine

Paper Presenters:
Creating Reliable Embedded Systems with Flash Memory
Scott Phillips, VP of Marketing, Virtium

Flash and File System Co-Design to Increase System Lifetime
Tom McCormick, Chief Engineer/Technologist, Swissbit

Security for Code and Data Protection in Embedded Systems
Grady Lambert, Engineering Director, Swissbit

Getting the Most Out of Performance Specs: Top Ten Points for Embedded Designers
Damien Col, Technical Marketing Manager, Hyperstone

Session Description:
Flash memory is obviously an ideal storage technology for embedded systems, since it is low-cost, low-power, rugged, small, and fast. However, there are still issues for embedded designers to consider, such as relatively short lifetimes, multiple security risks, long-term product availability, and limited software support. Many of the latest technology advances, such as 3D flash and QLC flash, are well-suited to enterprise applications with short useful lifetimes and benign environments, but not to embedded systems that are expected to last a long time in a wide variety of environments. System-level designers must tread carefully in a fast-changing situation.
About the Organizer/Moderator:
Thomas McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development with full lifecycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory system research and development. His on-going research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications. He has designed and developed many integrated hardware and software products as well as software product lines. He has also published articles and presented at many past Flash Memory Summits. He holds a PhD in Computer Engineering from Northeastern University.

Bill Wong is an Embedded/Systems/Software Technology Editor at Electronic Design Magazine. He writes several columns, including the popular Lab Bench, alt.embedded, and Bill’s Workbench hands-on column. He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the technology industry for almost 40 years, including over 15 years with Electronic Design. He is a frequent conference participant as a speaker, chairperson, and organizer, including at the Embedded Systems Conference. He holds a BSEE from Georgia Tech and a Master’s in computer science from Rutgers.

Tuesday, August 7th
8:30-9:35 AM
FTEC-101A-1: Annual Update on Flash Technology (Flash Technology Track Track)
Chairperson: Xinde Hu, Principal Engineer, Western Digital

Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:
Session Description:
Is NAND flash at a crossroads? Is the end of scaling near? How is 3D flash doing? Are the reported production problems real and how important are they? What?s the real story with 3D XPoint? In practice, NAND flash technology keeps advancing with manufacturers reporting successful products at ever-smaller dimensions. 3D flash is in production, as the transition continues. Flash memory remains the dominant non-volatile memory technology near term, and the 3D developments mean it will retain that status for years to come.
About the Organizer/Moderator:
Xinde Hu is currently Principal Engineer at Western Digital. His responsibility includes creating, designing, and evaluating innovative system architecture concepts and implementations for the next generations of non-volatile memory based storage systems. Before joining Western Digital, Dr. Hu worked for STEC and STMicroelectronics as a system architect. Dr. Hu has authored more than a dozen technical papers on coding/signal processing for data storage systems and has 40+ patent applications pending. He is currently Vice Chairman of the IEEE Data Storage Technical Committee (DSTC). He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.

Leah Schoeb is a Sr. Developer Relations Manager in the platform architecture team at AMD, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, with the last decade in solid state technology. She is also the Founding Data Architect at Data Glass, where she assists systems companies with performance engineering and optimization, market positioning, and benchmarking. She was previously Acting Director Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as the Industry Trends Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC), and Storage Networking Industry Association (SNIA). She is a member of the SNIA Technical Council and a co-founder of their Solid State Storage System Technical Work Group. She earned an MBA at the University of Phoenix and a BSEE at the University of Maryland, College Park.

Tuesday, August 7th
8:30-9:35 AM
INVT-101A-1: An All-NVMe Performance Deep Dive into Ceph (Software Track Track)
Chairperson: Deepankar Das, CTO, Sureline Systems

Paper Presenters:
An All-NVMe Performance Deep Dive into Ceph
Ryan Meredith, Principal Storage Solutions Engineer, Micron

Session Description:
Recent significant Ceph improvements, coupled with NVMe technology, will broaden the classes of workloads that Ceph can handle. The compelling speed and low latency of NVMe SSDs are obvious, but optimally harnessing them for I/O-intensive applications in shared VM storage environments is often non-trivial. An example describes the work involved in designing, deploying, tuning, and testing the latest all-flash accelerated Ceph reference platform leveraging NVMe SSDs. A new tuning and performance testing methodology had to be developed. Performance results cover FileStore vs. BlueStore optimizations with all-NVMe clusters for the latest Ceph version (called Luminous).
About the Organizer/Moderator:
Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Tuesday, August 7th
8:30-10:50 AM
ARCH-101-1: Flash-Memory Based Architectures: A Technical Discussion, Part 1 (Architectures Track Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
A Machine Learning Framework for NAND Flash Lifetime Extension
Lorenzo Zuolo, Flash Engineer, Microsemi

Introduction to Open-Channel SSDs
Matias Bjoerling, Director Solid State System Software, Western Digital

How Open-Channel SSDs Benefit Data Center and Enterprise Applications
Rick Huang, Product Marketing Manager, Silicon Motion

SSD Architecture Requirements for IO Determinism
Tim Canepa, Chief Architect and Director of Architecture, Independent Consultant

Session Description:
There are currently several approaches to handling low-level SSD operations such as data placement and garbage collection. The standard approach has been to embed the details inside the Flash Translation Layer (FTL). The driver then only has to perform straightforward input and output operations. However, hyperscale operators want to be able to control everything from the system software in order to obtain more efficient operations and minimize latency. I/O determinism and the open-channel SSD offer more flexibility at the cost of more complex system software. In general, clouds and other hyperscale operators prefer greater control while smaller data centers prefer the simpler interface.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 7th
8:30-10:50 AM
AUTO-101-1: Flash in Autonomous Vehicles, Part 1 (Automotive Applications Track Track)
Chairperson: Greg Basich, Associate Director, Automotive Infotainment and Telematics and Connected Mobility Services, Strategy Analytics

Organizer: Andy Marken, President, Marken Communications

Paper Presenters:
Memory security of Automotive Systems
Crystal Chang, Senior Manager, ATP Electronics

F-RAM for Automotive Event Data Recording in ADAS
Doug Mitchell, Member of the Professional Staff, Cypress Semiconductor Corp.

SLC NAND gains momentum in Autonomous Driving camera applications
Anil Gupta, Technical Executive, Winbond Electronics

Session Description:
Automotive Security, Privacy I - What Is Under The Hood The autonomous car will only emerge because of the CPU/GPU, storage and a few rules of the road. Now is the time to get your hands greasy and be part of the totally new way of getting around. CPUs will be checking, monitoring, capturing - and wanting to store - data from the wheels up. Thousands of firms are spending big to have a place in tomorrow's transportation. It isn't exhaust fumes you smell, it's money, and this session will keep you from being left in the dust. Find out how the industry wants to/plans to keep all that data is secure and private. This panel will inform you about the security and privacy issues. They'll discuss the practical and global issues. Learn how self-encrypting flash storage could satisfy everyone in the ecosystem ...and you! Advanced Auto Security, Privacy II - A Foolproof Solution When the Fool Doesn't Drive There are more electronic engineers and programmers in auto firms today's than car designers/specialists. They have one goal (beside selling more cars than the next guy) - make sure the computation and storage are fast, reliable, accurate, and safe enough to be around people. The panel details advanced computational architectures storage must support to be included. Find out firsthand about advanced IoT systems that are being developed. Learn about security/privacy issues your products need to address to be included in vehicles. Understand what your organization and you must provide to be included in the safe, secure, private, moving computer/storage system.
About the Organizer/Moderator:
Greg Basich is the Associate Director with Strategy Analytics’ Automotive Infotainment & Telematics service and the company’s Automotive Connected Mobility service. He has been with Strategy Analytics for more than 4 years after a previous 13-year career as a business-to-business automotive journalist. At Strategy Analytics, Greg focuses on a number of topics, including connected car technologies and business models, automotive infotainment, mobility services, and automotive cyber security.

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Tuesday, August 7th
8:30-10:50 AM
BMKT-101-1: Flash Growth & Opportunity in China, Part 1 (Business/Marketing Track Track)
Co-Organizer + Co-Chair: Chuck Sobey, Chief Scientist, ChannelScience

Organizer + Chairperson: Jerome Luo, President, Sage Microelectronics

Paper Presenters:
Developing Controllers That Are Aware of Underlying NAND Structure
Hongjun Xue, R&D Chief Architect, UNIC

Struggling while Booming NVM Eco-system in China
Zhiqiang Su, Director of Strategic Marketing, GigaDevice Semiconductor.

New NVM Device Research
Ming Liu, Academician, Academy of Science of China

China Flash Memory Technology and Market Landscape
Xinwu Zheng, CEO & Founder, DOIT Media Group

New Trends for Storage in Edge Computing
Banghong Chen, Senior Manager, Keyway Technology Co. LTD

Build a Key Value Flash-Based Storage System
Wei Zha, Chief Technology Planner of Storage Product, Huawei

Session Description:
China is today a major player in both using and developing flash products. Those working at organizations outside China need to understand what is happening currently at Chinese companies, universities, and other organizations. The Chinese market offers many potential opportunities for products, services, and collaboration. Interests range throughout the non-volatile memory area, including development of new technologies, enterprise storage, embedded applications, and hyperscale datacenters.
About the Organizer/Moderator:
Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer; as well as the Conference Chairperson of the 2018 Flash Memory Summit. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque). As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there. Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara

Jianjun (Jerome) Luo is the founder and president of Sage Microelectronics, a provider of ICs and solutions for digital storage and data security applications (including SSD controllers) with offices in both Silicon Valley and Hangzhou, China. Jerome is also a Professor and Director of the Microelectronic Research Institute at Hangzhou Dianzi University. Jerome helped organize the first flash memory conference held in China (the China Flash Forum held in Beijing on October 23, 2014). He has been an ASIC design engineer and Director of R&D at Initio and has designed more than 10 ASICs. He earned a PhD in semiconductor technology from Zhejiang University, a Master’s in Microelectronics from the Hangzhou Institute of Electronics Engineering, and a Bachelor’s in Electronics Engineering from Shanghai Jiaotong University.

Tuesday, August 7th
8:30-10:50 AM
ENAP-101-1: Enterprise Applications, Part 1 (Enterprise Applications Track Track)
Organizer + Chairperson: Tom Burniece, President, Burniece Consulting Services

Paper Presenters:
Storage Class Memory the next turbo for Databases
Edward Duarte, Sr Product Manager,, HPE

Clearwater Analytics Accelerates SaaS Workloads with Kaminario
Derek Swanson, CTO, North America, Kaminario

Oracle Exadata: Achieving Memory-Level Performance with NVME Flash
Gurmeet Goindi, Master Product Manager, Oracle

Accelerating Image Processing for Object Storage
Sean Gardner, Sr. Product Marketing Manager, Xilinx

Reducing Business Risk with Flash
Summer Matheson, Product Marketing Manager, Hitachi Data Systems

Ryan Rady, , National Government Services (Anthem)
Software-defined Storage and the Customer Path to NVMe-oF, Parts 1 & 2
Benjamin Treiber, Sr. Director, Engineering Product Management, DataCore Software

Session Description:
Flash memory has revolutionized storage system and computing architectures for many enterprise applications. Actual case studies from innovative storage companies, including descriptions of the problem, approach, and results, provide examples of practical situations. Applications will include SQL and NoSQL databases, OLTP, data warehousing, big data analytics, Hadoop/MapReduce, financial transactions, and in-memory computing. Customers will co-present with some speakers.
About the Organizer/Moderator:
Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Tuesday, August 7th
8:30-10:50 AM
NVME-101-1: NVMe Roadmaps and Market Data/Architectures (NVMe Track Track)
Session Sponsor: NVM Express
Organizer + Chairperson: Brandon Hoff, Software Architect, Broadcom

Paper Presenters:
Session Description:
Part 1: Annual Update NVMe continues to extend its domination of storage infrastructures. New markets keep opening up, and new features continue to be added. New features in the latest NVMe update include self-test, boot partitions, sanitize, standard virtualization features set, multiple sector sizes, directives support, more flexible power management, and host-controlled thermal management. New features in the latest NVMe-oF work will add TCP to the wide range of protocols that support NVMe. Future additions will add more utilities and advanced features, provide more detailed management control, and allow closer interaction with widely used system software. The specification will handle an ever wider range of storage issues for even more applications, including computers, high-performance systems, embedded systems, and industrial/process control, as well as enterprise storage. Part 2: Architectures NVMe keeps adding features storage designers need to handle applications ranging from clouds to clients. Real-world implementations show the benefits and impacts of NVMe on environments such as hyperscale data centers, enterprise data centers, and client (laptop) computers.
About the Organizer/Moderator:
Brandon Hoff is Distinguished Software Architect at Broadcom, where he focuses on new product strategy, including product development interlock, business planning, and sales strategy development for growth initiatives. He has also worked on innovation initiatives, end user strategies, technology and strategy solutions for Web giants, and product portfolio leadership. He has been an active participant in NVM Express, the sponsoring organization for NVMe standards, and has also been IBTA Marketing Work Group Co-Chair. He is a frequent participant at industry events, including NVM Express meetings, SNIA conferences, and Ethernet Alliance events. He has over 25 years of industry experience, including a stint as Chief Strategy Officer/Chief Marketing Officer at CipherOptics, where he was responsible for managing all aspects of marketing, corporate strategy, product management, field and corporate marketing, marketing communications, public relations, branding, and lead generation. He holds an MBA from the University of Colorado (Boulder) and a BSEE from Colorado State University.

Tuesday, August 7th
8:30-10:50 AM
PMEM-101-1: Advances in Persistent Memory (Persistent Memory Track Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Chairperson: Stephen Bates, CTO, Eideticom

Paper Presenters:
Persistent Memory Technology Roadmap and Market
Mark Webb, President, MKW Ventures

Why Persistent Memory Matters - How Did We Get Here, and What Lies Ahead?
Jim Pappas, Director, Initiative Marketing, Intel Server Platforms Group

Current Status and Overview of Standards Related to Persistent Memory
Rob Peglar, President, Advanced Computing and Storage

The SNIA Persistent Memory Security Threat Model
Mark Carlson, Technical Council Co-Chair, SNIA

Session Description:
Persistent memory offers fast, byte-addressable access to data that persists! No more waiting endlessly for accesses to load data into memory or doing task switches to find something that can make progress during the wait. Obviously, the advance should mean huge speedups for applications that can’t currently keep all their data in memory, such as database, big-data analytics, and hyper-converged platforms. It is already proving to be great for accelerating applications such as Microsoft SQL, VDI, and high-availability storage. But what about the software? It is currently all written and optimized to still copy data from memory to storage. Architects, developers, end user adopters, and vendors of today’s persistent memory must understand what development tools, platforms, management tools, and applications are currently available or in-progress to harness this new approach in their systems.
About the Organizer/Moderator:
Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Speaker Bio: Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Speaker Bio: Mark A. Carlson, Principal Engineer, Industry Standards at Toshiba, has more than 35 years of experience with Networking and Storage development and more than 20 years experience with Java technology. Mark was one of the authors of the CDMI Cloud Storage standard. He has spoken at numerous industry forums and events. He is the co-chair of the SNIA Cloud Storage and Object Drive technical working groups, and serves as co-chair of the SNIA Technical Council.

Tuesday, August 7th
9:45-10:50 AM
DPRO-101B-1: Data Recovery of SSDs (Data Protection Track Track)
Session Sponsor: Ontrack Data Recovery
Organizer + Chairperson: Troy Hegr, Sr. Manager Global BD, Ontrack Data Recovery

Paper Presenters:
Data needed from Drones? Yes, and the data is rich. Recovery of a drone.
Will DeLisi, NAND Flash Recovery Specialist, DriveSavers Data Recovery

Josey Santana, , DriveSavers Data Recovery
Recovering Data from 3D NAND-Based Devices
Robin England, Hardware Research & Development Team Lead, Ontrack Data Recovery

Session Description:
SSDs are very reliable data storage devices. But when something goes amiss, users need to know what considerations should be taken into account to access and protect your organization's sensitive data? How is inaccessible data recovered from SSDs? Are SSDs designed to make finding lost data easier? When should one engage a data recovery specialist? How do you ensure your sensitive data is securely erased and sanitized from an SSD at the end of its useful life? Data recovery experts, digital forensic specialists, and SSD manufacturers will discuss the technology and science behind data recovery and data sanitization from flash based storage. If you've ever experienced data loss, want to know how to effectively plan and be prepared in the event of data loss, or need to know who the experts are and what they do, this is a must-attend session!. Attendees will gain an in-depth understanding of the effort involved in restoring lost data from an SSD, and how to ensure sensitive data is protected and erased when an SSD is at the end of its useful life or needs to be repurposed for other uses.
About the Organizer/Moderator:
Troy Hegr, Sr. Manager Strategic Alliances at DriveSavers Data Recovery, helps facilitate discussion in the technical community with leading data storage and computer system designers, manufacturers and industry groups. Mr. Hegr benefits from over 25 years of experience. Prior to joining DriveSavers in 2016, he worked at Ontrack Data Recovery (Kroll Ontrack) for over two decades leading numerous roles including engineering, eDiscovery/ forensics, operations management, and head of Research & Development as Technology Manager.

Tuesday, August 7th
9:45-10:50 AM
EMBD-101B-1: Embedded Applications - Drive Design (Embedded Applications Track Track)
Organizer: Tom McCormick, Chief Engineer/Technologist, Swissbit

Chairperson: Bill Wong, Sr Content Director/Editor, Electronic Design Magazine

Paper Presenters:
Improving the Performance of M.2 NVMe SSDs at Industrial Temperatures
Peter Huang, Senior Manager, Product Management, ATP Electronics

One-Chip Flash Solution for Industrial Applications
Chanson Lin, Founder/CEO, EmBestor Technology

Is NVMe Right for Mil/Industrial Applications?
Chris Budd, Director Engineering, SMART High Reliability Solutions

Session Description:
Embedded systems have long used flash memory to support highly diverse system features and functionality under a wide range of operating conditions. In recent years, cost pressures from consumer applications have reduced the performance characteristics of the most widely available flash memory devices and have strained their ability to meet the more stringent reliability requirements of embedded applications. Embedded flash must have special characteristics to meet industrial, mil/aero, and other applications? needs in areas such as temperature, pressure, operating lifetime, shock, vibration, EMI, RFI, and radiation exposure.
About the Organizer/Moderator:
Tom McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development and full life cycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory product research and development.. His ongoing research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications. He has presented at Flash Memory Summit and the Non-Volatile Memory Workshop, and has published an article on embedded flash in EE Times. He holds a PhD in Computer Engineering from Northeastern University, an MBA and an MS in Computing Engineering from the University of Massachusetts at Lowell, and an MSME and BSME (summa cum laude) from Drexel University.

Bill Wong is an Embedded/Systems/Software Technology Editor at Electronic Design Magazine. He writes several columns, including the popular Lab Bench, alt.embedded, and Bill’s Workbench hands-on column. He has written a dozen books and was the first Director of PC Labs at PC Magazine. He has worked in the technology industry for almost 40 years, including over 15 years with Electronic Design. He is a frequent conference participant as a speaker, chairperson, and organizer, including at the Embedded Systems Conference. He holds a BSEE from Georgia Tech and a Master’s in computer science from Rutgers.

Tuesday, August 7th
9:45-10:50 AM
ENST-101B-1: Annual Update on Enterprise Flash Storage (Enterprise Storage Track Track)
Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Chairperson: Rohit Gupta, Segment Manager, Enterprise Storage Solutions, Western Digital

Panel Members:
Session Description:
Enterprise flash storage continues to advance from being a faster plug-in replacement for disk drives to being a storage layer on its own. The original SSD conception obviously allowed storage designers to use the mature hardware and software ecosystem available for HDDs, adding only the Flash Translation Layer to make the necessary adjustments. However, this approach still left SSDs with all the disadvantages of disk storage including its complexity and low speed. NVMe has now brought a standardized high-speed parallel interface to solid-state storage, allowing it to act as a high performance tier in all-flash arrays, and now allowing it to be readily networked through the new NVMe Over Fabrics (NVMe-oF) standard. The world of NVMe-oF expanded rapidly this year from ultra-low latency JBODs to high-performance, low latency arrays with a full set of data services. Even more improvement is on the way, as we begin to treat solid-state storage as memory rather than as a peculiar form of disk drive. This advance will bring great change as in-memory databases become both truly all in memory and as persistent as traditional DBMSes. Low latency RDMA networks, which are also used by NVMe-oF, will allow an application to use memory semantics to write into another system?s non-volatile memory address space. This session will examine the development of these technologies into products enterprises can deploy, and the applications such products can best address. We?ll also look into our murky crystal ball a little and predict what users can expect to see over the next 2-3 years.
About the Organizer/Moderator:
Leah Schoeb currently works at Rubrik as a Master Technologist and brings expertise ranging from cloud infrastructure and virtualization to system and data infrastructure performance. Her latest work with infrastructure optimization and solid state technology. She draws over many years of experience in the computer industry helping systems companies with performance engineering and optimization, market positioning, benchmark evidence creation, and guiding industry standards development for system, virtualized, containerized, and data solutions. Leah has served in several leadership roles for performance architecture for companies, such as, Turbonomic, VMware, Sun Microsystems, Dell, Intel, and Amdahl.

Coming soon..

Speaker Bio: Howard Marks has been writing, speaking, and consulting about enterprise technology for over thirty years. As a consultant, he has designed storage, server, and network infrastructures for organizations such as The State University of New York (Purchase), BBDO Worldwide, and the Foxwoods Resort Casino. He also operates an independent laboratory (DeepStorage) which tests storage products for both vendors and magazines. He started testing and reviewing products at PC Magazine in the late 1980s and has written hundreds of articles and product reviews for such media as Network World, Network Computing, and InformationWeek. A top rated speaker at industry events, he has spoken at Storage Decisions, Interop, and Microsoft’s TechEd. He has also developed training programs for organizations such as JP Morgan and American Express.

Tuesday, August 7th
9:45-10:50 AM
INVT-101B-1: Hardware Acceleration of Storage for Composable Infrastructure (NVMe-over-Fabrics (NVMe-oF) Track Track)
Chairperson: Xiaobing Lee, , Independent Consultant

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Hardware Acceleration Techniques for NVMe-oF
Bryan Cowger, VP Sales/Marketing, Kazan Networks

Session Description:
The move to composable Infrastructures is being driven by large datacenters seeking increased business agility and lower TCO. It requires new remote-attached storage solutions which can deliver extremely high data rates with minimal latency. Unfortunately, the industry-standard embedded processors used in controllers aren't fast enough to manage complex protocols at the required speed. For example, they cannot keep up with the work required to access NVMe SSDs efficiently over an NVMe-oF networked infrastructure. The solution is to add accelerators, typically built using an ASIC, FPGA, or other high-speed hardware. The accelerators offload the processing of protocols such as RDMA, TCP, and NVMe. The result is essentially the same performance for remote storage accessed over a network as for direct-attached storage. The combination provides an optimal blend of high performance, low power, and low cost to yield tremendous CAPEX and OPEX savings in the next-generation datacenter. The technology enables virtually limitless scalability, and will drive dramatically lower TCO for hyperscale and as-a-service datacenter applications.
About the Organizer/Moderator:
Coming soon..

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 7th
9:45-10:50 AM
TEST-101B-1: The Performance Story: An Independent Evaluation of Flash Storage (Testing Track Track)
Organizer + Speaker: Dennis Martin, Sr Analyst, Principled Technologies

Chairperson: Kimball Brown, Sr Director Alliances, BlackRidge Technology

Paper Presenters:
The Performance Story: An Independent Evaluation of Flash Storage
Dennis Martin, Sr Analyst, Principled Technologies

Session Description:
Everyone (designers, marketers, salespeople, executives, and customers) wants to know how flash storage really performs. And they want to know it from an independent source using real-world applications. Demartek will report on vendor-neutral performance tests run on database and virtualization workloads typical of today?s data centers. The tests cover systems from several manufacturers, using a variety of form factors and interfaces and including both block and file protocols. Attendees will get good estimates of what to expect in practice, since the tests are independent and focus on current applications and environments. Demartek will also discuss recent advances such as NVMe over Fabrics (NVMe-oF) and high-speed interfaces such as 100 GbE and 32Gb Fibre Channel. Vendors will learn how their products shape up and where they should put their efforts.
About the Organizer/Moderator:
Dennis Martin is the founder and President of Demartek, an analyst firm focused on validation and performance testing of data center products. Demartek has its own fully equipped, modern test lab with the servers, networking and storage gear found in today’s data centers. Its widely recognized reports cover products and technologies from both well-known vendors and startups, including Broadcom, Cavium, Cisco, Dell EMC, HPE, IBM, Intel, Microsemi, NetApp, Nimbus Data, Pure Storage, Samsung, Seagate, Toshiba, Western Digital and others. Demartek also produces popular industry references, including its “Storage Interface Comparison” covering every interface used by storage systems and its “SSD Deployment Guide” that explains everything you need to know to deploy flash-based storage systems in the datacenter. Dennis’ commentary “NVMe over Fabrics Rules of Thumb” is a must-read for those designing storage systems that will take advantage of NVMe devices with multiple network adapters for network fabrics. Dennis is frequently quoted in the press (in such outlets as TechTarget, Market Watch, and Street Insider) on such topics as best practices for deploying SSD technologies and analyzing performance claims for all-flash arrays. A 38-year veteran of the technology industry, Dennis was previously a Senior Analyst with Evaluator Group and a marketing and engineering executive with StorageTek.

Kimball Brown is Senior Director Alliances at security software firm BlackRidge Technology. He was previously a Technical Strategist at VMware, where he drove all product management and engineering workstreams between VMware HP and later Cisco. He has also been VP Senior Datacom Analyst at LightCounting, VP Business Development at Server Engines, and VP Marketing at server adapter maker Neterion. He also spent six years at Gartner as VP Chief Analyst Servers. He has long experience in the server market managing OEM and partner relationships, writing press releases, managing trade shows, developing company revenue forecasts and valuation models, and interacting with analysts and press. He has written many articles and spoken at many events. Kimball earned an MBA from UC Berkeley and a BSEE from Duke University.

Tuesday, August 7th
3:40-4:45 PM
BMKT-102A-1: Flash Growth and Opportunity in China, Part 2 (CEO Panel) (Business/Marketing Track Track)
Co-Organizer + Co-Chair: Chuck Sobey, Chief Scientist, ChannelScience

Organizer + Chairperson: Jerome Luo, President, Sage Microelectronics

Panel Members:
Panelist: Minghau Lee, President, Epostar Electronics

Panelist: Michael Wang, VP, GigaDevice Semiconductor

Panelist: Ming Liu, Academician, Academy of Science of China

Panelist: Robert Lee, CTO of Apacer Technology Inc., Apacer Technology

Panelist: Shu Li, Director, Alibaba

Panelist: KS Pua, Chairman, Phison Electronics

Session Description:
Need to know what’s going on with regard to China and Chinese companies? Relations between the US and China seem to change daily. What are the latest regulations and requirements? What can organizations do and who can they do business with? Get the latest status at this session which will cover breaking news, short-term and long-term trends, best practices, current recommendations, and best sources of information.
About the Organizer/Moderator:
Chuck Sobey is an internationally-respected technology advisor, researcher, and lecturer; as well as the Conference Chairperson of the 2018 Flash Memory Summit. He is the founder of the confidential R&D services firm ChannelScience, which works with startups, Fortune 100 companies, and large institutions to develop new capabilities in data storage and establish the state-of-the-art. He has deep expertise in the design, function, manufacture, and test of data storage devices. Chuck is currently applying machine learning techniques to reduce R&D cycle times and is developing signal processing and coding algorithms matched to the physics of STT-MRAMs (spin transfer torque). As China focuses on flash as a strategic initiative, Chuck was honored to give the opening technical keynote address at the first flash conference held there. Chuck is an electrical and computer engineering graduate of Carnegie Mellon University and the University of California at Santa Barbara

Jianjun (Jerome) Luo is the founder and president of Sage Microelectronics, a provider of ICs and solutions for digital storage and data security applications (including SSD controllers) with offices in both Silicon Valley and Hangzhou, China. Jerome is also a Professor and Director of the Microelectronic Research Institute at Hangzhou Dianzi University. Jerome helped organize the first flash memory conference held in China (the China Flash Forum held in Beijing on October 23, 2014). He has been an ASIC design engineer and Director of R&D at Initio and has designed more than 10 ASICs. He earned a PhD in semiconductor technology from Zhejiang University, a Master’s in Microelectronics from the Hangzhou Institute of Electronics Engineering, and a Bachelor’s in Electronics Engineering from Shanghai Jiaotong University.

Tuesday, August 7th
3:40-4:45 PM
BMKT-102A-2: Know What the Enterprise Flash Customer Wants and Needs (Business/Marketing Track Track)
Organizer: Jay Kramer, President, Network Storage Advisors

Chairperson: Dave Raffo, Editorial Director, TechTarget

Panel Members:
Panelist: Marc Staimer, President, Dragon Slayer Consulting

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Brian Schwarz, VP Product Management, Pure Storage

Panelist: Josh Epstein, Chief Marketing Officer, Kaminario

Session Description:
All-flash arrays (AFAs) are the fastest growing segment of the storage industry. To gain market share in this highly competitive area, vendors must have a good handle on what customers are looking for. Is it capacity, performance, scalability, the latest technologies, the best selection of storage utilities, support, management features, IOPS, ease of use, or just plain old prices? How are preferences changing in the light of ever-larger datasets, faster storage (with NVMe), more networking (with NVMe-oF), more complex applications, and greater reliance on clouds rather than in-house data centers? TechTarget presents market research data spotlighting the customer movement toward the all flash data center with high-speed networks making flash accessible everywhere. An expert panel addresses today’s killer apps and highest-priority use cases for AFAs.
About the Organizer/Moderator:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Dave Raffo is Editorial Director of TechTarget’s Storage Group, and the leading U.S. media source on storage. He leads the tech publisher’s coverage of storage, data protection, and hyperconvergence, and is responsible for the SearchStorage.com, SearchDataBackup.com, SearchCloudStorage.com, SearchDisasterRecovery.com, and Search ConvergeInfrastructure.com websites. The sites generate millions of page views per year, and not a single instance of fake news can be found on them. Dave has covered storage full-time since his days at Byte and Switch in 2003, and he had written thousands of stories on storage companies, markets, news and technology since then. He was TechTarget Editor of the Year in 2015, and he and his TechTarget storage team have won bushels of American Society of Business Professional Editors (ASBPE) awards. He has also worked Managing Editor of EdTech Magazine, Features and New Products Editor of Windows Magazine, and Technology Editor of the eLearning company WatchIT. He also has been an editor/reporter for United Press International (UPI). He earned a BA in communications/ journalism from William Paterson University of New Jersey, and has presented at recent Flash Memory Summits on flash customer needs.

Tuesday, August 7th
3:40-4:45 PM
CTRL-102A-1: Annual Update on Flash Controllers (Controllers Track Track)
Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Chairperson: Mike McKean, Director, Encore Semi

Paper Presenters:
Session Description:
The development of high-speed, well-designed, and low-cost controllers has been a key factor leading to wider use of flash memory. Controllers must account for flash?s special features, as well as providing error correction, wear management, and high availability. The controller market has also been in a state of flux with new entrants constantly appearing while old stalwarts are acquired or lose their technical edge. The big news in the last year has been the rapid emergence of NVMe and NVMe-oF controllers, which appear ready to dominate the market. There has also been interest in higher-speed and lower-latency controllers and in ones that can be managed more precisely (via I/O determinism) and networked efficiently.
About the Organizer/Moderator:
Leah Schoeb currently works at Rubrik as a Master Technologist and brings expertise ranging from cloud infrastructure and virtualization to system and data infrastructure performance. Her latest work with infrastructure optimization and solid state technology. She draws over many years of experience in the computer industry helping systems companies with performance engineering and optimization, market positioning, benchmark evidence creation, and guiding industry standards development for system, virtualized, containerized, and data solutions. Leah has served in several leadership roles for performance architecture for companies, such as, Turbonomic, VMware, Sun Microsystems, Dell, Intel, and Amdahl.

Mike McKean is currently Director of Sales at Encore Semi, a design services firm focused on ASIC and firmware/software design and development. At Encore Semi, he leverages his ASIC and firmware background to grow key accounts and support projects with technical skills. He is currently leading firmware development for projects using multiple SSD controller architectures. Before joining Encore, Mike was VP Product Solutions at cybersecurity startup FHOOSH and General Manager for the Colorado Design Center of Synapse Design Automation. At Synapse, Mike led the successful execution of multiple HDD, SDD, and consumer electronics projects. He has 30 years experience in the semiconductor and systems industries. Mike is a regular presenter, chairperson, and organizer at Flash Memory Summit. He earned an MBA from the University of Texas at Austin and a BS in Engineering Science from Trinity University (TX).

Tuesday, August 7th
3:40-4:45 PM
INVT-102A-1: Enabling I/O Determinism in Hyperscale Data Centers (Enterprise Storage Track Track)
Chairperson: Xinde Hu, Principal Engineer, Western Digital

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Enabling IO Determinism in Hyperscale Data Centers
Chris Petersen, Hardware Systems Technologist, Facebook

Session Description:
SSD I/O isolation and latency control in multi-tenant cloud applications have become increasingly important, especially as the capacity of the physical drives grows larger. Working with the major cloud providers and SSD vendors, Facebook has led the industry to standardize two NVMe Technical Proposals that strive to tackle the problems. NVM Sets and Read Recovery Levels enables partitioning of a physical SSD into multiple independent quality of service (QoS) isolated NVMe namespaces. I/O Determinism (IOD) gives the host software stack the control of SSD background operations in order to achieve deterministic I/O behavior. This talk presents a Linux-based software architecture and the test results using Facebook workloads that improves the read I/O latency distribution while leveraging the NVMe Sets and I/O Determinism standards. In a nutshell, the architecture builds on top of the basic RAID developed using IOD-capable SSDs. By mediating the deterministic and non-deterministic windows of the SSDs in the RAID group as defined in the I/O Determinism specification, we can service the read I/O from the SSDs in the deterministic window.
About the Organizer/Moderator:
Xinde Hu is currently Principal Engineer at Western Digital. His responsibility includes creating, designing, and evaluating innovative system architecture concepts and implementations for the next generations of non-volatile memory based storage systems. Before joining Western Digital, Dr. Hu worked for STEC and STMicroelectronics as a system architect. Dr. Hu has authored more than a dozen technical papers on coding/signal processing for data storage systems and has 40+ patent applications pending. He is currently Vice Chairman of the IEEE Data Storage Technical Committee (DSTC). He received his PhD in Electrical and Computer Engineering from Carnegie Mellon University.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 7th
3:40-4:45 PM
SECU-102A-1: New Directions in Security (Security Track Track)
Organizer + Chairperson: Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Organizer + Speaker: Paul Suhler, Storage Architect, Micron Technology

Paper Presenters:
Hardware-Accelerated Security Offloads for Networked Storage
Bob Doud, Senior Director of Marketing, Mellanox

A Certification Program for Sanitizing SSDs
Paul Suhler, Storage Architect, Micron Technology

Session Description:
This session will explore issues and challenges in securing data on flash memory devices and systems. It will pose related issues and opportunities and will discuss how technologies and market trends are impacting deployment of such systems in large government and private organizations. Topics covered will include self-encrypting storage, standards, secure erasure and elimination, encryption, trusted storage, embedded and industrial computing applications, and security for flash drives, SSDs, and industrial devices.
About the Organizer/Moderator:
Bob Thibadeau is Chairman and CEO of the Drive Trust Alliance (DTA). Previously he was Chief Technologist for Seagate Technology and the originator of the Trusted Computing Group’s Self-Encrypting Drive (SED) Technologies. Currently the DTA has developed “Auto Erase” key management technology for SEDs in Automotive and other system IoT situations where SEDs are physically distributed in the IoT system (drivetrust.com/auto-erase). Previously, he headed projects in Robotics at Carnegie Mellon University for the major Automotive OEMs which resulted in nearly universal adoption of his inventions.

Paul Suhler is a storage architect in SSD engineering at Micron Technology, where he is responsible for NVMe interfaces and for educating internal teams as well as customers. He is Micron's primary representative to the NVMe Technical Work Group to which he has contributed many proposals. He is also active in the SFF Technical Work Group, having chaired working groups on the U.3 specification, Ethernet drive connectors, and Ethernet speed negotiation. He has worked in the data storage industry for over twenty years at companies including HGST, Quantum, Seagate, and Adaptec. He has also been a member of the research faculty at the University of Southern California. He received the INCITS Technical Excellence Award, and is a Senior Member of IEEE. He holds a PhD and BS in computer engineering from the University of Texas at Austin, and an MS in computer engineering from the University of California, Berkeley. He is the author of papers and journal articles on parallel computing.

Tuesday, August 7th
3:40-6:05 PM
ARCH-102-1: Flash-Memory Based Architectures: A Technical Discussion, Part 2 (Architectures Track Track)
Session Sponsor: CNEX Labs
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
Project Denali Open-Channel SSDs
Javier Gonzalez, Software Engineer / Team Lead, CNEX Labs

QLC and Mixed Mode SSDs Require Deep FTL-Tuning
Karl Schuh, Senior Firmware Architecture Manager, Micron

The Reality of an NVMe IO Deterministic Drive Using QLC
Steven Wells, Fellow – SSD Data Center Architecture, Toshiba

Transforming an SSD into a Cost-Effective Edge Server
Neil Werdmuller, Director, Storage Solutions, Arm Holdings

Session Description:
Architects continue to examine a variety of ways to increase flash performance and allow for upgrades in technology. Typical approaches include aligning pages and blocks and examining the details of write amplification to minimize its effects. A self-learning flash translation layer (FTL) helps avoid the problem of obsolescence caused by technology advances. A more cosmic approach is to handle the emergence of persistent memory and ultra-high-speed networks by treating everything as super-fast memory.and avoiding the need for long delays or transfers that bypass standard processor channels.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 7th
3:40-6:05 PM
AUTO-102-1: Flash in Autonomous Vehicles, Part 2 (Automotive Applications Track Track)
Organizer: Andy Marken, President, Marken Communications

Chairperson: Allan McLennan, Chief Executive / Analyst, PADEM Media Group

Paper Presenters:
Data is the new horse power
Russell Ruben, Director of Marketing for Automotive Solutions, Western Digital

Solving functional safety challenges in automotive with NOR Flash Memory
Sandeep Krishnegowda, Marketing Director, Flash Business Unit, Cypress Semiconductor

Why NV Storage in Automobiles Must Employ Industry Standard Hardware Encryption
Robert Thibadeau, Chairman/CEO, Drive Trust Alliance

PCIe BGA SSD for Automotive Applications
Mason Chen, Product Marketing Manager, Silicon Motion

AI/ML intelligence
Allan McLennan, Chief Executive / Analyst, PADEM Media Group

The End-to-End Storage Challenge of Autonomous Transportation
Eric Stouffer, VP Distributed Storage BU, IBM

Session Description:
Automated and Connected Vehicles - Storage Beyond the Trunk It feels like everyone wants to sell their products into the fully automated, advanced driver-assisted sensor (ADAS) connected car. Find out where the sensor-based, video-oriented electronic systems are being designed in. Learn how the demand for better, faster, more reliable storage is growing. Hear how radar, sonar, lidar, and elaborate/elegant in-car HD camera systems will be part of sophisticated infotainment systems. Get inside information from leading autonomous system architecture designers of tomorrow's cars. Find out about the wide array of tailored flash memory solutions - NVMe solid state drives, Universal Flash Storage, and other NAND-based in-car storage solutions you will have to produce to be competitive. Get Your Storage on The Highways, Not in the Ditch Until now no one bragged about how much storage their car had, how fast off the line it was, and how much safe mileage it would provide. No one cared! Now storage is sexy, worth talking about. Instead of focusing on better headlights, better brakes, better entertainment systems, or more horsepower, people want to know if the storage is big enough, rugged enough, and safe enough for them. If 80 percent of the data systems accumulate will stay in the car, learn what it takes to have your storage designed in because it is fast, accurate, safe, secure, and life-saving. Learn first hand what it takes to get your storage solutions in the car and on the road.
About the Organizer/Moderator:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Allan McLennan is a Technologist/Analyst of the US based PADEM Media Group, one of the world’s recognized voices* in the advancement of IP (web/broadband/mobile) based television/OTT/VOD, video streaming and AI/ML engagement through connected devices. Allan is an established IP market technology executive in next generation digital media innovations/networks, consumer products and market capitalization deployments worldwide. His current work with global corporations and innovators addresses the deployments and acquisitions across multi-device IP networks, OTT/TV/VOD network programming and multi-platform video distribution. He actively participates in the advancement of data analytics, advanced advertising (ACR, RTB, Programmatic APIs) and the overall revision of the entertainment/media multi-platform video consumption models being explored today. He has participated in the creation/innovation, packaged and/or sold multiple new offerings throughout the world in 17 countries with close to four billion households as both a corporate executive and innovator. Allan has held five patents in targeted advertising and worked with corporations such as Ericsson, Siemens, Microsoft, TIVO, COMCAST, APPLE, Universal, Disney and more involving the advancement of IP/digital media distribution. Additionally, he was the founding AMI divisional president of the US publicly traded entertainment data analytics corporation – RENTRAK (NASDAQ: RENT), serving 100% of the studio and network marketplace.

Tuesday, August 7th
3:40-6:00 PM
ENST-102-1: Enterprise Storage Design (Enterprise Storage Track Track)
Organizer + Chairperson: KRS Murthy, CEO, I Cubed

Paper Presenters:
Raising QLC Reliability in All-Flash Arrays
Jeff Yang, Principal Engineer, Silicon Motion

Using Flash Storage to Obtain Real-Time Insight from a Data Lake
Sanhita Sarkar, Global Director, Analytics Software Development, Western Digital

Using Non-Volatile Memory for Computation-in-Memory
WeiTi Liu, President, LucidPort Technology

New Flash Technologies Can Meet Real-Time Needs
Brian Bulkowski, CT0/Co-Founder, Aerospike

Blockchain: Trusted Transactions Lead to Enormous Storage Needs
W David Schwaderer, Principal, Smart Creatives

Off Module Power Loss Protection: Cost efficiencies for enterprise systems
Rob Sykes, Sr Distinguished Engineer, Toshiba

Gen-Z: High-Performance Interconnect for the Data-Centric Future
Kurtis Bowman, President, Gen Z Consortium

Session Description:
Enterprise storage today must adapt to new requirements in the data center. Although cloud computing, analytics, deep learning, and big data have received the most attention recently, server and desktop virtualization, data tiering, efficient architectures, and implementation of data policies still must be further addressed. As the number of applications and users keeps increasing, the need for rapid, predictable, and intelligent access to data becomes more important. Solid state storage is a key technology in meeting higher demand and providing faster access to data at reasonable cost. However, managers must understand which flash technology to adopt and how to make price/performance tradeoffs. New physical architectures, new technologies, and new approaches to long-existing issues such as caching and distributed systems must all be leveraged to optimize enterprise storage and its solutions.
About the Organizer/Moderator:
KRS Murthy is an experienced venture capitalist, serial entrepreneur and corporate strategist. He is currently focused on mergers and acquisitions, corporate governance, and competitive strategy. He has developed national level technology and industry strategies in multiple key areas. He has led many companies at many different stages and has grown companies to sales of over $500 million. He is a popular speaker at conferences around the world and a leader in many technical societies, including IEEE Nanotechnology Council, IEEE Engineering Management Society, IEEE Computer Society, Silicon Valley Engineering Council, and IEEE Standards Board. Murthy also has experience as a USA Country Manager for AT&T and AT&T Bell Labs and as a professor of computer engineering at California State University, Pomona & Fullerton. He has received a Distinguished Service Award from the IEEE Engineering Management Society and a Distinguished Achievement Award from the President of India.

Tuesday, August 7th
3:40-4:45 PM
MCRN-102A-1: QLC Is the Best Way to Replace Enterprise HDDs (Micron Track)
Session Sponsor: Micron
Chairperson: Steve Hanna, Sr. Product Manager, Enterprise SSDs, Micron

Organizer + Speaker: Doug Rollins, Principal Technical Marketing Engineer, Enterprise SSDs, Micron

Paper Presenters:
Session Description:
An issue with replacing enterprise HDDs with SSDs is that, at a drive level, 7200 RPM HDDs still have a lower cost/bit. QLC flash helps lower that cost, easing the problem, as well as reducing the total system cost. However, current QLC SSDs have much shorter lifetimes than TLC. Testing of first-generation QLC drives shows that designers and users alike must look for the best use cases and workloads that are a good fit for QLC SSD technology. Likely candidates are low write-rate nearline applications, such as real-time analytics, AI, machine learning, Hadoop, NoSQL databases, content delivery, decision support systems, and scale-out active archives and block stores. This session will cover Micron test data on QLC SSDs over a variety of these workloads
About the Organizer/Moderator:
Steve Hanna is Sr Product Marketing Manager, Enterprise SSDs at Micron. He works on Micron’s entire enterprise SSD product portfolio, including SATA, SAS, and NVMe drives. He handles product launches (including the world’s first QLC SSD), market and customer intelligence, customer development, and training/enables for partners. He has been with Micron for over 6 years and was previously a Content Marketing Manager and Content Author. He studied innovation and entrepreneurship at Stanford and has authored over 50 thought leadership pieces related to server memory and SSDs. He earned a BA in English and Spanish from the University of Idaho.

Doug Rollins is a Principal Technical Marketing Engineer for Storage in Micron’s Enterprise SSD Products Group. He focuses on systems and system-level performance and performance measurement with the idea of creating competitive analysis. He is well-known as a blogger, conference participant, instructor, and seminar and class leader. He is active in standards activities, particularly with the Storage Networking Industry Association (SNIA). He is the former co-chair of the SSSI Technical Working Group and also participates in the I/O and Trace Tools Analysis, Marketing and Technical Development, Total Cost of Ownership, and Data Protection and Capacity Optimization groups. He was instrumental in the early development and validation of SNIA’s SSD Performance Test Specification. Before joining Micron, Mr. Rollins spent 17 years working in server system, network appliance, and storage platform/data protection design and manufacturing, and solid state storage. He is the named inventor in 13 US patents and has been recognized by both SNIA and Intel for outstanding technical achievement. He has written and published several papers and taught hands-on lab activities on SSD performance measurement. Mr. Rollins earned his BA in mathematics from Humboldt State University (California).

Tuesday, August 7th
3:40-6:00 PM
NVME-102-1: NVMe Management Interface, Drivers and Software / NVMe-oF Transport (NVMe Track Track)
Session Sponsor: NVM Express
Chair, 1st Part: Uma Parepalli, Sr Manager, Marvell

Organizer + Chair, 2nd Part: Brandon Hoff, Software Architect, Broadcom

Panel Members:
Speaker, 2nd Part: Praveen Midha, Director Product Management/Strategic Marketing, Marvell

Speaker, 1st Part: Fazil Osman, Distinguished Engineer, Broadcom

Speaker, 2nd Part: Fazil Osman, Distinguished Engineer, Broadcom

Speaker, 2nd Part: J Metz, Office of the CTO/Board Member, Cisco Systems

Speaker, 1st Part: James Harris, Principal Software Engineer, Intel

Speaker, 1st Part: Lee Prewitt, Principal Program Manager, Microsoft

Speaker, 1st Part: Dave Mintern, Principal Engineer, Intel

Speaker, 1st Part: Suds Jain, Product Manager, VMware

Speaker, 2nd Part: Curt Beckmann, Product Architect Nvme Over Fibre Channel, Brocade

Session Description:
NVMe, NVMe-MI, and NVMe-oF now offer the basic ecosystem developers need to create complex storage systems including faster and more resilient drivers, an extensive management interface, and optimized, highly tested tools for developing user space software. Part 1: NVMe Management Interface, Drivers and Software: This session provides the insights in to the latest updates on NVMe Management Interface (MI), Drivers and software. The NVMe Management Interface (NVMe-MI) is programming interface that allows out-of-band management of an NVMe Storage Device Field Replaceable Unit (FRU). This session will provide an overview of NVMe-MI and how it is being extended in the next revision of the specification to cover in-band management, enclosure management, and managing more complex types of devices. This session will talk about what is new in the drivers available for UEFI, Windows, Linux and VMWare platforms. In addition, the Intel Storage Performance Development Kit (SPDK) provides an open source set of tools and libraries hosted on GitHub that helps developers create high-performance, scalable storage applications for multicore CPUs and high-speed storage devices. Part 2: NVMe over Fabrics (NVMe-oF) the Transports: NVMe-oF extends NVMe to networked systems including clusters, hyperconverged sites, and distributed computers. It allows systems to share flash storage, increasing utilization and scalability and making far more flash available to applications running on any available CPU. Implementations have advanced rapidly, moving from prototypes to shipping solutions in less than a year. As customers scale their NVMe deployments from a handful of drives to thousands, NVMe-oF will expand the market with many new storage solutions. NVMe-oF is transport agnostic, and can work with any popular high-popular high-speed transport, such as NVMe over RDMA, NVMe over Fibre Channel, and NVMe over TCP.
About the Organizer/Moderator:
Uma Parepalli is a Sr Manager for Servers and Storage Platform Firmware at Western Digital, where he focuses on cloud and data center servers and storage, embedded systems storage, hardware-firmware codesign, architecture, and management. He has over 25 years of semiconductor industry experience in servers, storage, embedded, aerospace, and consumer electronics applications. Uma previously worked for Viavi Solutions, SK hynix, EMC, LSI, Dell, and Intel in roles ranging from Senior Architect/Principal Engineer to Director and VP of Engineering, and has led global engineering teams. He has also worked on industry standards specification development for over 20 years. He is a Computer Engineering graduate of the University of Mysore, India. He is a frequent participant at Flash Memory Summit as an organizer, chairperson, presenter, and panelist, and is a member of the Summit’s Conference Advisory Board.

Brandon Hoff is Distinguished Software Architect at Broadcom, where he focuses on new product strategy, including product development interlock, business planning, and sales strategy development for growth initiatives. He has also worked on innovation initiatives, end user strategies, technology and strategy solutions for Web giants, and product portfolio leadership. He has been an active participant in NVM Express, the sponsoring organization for NVMe standards, and has also been IBTA Marketing Work Group Co-Chair. He is a frequent participant at industry events, including NVM Express meetings, SNIA conferences, and Ethernet Alliance events. He has over 25 years of industry experience, including a stint as Chief Strategy Officer/Chief Marketing Officer at CipherOptics, where he was responsible for managing all aspects of marketing, corporate strategy, product management, field and corporate marketing, marketing communications, public relations, branding, and lead generation. He holds an MBA from the University of Colorado (Boulder) and a BSEE from Colorado State University.

Tuesday, August 7th
3:40-6:05 PM
PMEM-102-1: Persistent Memory Hardware (Persistent Memory Track Track)
Session Sponsor: SNIA, JEDEC, and OFA
Organizer: Jim Pappas, Director, Initiative Marketing, Intel Server Platforms Group

Organizer + Chairperson: Jonathan Hinkle, Principal Researcher, Lenovo

Paper Presenters:
Overview of Persistent Memory Hardware and JEDEC NVDIMM Standards
Bill Gervasi, Principal Systems Architect, Nantero

Key Considerations for Persistent Memory and NVDIMMs
Frank Ross, Sr. Memory Systems Architect, Micron

Persistent Memory DIMMs
Mark Henderson, Memory and Storage Product Marketing Manager, Intel

NVDIMM-N Capabilities and Enabled System Benefits
Bob Frey, Director Memory and Systems Engineering, SMART Modular Technologies

NVDIMM-P
Thomas Choi, Senior Engineer, DRAM Product Planning, SK hynix

Design of PRAM-based Persistent NVDIMM Controllers to Prepare the Data Age
Myoungsoo Jung, Professor, School of Integrated Technology, Yonsei University

Session Description:
Persistent memory - fast, byte-addressable memory that retains data - requires new hardware implementations. NVDIMM is currently the most popular and most widely used approach. The JEDEC standard NVDIMM-N is commonly available, but uses its flash memory only for backup in the event of power loss. The upcoming persistent NVDIMM will allow direct access to the flash memory for caching purposes. NVDIMM-N is widely supported in operating systems (such as Linux and Windows Server), hypervisors (such as VMware), and other software. The obvious advantage is that NVDIMM uses standard DRAM memory modules and so requires few system modifications. Future implementations will surely use faster, more capable non-volatile technologies such as 3D XPoint™ and MRAM. However, they will require more system changes so more design work, more extensive changes in system software, and more standards efforts will be necessary to make them generally viable.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Jonathan Hinkle is Director, Systems Platform Technologist at Lenovo, where he drives new server architecture and technologies in their Enterprise Product Group. Previously, Jonathan was Storage and Memory Systems Architect at Viking Technology, where he developed next-generation memory and storage products and technologies. Before Viking, Mr. Hinkle worked at IBM where he developed server systems ranging from high-end enterprise boxes to blade servers. He is the chairman of the JC45.1 RDIMM committee and the Hybrid Memory Module task group in the JEDEC standards organization. He also invented and drove first development of the VLP DIMM and the SATADIMM SSD. He is a senior member of the IEEE and has a Bachelors and Masters degree in Computer Engineering from North Carolina State University. He is a member of the Program Executive Committee for Flash Memory Summit.

Coming soon..

Coming soon..

Coming soon..

Speaker Bio: Bill Gervasi, Principal Systems Architect at Nantero, is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.

Speaker Bio: Dr. Myoungsoo Jung is an Assistant Professor at Yonsei University (Korea). He has many years of industry experience, holds several industrial U.S. patents related to multi-channel SSDs, and has published forty technical papers on SSD flash firmware and kernel-level file systems. His work won a best paper nomination from the IEEE/ACM Internal Conference for High Performance Computing, Networking, Storage and Analysis 2013 (SC'13). He received core grant awards from National Science Foundation (NSF) and the Department of Energy (DOE), as well as the Lawrence Berkeley National Laboratory (LBNL) Award of Excellence. His current research interests include coprocessor architecture (e.g., MIC/GPU), FPGA-based accelerators, advanced computer architecture, and operating systems that take advantage of emerging non-volatile memory and solid state drive technologies. Dr. Jung earned his Ph.D. in Computer Science from Pennsylvania State University and his M.S. in Computer Science from Georgia Institute of Technology. He also earned an M.S. in Embedded Systems from Korea University in Seoul.

Tuesday, August 7th
3:40-5:45 PM
SSDS-102-1: Enterprise SSDs (SSDs Track Track)
Co-Organizer + Co-Chair: Tom Friend, Director of Industry Standards, Independent Consultant

Organizer + Chairperson: Mike Gluck, VP/CTO, Sanity Solutions

Paper Presenters:
Low-Power Design of SSDs
Daniel Sun, ,

Dual-Mode SSD Architecture for Next-Generation Hyperscale Data Centers
Ping Zhou, Staff Engineer, Alibaba

Making the Right SSD Choice for Big Data, Fast Data Workloads
Walter Hinton, CMO, Pavilion Data Systems

Intelligent Hybrid Flash Management
Jerome Gaysse, Managing Director, Silinnov Consulting

Optimizing SSDs for Multiple Tenancy Use
Liam Parker, Senior Technologist, SSD Systems Engineering, Western Digital

Reducing Performance Variations Caused by Garbage Collection in Enterprise SSDs
Ken Qing Yang, Professor and CSO, University of Rhode Island and Dapu Microelectronics Ltd CO

Session Description:
Enterprise SSDs are achieving higher capacities and higher performance and are therefore used in more applications, displacing HDDs in a wide variety of environments. Storage system designers must make new tradeoffs among performance, data retention and endurance for SSDs to account for their special characteristics. Hyperscale data centers also have special requirements that must be met, most likely with architectures specifically intended for these fast-growing environments.
About the Organizer/Moderator:
Tom Friend is Director of Industry Standards at SK hynix memory systems, where he manages industry relationships and participates in standard groups including INCITS T10 and T13, NVMe, PCI-SIG, TCG, SNIA, and JEDEC. Before joining SK hynix, he was Director of Industry Standards at Toshiba and OCZ. He has also worked at WDC, HP, Microsoft and a number of startups during his lengthy career in the technology industry. Besides his activity in standards groups, he publishes articles, gives conference presentations (including past Flash Memory Summits), and teaches courses in NVMe and standards interactions.

Mike Gluck is Vice President and CTO at Sanity Solutions. Mike has over 35 years of experience in the computer and data storage industry. His focus is assisting clients craft innovative data management solutions that provide distinctive value and competitive advantages for their strategic business goals. Internally, he analyzes key IT trends, paradigm shifts and disruptive technologies, searching for leading-edge vendors and products that can provide differentiation and competitive advantages for clients.

Tuesday, August 7th
4:55-6:05 PM
BMKT-102B-1: What Do the 800-Pound Gorilla Customers Want in Flash Storage? (Business/Marketing Track Track)
Organizer: Jay Kramer, President, Network Storage Advisors

Chairperson: Krista Macomber, Director of Market Intelligence, TechTarget

Panel Members:
Panelist: Iqbal Bhalwani, VP of Global Sales, ScaleFlux

Panelist: Rakesh Radhakrishnan, Director, Product Management, VMware

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Alan Armstrong, CEO, CNEX Labs

Panelist: Shane Kavanagh, Engineering Technologist, Dell EMC

Session Description:
Hyperscale Cloud Service Providers (CSPs) are growing and On-Premise data centers are shrinking. What are the storage requirements of the cloud providers? Are their needs different? What are the mega-cloud providers buying and why? Who are the winners and who are the losers? What do vendors designing products and IT organizations buying products need to know as we look at the cloud storage marketplace.
About the Organizer/Moderator:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Krista Macomber is Director of Market Intelligence at TechTarget, where she provides actionable analysis and insight on major trends disrupting today’s technology marketplace. She meshes her market knowledge with qualified pre- and post-purchase influence data and marketing campaign performance to help TechTarget clients achieve their marketing goals. Before joining TechTarget, she was a competitive and industry analyst at Technology Business Research, where she managed and acted as the subject matter expert for the IT infrastructure practice. She frequently authors content and hosts webinars and industry sessions covering topics such as flash storage, hyperconverged infrastructure and private and hybrid cloud. She earned a BA in journalism from the University of New Hampshire.

Tuesday, August 7th
4:55-6:05 PM
INVT-102B-1: IP-Based Development Platform for NVMe-Based Products (NVMe Track Track)
Chairperson: Rakesh Cheerla, Solution Planner, Intel

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
IP-Based Development Platform for NVMe-Based Products
Mickael Guyard, Sales/Marketing Manager, IP-Maker

Session Description:
NVM Express (NVMe) is an ideal protocol to use in attaching flash memories to a CPU, and is today in full deployment in data centers utilizing PCIe NVMe SSDs. On the other hand, server system architectures are evolving rapidly, moving from a CPU-centric to a data-centric and heterogeneous computing architecture. NVMe is still the best way to manage data transfers between computing accelerators and non-volatile memory (NVM). This talk presents the implementation of the NVMe protocol as full hardware IPs for an FPGA-based development platform. Both the host and device sides are implemented in RTL, leading to ultra-low latency data access, making it ready to support persistent memories. This IP set is easy to implement and delivers a fast access between compute and storage. The development platform is an excellent tool to design new kinds of NVMe-based products such as HBAs, in-storage processing, and computing accelerators.
About the Organizer/Moderator:
Rakesh is a Senior Product Manager for Storage Solutions at Xilinx, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Tuesday, August 7th
4:55-6:05 PM
NEWM-102B-1: Annual Update on Emerging Memory Technologies (New Memory Technologies Track Track)
Chairperson: Satoru Araki, Senior Director, Program/Product Management, Spin Memory

Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:
Session Description:
Emerging memories have been forever banished to tiny niche markets subject to their impossibly insurmountable DRAM and NAND overlords? or have they? Each year, Flash Memory Summit offers predictions about how new memory technologies are near the horizon ? and why they will disrupt the memory business and system architectures. Will emerging memories perpetually be 3 years to production or is the dawning of something new finally here? This session will offer a practical walkthrough of what we?ve learned about emerging memories over the past decade, the barriers that threaten their emergence, and what technical, manufacturing, ecosystem, and market conditions need to exist for them to be truly successful.
About the Organizer/Moderator:
A technology management executive with over 20 years’ experience, Satoru Araki is currently Sr Dir, Product/Program Management at Spin Transfer Technologies. He was previously a Dir, Program Management and Platform Development at HGST where he served as technology project/program director for several technical projects and products. He has previously been a Dir, Advanced Wafer Engineering and Advanced Technology at HGST. He also has prior experience with Read-Rite and TDK as a Sr. Director. He holds a BS, MS, and PhD in Applied Physics from Waseda University, Japan and an MBA from San Jose State University.

Leah Schoeb currently works at Rubrik as a Master Technologist and brings expertise ranging from cloud infrastructure and virtualization to system and data infrastructure performance. Her latest work with infrastructure optimization and solid state technology. She draws over many years of experience in the computer industry helping systems companies with performance engineering and optimization, market positioning, benchmark evidence creation, and guiding industry standards development for system, virtualized, containerized, and data solutions. Leah has served in several leadership roles for performance architecture for companies, such as, Turbonomic, VMware, Sun Microsystems, Dell, Intel, and Amdahl.

Tuesday, August 7th
4:55-6:00 PM
MCRN-102B-1: Meeting the Storage Needs of 5G Networks (Micron Track)
Session Sponsor: Micron
Organizer + Speaker: Mario Endo, Sr. Regional Marketing Manager, Mobile Business Unit, Micron

Panel Members:
Organizer + Speaker: Mario Endo, Sr. Regional Marketing Manager, Mobile Business Unit, Micron

Session Description:
The 5th generation cellular network (5G) is set to launch in 2019 which can deliver peak data rates of 10Gbps over a wider frequency bandwidth compared to 4G. Once 5G proliferates the market, more people will have access to faster data which enables users to conveniently upload and download larger content such as 4k or higher resolution videos and games. In order to keep up with these usage patterns, mobile storage densities will continue to increase to support storing more content and transition to protocols such as UFS3.0 that support faster data transfer rates that keep up with 5G speeds.
About the Organizer/Moderator:
Mario has been with Micron since 2017, prior to that he held various engineering and management positions at Texas Instruments. He has a Masters in Mechanical Engineering from Santa Clara University ,and a BSME from USC

Tuesday, August 7th
4:55-6:05 PM
SECU-102B-1: Encryption for Data Protection (Security Track Track)
Organizer + Chairperson: Paul Suhler, Storage Architect, Micron Technology

Organizer + Speaker: Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Organizer + Speaker: Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Paper Presenters:
Making Your Data Secure Today with the New TCG Ruby Standard
Drew Tipton, Technical Product Manager, Toshiba America

What Industry Standard Self-Encrypting Storage is, and why it is Essential
Bob Thibadeau, Chairman/CEO, Drive Trust Alliance

Session Description:
Ransomware is malicious software that threatens to publish the victim?s data or block access to it unless the victim pays a ransom. The problem of ransomware began around 2012 and has grown rapidly (and internationally). The sophistication of the attacks has grown rapidly, and the difficulty of stopping them or tracing what happens to payments has also increased greatly. The largest threat appears to be to medium-sized installations that depend on their data, lack much sophistication in methods or personnel, and are capable of paying large ransoms. Examples include school districts, hospitals, professional firms, and small/medium-size businesses. As flash memory becomes more widespread, it will surely become still another method for attack. As a new technology, it is often left unprotected and its vulnerabilities are neither well-known nor well-understood. As more data migrates to flash, the problem will only get worse. Flash manufacturers at all levels will need to understand this threat and what they can do to combat it.
About the Organizer/Moderator:
Paul Suhler is a storage architect in SSD engineering at Micron Technology, where he is responsible for NVMe interfaces and for educating internal teams as well as customers. He is Micron's primary representative to the NVMe Technical Work Group to which he has contributed many proposals. He is also active in the SFF Technical Work Group, having chaired working groups on the U.3 specification, Ethernet drive connectors, and Ethernet speed negotiation. He has worked in the data storage industry for over twenty years at companies including HGST, Quantum, Seagate, and Adaptec. He has also been a member of the research faculty at the University of Southern California. He received the INCITS Technical Excellence Award, and is a Senior Member of IEEE. He holds a PhD and BS in computer engineering from the University of Texas at Austin, and an MS in computer engineering from the University of California, Berkeley. He is the author of papers and journal articles on parallel computing.

Bob Thibadeau is the chairman and CEO of the Drive Trust Alliance, and is a contributor to the Trusted Computing Group's Storage Work Group.

Bob Thibadeau is Chairman and CEO of the Drive Trust Alliance (DTA). Previously he was Chief Technologist for Seagate Technology and the originator of the Trusted Computing Group’s Self-Encrypting Drive (SED) Technologies. Currently the DTA has developed “Auto Erase” key management technology for SEDs in Automotive and other system IoT situations where SEDs are physically distributed in the IoT system (drivetrust.com/auto-erase). Previously, he headed projects in Robotics at Carnegie Mellon University for the major Automotive OEMs which resulted in nearly universal adoption of his inventions.

Wednesday, August 8th
Wednesday, August 8th
8:30-9:35 AM
BMKT-201A-1: Annual Update on Flash Arrays (Business/Marketing Track Track)
Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Paper Presenters:
Session Description:
"All-flash arrays are dominating primary storage spend in the enterprise, driving over 80% of that revenue in 2017," reports IDC Research Vice-President Eric Burgener. All-flash arrays (AFAs) are now a multibillion dollar market, with Pure Storage, HPE, NetApp, Dell EMC, and IBM leading the way. DCIG offers an intensive examination of the AFA market including discussions of current product architectures, with an emphasis on each one’s major features and applications. DCIG also ranks each array based on different use cases with regard to such highly desirable features as capacity optimization, future-proof refreshes, and NVMe utilization. The DCIG analysis helps designers and users alike determine which arrays are best for particular use cases, make competitive comparisons, and identify market opportunities.
About the Organizer/Moderator:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Wednesday, August 8th
8:30-9:35 AM
INVT-201A-1: Innovation, Determination and the First Days of Flash (History Track Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Paper Presenters:
Innovation, Determination and the First Days of Flash
Dov Moran, Managing Partner, Grove Ventures

Session Description:
This talk will be given by Dov Moran, one of the recipients of this year's Flash Memory Summit Lifetime Achievement Award. This will be a light-hearted talk about the early days of flash memory, and how forming M-Systems in Israel early in 1989 led to many inventions and products that had a huge impact on the nonvolatile memory industry Although Dov and his partner Aryeh Mergi were already creating early SSDs based on EEPROMs and battery-backed SRAM, the inspiration to form the company came from Intel's announcement of its first NOR flash memory chips in late 1988. The story continues with the TrueFFS Flash File System, which was adopted by the PCMCIA PC Card committee as its Flash Translation Layer software. In 1993, the DiskOnChip device was created for use as an embedded SSD, and this product was successful for over 10 years - first as a NOR-based device, and then as a NAND-based device. In 1998, the concept of a USB-based flash device was born as DiskOnKey, and this led to a USB Flash Device that was co-announced with IBM at COMDEX in 2000. A mobile version of the DiskOnChip was developed, and Nokia shipped the first embedded SSD for a cellphone based on this device in 2002, Many other cellphone companies ended up using the device as well, and NAND-based SSDs have been an essential feature of cellphones since that time. A 4-year design effort led to M-Systems' introduction of a 4 bit/cell Flash device in 2006, and this product received the Most Innovative Flash Product award at the first Flash Memory Summit in 2006. SanDisk acquired the company later that year, and its Israeli R&D center continues as part of Western Digital (which bought SanDisk in 2016). The interesting stories behind this company's history will make for an enjoyable presentation.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Wednesday, August 8th
8:30-9:35 AM
MRES-201A-1: Market Research Panel (Market Research Track Track)
Chairperson: John Rotchford, Managing Director, SASI

Panel Members:
Panelist: Thomas Coughlin, President, Coughlin Associates

Panelist: Camberley Bates, Managing Director/Analyst, Evaluator Group

Speaker: Jim Handy, Director/Chief Analyst, Objective Analysis

Panelist: Jeff Janukowicz, VP, IDC

Panelist: Chris DePuy, Research Analyst/Co-Founder, 650 Group

Session Description:
The flash memory market has recently seen explosive growth and rising demand, attracting many startups and creating exciting acquisitions and IPOs. On the technology front, NAND flash products are achieving lower cost through higher densities and by cascading from SLC to MLC to TLC to 3D. New products are being targeted for the enterprise ranging from embedded flash on servers to improve their I/O performance a thousand-fold to networked SSDs targeting lower costs. A new generation of smart controllers significantly increases performance using hierarchical flash caching, improves availability, and enhances endurance through deploying ECC, wear-leveling, overprovisioning, and garbage collection techniques together with auto-configuration and workload aware auto-tiering placement. Such controllers help make SSDs suitable for mission critical enterprise applications. Attend this key session on the state of the flash Industry. It will cover market forecasts, shares, technology progress, competition, go-to-market pricing structures, and possible mergers and acquisitions. Ask questions of analysts to crystallize your understanding of markets and potentially competitive products. Areas of interest include: Forecast of flash growth in server and storage markets; Market segments where flash will displace other technologies; New configurations such as all-flash arrays and flash in DIMM (NVDIMM); Price trends and their impact on markets; New interfaces such as NVMe and NVMe-oF; Effects of software-defined storage and hyperconvergence; Whether future computer systems will incorporate flash directly at all levels; The role storage will play in the transition from on-premise data centers to clouds; The status of emerging technologies such as MRAM, RRAM, and 3D XPoint; and Acquisition candidates
About the Organizer/Moderator:
John Rotchford is Managing Director and Founder at SASI, a boutique mergers and acquisitions (M&A) advisory firm focused on serving investors and entrepreneurs in the IT industry. SASI represents leading venture backed private companies that are exploring strategic M&A options. John is a 20-year technology industry veteran with a unique blend of investment banking, strategy consulting, corporate development, and start-up experience. He was previously a Vice-President at Silicon Valley Bank, where he co-managed the information technology practice, and Director Corporate Development at Iomega, where he was responsible for strategic planning, M&A, and new investment activities. He earned a BS in Accounting and Finance from Babson College.

Wednesday, August 8th
8:30-9:35 AM
NEWM-201A-1: 3D XPoint: Current Implementations and Future Trends (New Memory Technologies Track Track)
Organizer + Chairperson: Milind Weling, Sr VP Programs and Operations, Intermolecular

Paper Presenters:
3D Xpoint: Applications, Performance, and Revenue Forecast through 2023.
Mark Webb, President, MKW Ventures

Process Challenges For 1S-1R Crossbar Type Memory
Mahendra Pakala, Sr Director, Applied Materials

3D XPoint: Process and Architecture Views
Jeongdong Choe, Consulting Engineer, TechInsights

Session Description:
The speculation surrounding Intel/Micron 3D XPoint technology has been huge, ever since its introduction in 2015. What is the reality? Where is the technology today and what applications are already using it? What are the effects of the relatively high prices (five times that of flash) that have now been suggested? Where will the technology be in 2022 and what steps will occur along the way? Obviously, this is long-term speculation with no guarantees. However, a look at the far horizon can provide guidance as to what developers are thinking and what initial users and observers now feel is possible.
About the Organizer/Moderator:
Milind Weling is Senior Vice President of Programs and Operations at Intermolecular. He is responsible for IMI’s high throughput experimentation technology and manages the technical execution of customer programs for the discovery of advanced materials and leading edge device optimization. Milind is a senior engineering and management professional with extensive experience in advanced memory and logic semiconductor technology development, DFM and design-process interactions, new product introduction, and foundry management. His previous senior management roles include DFM products engineering at Cadence Design Systems and high performance CMOS technology development at Sun Microsystems, Philips Semiconductors and VLSI Technology. Milind holds a B. Tech degree in Electrical Engineering from the Indian Institute of Technology, Bombay, and a MS degree in Electrical Engineering from the University of Hawaii. He holds 50+ patents and has co-authored over 70 technical papers, primarily focused on process technology, reliability and integration.

Wednesday, August 8th
8:30-10:50 AM
CTRL-201-1: Controllers and Flash Technology, Part 1 - Hardware and Algorithms (Controllers Track Track)
Chairperson: David Declercq, CTO, CodeLucida

Organizer + Instructor: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Presenters:
Novel Error Recovery Architecture based on Machine Learning
Cloud Zeng, Sr Engineer, Lite-On Storage

An SSD Controller for 3D NAND with Compression, LDPC Coding and Media Management
Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Designing Enterprise Controllers with QLC 3D NAND
Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Beyond AWGN, Soft Decoding performance Optimization for Flash Channels
Peter Graumann, Technical Director, End Point Solution Business Unit, Microsemi

A 4KB-codeword LDPC ECC engine with advanced DSPs for enterprise SSD
Wei Lin, System Architect, Phison Electronics

Horizontal Error Detection & Vertical LDPC ECC for Reliable 3D-TLC NAND Flash
Shun Suzuki, Student, Chuo University

Session Description:
This session provides details on improving the endurance, retention, and performance of 2D and 3D NAND flash devices. Important strategies and signal processing that controllers can employ to further improve key reliability measures are revealed. The forum also presents novel implementations for reducing power usage and solving problems caused by write amplification. Learn about new technology developments and have time for questions and answers with top industry experts.
About the Organizer/Moderator:
David Declercq is the co-founder and CTO of Codelucida Inc. He was previously full professor at the ENSEA in Cergy-Pontoise, France, from 2001 to 2017. He is a senior member of the IEEE, and a widely renowned researcher in the area of LDPC code and decoder design. He published more than 150 papers in the area, and holds 8 patents. Several of his contributions towards LDPC code and decoder design have been employed by industry as well as adopted in several standards. He is especially recognized for his pioneering works on non-binary LDPC code and decoder designs.

Erich Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Wednesday, August 8th
8:30-10:50 AM
ENAP-201-1: Enterprise Applications, Part 2 (Enterprise Applications Track Track)
Organizer + Chairperson: Tom Burniece, President, Burniece Consulting Services

Paper Presenters:
Integrating Scale-out Flash Cache into Production Workflows
Kurt Kuckein, Director or Marketing, DDN Storage

Optimizing storage for planetary data with All flash arrays
Bob Fine, Director Product Marketing, Dell

Thomas Stein, , Washington University
SSD and Container Native Storage for High-Performance Database
Earle Philhower, Sr Technical Marketing Manager, Western Digital

Flash Continues to Drive Innovation For Customers
Eric Herzog, CMO VP Worldwide Storage Channels, IBM

MacStadium Chooses Pure Storage to Improve Infrastructure
Chadd Kenney, VP/CTO, Pure Storage

Global Response Enlists Pure Storage to Support Growth and Boost Efficiency
Chadd Kenney, VP/CTO, Pure Storage

Scaling IP Video CDN with All-Flash
Mike Gluck, VP/CTO, Sanity Solutions

Real world results and observation from implementing virtualized environments
Bob Fine, Director Product Marketing, Dell

Greg Patchev, , Gerrie Electric Wholesale

Session Description:
Flash memory has enabled new storage system and computing architectures which can handle many enterprise applications far more efficiently than is possible with hard drives. This session will feature actual case studies by innovative storage companies, including descriptions of the problem, approach, and results. Customers will co-present with some speakers.
About the Organizer/Moderator:
Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Wednesday, August 8th
8:30-10:50 AM
NVME-201-1: NVMe-oF Enterprise Arrays/Appliances (NVMe Track Track)
Session Sponsor: NVM Express
Organizer + Chairperson: Brandon Hoff, Software Architect, Broadcom

Chairperson: Jeremy Werner, VP SSD Marketing & Product Planning, Toshiba Memory

Panel Members:
Speaker, 1st Part: Michael Peppers, Technical Marketing Engineer, NetApp

Speaker, 2nd Part: Nishant Lodha, Sr Technical Marketing Manager, Marvell

Speaker, 2nd Part: Lior Gal, CEO, Excelero

Speaker, 1st Part: Clod Barrera, Distinguished Engineer/Chief Technical Strategist, IBM

Speaker, 2nd Part: Manoj Wadekar, Storage Architect, Facebook

Speaker, 2nd Part: Kamal Hyder, Director Product Management Cloud Software, Toshiba Japan

Session Description:
Part 1: NVMe-oF Enterprise Arrays: NVMe-oF and NVMe is improving the performance of classic storage arrays, a multi-billion dollar market. This session will cover NVMe and NVMe-oF for Enterprise All Flash Arrays (AFAs) including SPDK with NVMe-oF. Part 2: NVMe-oF Appliances: These solutions are different than Enterprise Arrays because the targets being more like JBOFs than Enterprise AFAs. We will discuss solutions that deliver high-performance and low-latency NVMe storage to automated orchestration-managed clouds.
About the Organizer/Moderator:
Brandon Hoff is a Distinguished Software Architect at Broadcom, where he focuses on new product strategy, including product development interlock, business planning, and sales strategy development for growth initiatives. He has also worked on innovation initiatives, end user strategies, technology and strategy solutions for Web giants, and product portfolio leadership. He has been an active participant in NVM Express, the sponsoring organization for NVMe standards, and has also been IBTA Marketing Work Group Co-Chair. He is a frequent participant at industry events, including NVM Express meetings, SNIA conferences, and Ethernet Alliance events. He has over 25 years of industry experience, including a stint as Chief Strategy Officer/Chief Marketing Officer at CipherOptics, where he was responsible for managing all aspects of marketing, corporate strategy, product management, field and corporate marketing, marketing communications, public relations, branding, and lead generation. He holds an MBA from the University of Colorado (Boulder) and a BSEE from Colorado State University.

Jeremy Werner is VP SSD Marketing/Product Planning at Toshiba Memory, where he focuses on products that advance enterprise transformation and provide new levels of performance. He is also a member of the Board of Directors of NVM Express®, the standards organization for NVMe. He was previously VP Sales/Marketing at Tidal Systems, a developer of flash controllers acquired by Micron. He has also held marketing management positions at Seagate, LSI, and SandForce. He holds 23 patents in storage technology He earned a BSEE at Cornell University (Ithaca, NY).

Wednesday, August 8th
8:30-10:50 AM
NVME-201-2: PCIe/NVMe Issues (NVMe Track Track)
Co-Organizer: Rakesh Cheerla, Solution Planner, Intel

Organizer + Chairperson: Deepankar Das, CTO, Sureline Systems

Paper Presenters:
Non-Disruptive Firmware Upgrades for Enterprise SSDs
Radjendirane Codandaramane, Sr. Manager, Applications Engineering, Microsemi

Implementing Hot Plug in NVMe Storage Systems
Wesley Yung, Principal Engineer, Applications, Microsemi

Bullet-Proofing PCIe in Enterprise Storage SoCs with RAS features
Michael Fernandez, Field Applications Engineer, PLDA

Ensuring Data Availability for NVMe-Based Storage
Jeff Plank, RAID Solution Architect, Microsemi

Accelerating Applications with Flexible NVMe SSD Design Optimization
Tao Zhong, CTO, NETINT Technologies

Session Description:
PCIe SSDs offer higher performance than ones based on disk interfaces, since they utilize the high-speed (and widely supported) PCIe bus. They have quickly become popular in a wide variety of enterprise applications, particularly in implementations utilizing the new NVMe standard. Of course, all the usual design problems occur ranging from connectors through power management, power consumption, configurability, and hardware/software tradeoffs. But with over 100 million enterprise PCIe ports already shipped, this is an approach enterprises find to be both reasonably priced and easily implemented. It can work in both client and data center applications.
About the Organizer/Moderator:
Rakesh is a Senior Product Manager for Storage Solutions at Xilinx, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Wednesday, August 8th
8:30-10:50 AM
PMEM-201-1: Persistent Memory Software and Applications (Persistent Memory Track Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Organizer: Jim Pappas, Director, Initiative Marketing, Intel Server Platforms Group

Co-Organizer + Co-Chair: Jeff Chang, VP Marketing, AgigA Tech

Co-Organizer + Co-Chair: Arthur Sainio, Director Product Marketing, SMART Modular Technologies

Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Paper Presenters:
The SNIA NVM Programming Model
Doug Voigt, Distinguished Technologist, HPE

NVDIMM: The savior of SSD endurance in CEPH
David Tseng, Supervisor Engineer, Bigtera

Performance Benefits of NVDIMMs in Enterprise Data Storage Platforms
Sreekanth Garigala, Senior Technologist, Western Digital

PM Applications Panel - 9:45 -10:50 am
Scott Miller, Technology Fellow, Engineering and Infrastructure, DreamWorks Animation

Jia Shi, , Oracle
Brian Bulkowski, , Aerospike

Session Description:
Putting it All Together – The Enablement, Adoption, and Application of Persistent Memory The ecosystem for persistent memory has come a long way with help from standards bodies, platform enablers, and many others. With continued advances in operating systems and open source libraries, today’s platforms allow software applications to leverage the benefits of persistent memory technology. The industry is witnessing a major change in computer architecture based on the availability of low latency persistent memory products and the resulting need to modify applications to treat memory as nonvolatile. Examples drawn from software-defined storage, enterprise data storage, cloud infrastructure, and other areas illustrate the deployment of persistent memory.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Jeff Chang is VP Sales/Marketing at AgigA Tech, a pioneer in NVDIMM technology. He is responsible for product strategy, definition, and rollout as well as customer and partner relationships. He has also focused on the promotion and evangelization of NVDIMM technology to the industry at-large through conference appearances, articles in the trade and technical press, webinars, and webcasts. Jeff is co-chair of the Persistent Memory and NVDIMM Special Interest Group (SIG) within SNIA/SSSI. Before joining AgigA Tech, he held executive management and marketing positions at Entropic Communications, Staccato Communications, and Cypress Semiconductor. Mr. Chang has built and managed successful product portfolios spanning multiple end user markets including personal computing, consumer electronics, mobile handsets, enterprise systems, and operator-class communication systems. He earned a BSEE from the University of Washington.

Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he leads efforts in new technologies such as NVDIMMs. He has been instrumental in making SMART a leader in embedded applications of solid state storage over the last 20 years. He has promoted NVDIMMs through conference appearances, articles in the trade and technical press, webinars and webcasts, and organization of a Persistent Memory and NVDIMM Special Interest Group within SNIA/SSSI (where he serves as co-chair). He has been a frequent organizer, speaker, and moderator at SNIA events, Flash Memory Summit, and the In-Memory Computing Summit. Arthur earned an MBA from San Francisco State University and an MS from Arizona State University.

Jonathan Hinkle is Director, Systems Platform Technologist at Lenovo, where he drives new server architecture and technologies in their Enterprise Product Group. Previously, Jonathan was Storage and Memory Systems Architect at Viking Technology, where he developed next-generation memory and storage products and technologies. Before Viking, Mr. Hinkle worked at IBM where he developed server systems ranging from high-end enterprise boxes to blade servers. He is the chairman of the JC45.1 RDIMM committee and the Hybrid Memory Module task group in the JEDEC standards organization. He also invented and drove first development of the VLP DIMM and the SATADIMM SSD. He is a senior member of the IEEE and has a Bachelors and Masters degree in Computer Engineering from North Carolina State University. He is a member of the Program Executive Committee for Flash Memory Summit.

Speaker Bio: Sreekanth Garigala is a Senior Technologist in Tegile, Western Digital DCS division. He is the primary designer of intelliRAID, a patent pending storage technology for Tegile High Performance Arrays. He has 15 years of experience in developing device drivers, volume manager, file systems, dedupe and replication.

Speaker Bio: David Tseng joined Bigtera in 2014 as software engineer, responsible for developing CEPH core and maintaining SCSI target services.David Tseng is a supervisor engineer at Bigtera, who has more than 7 years in SDS software, and an official Linux driver maintainer. Before Bigtera, he researched distributed storage systems in Academia Sinia. At Bigtera he currently focuses on CEPH core development, including performance and stability enhancement, new feature design and development. He holds an M.S.C.S.E. degree and was enrolled in as PhD student from Operating System Lab, National Sun Yat-Sen University, Taiwan. Mainly researches on distributed systems and developing linux drivers for some prototype HWs in university.

Speaker Bio: Doug Voigt is a Distinguished Technologist in HPE’s Storage Division. He is chair of the SNIA NVM Programming Model TWG and a member of the SNIA Technical Council. Doug has 40 years of development experience in disk drives, disk arrays, storage management and non-volatile memory. He holds CS and EE degrees from Cornell University and 38 US patents, primarily in virtual arrays.

Wednesday, August 8th
8:30-10:50 AM
SOFT-201-1: Increasing the Performance of Software-Defined Storage (Software Track Track)
Organizer + Chairperson: Matias Bjorling, Director Solid State System Software, Western Digital

Co-Organizer: Renu Raman, VP Cloud Architecture and Engineering, SAP

Paper Presenters:
Building High Performance, Cost-Effective Ceph All-Flash Arrays
Brien Porter, Sr Program Manager, Big Data Technologies, Intel

Using Software to Reduce High Tail Latencies on SSDs
Kapil Karkra, Software Architect, Intel

Key-Value Store Friendly SSD Interface Design and Optimization
Teng Yang, senior firmware engineer, Starblaze Technology

Using Flash Memory Cost-Effectively in Software Composable Infrastructures
Brian Pawlowski, CTO, DriveScale

Important New NVMe Features for Optimizing the Data Pipeline
Stephen Bates, CTO, Eideticom

Session Description:
There is no question that open-source software plays an ever-increasing role in data centers. For example, the companies that run mega-websites and clouds are able to achieve much higher economies of scale thanks to open-source projects like the Linux kernel, Ceph, and Open Stack. They would much rather contribute to open-source projects and than pay huge licensing or maintenance charges for the software they need. Flash memory and open-source software intersect in two ways: (1) flash-related system software may itself be open-source, e.g., the NVMe driver in Linux, F2FS (the Flash Friendly File System) and the LightNVM driver for open-channel SSDs, and (2) open-source software must be designed to utilize flash efficiently and take full advantage of its availability. The latter issue applies especially to storage software such as Ceph, which offers a combination of a traditional relational database and newer object-based methods. In addition, Ceph provides easy access to flash facilities, and provides efficiency in today’s flash-heavy environments.
About the Organizer/Moderator:
Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

Renu Raman is VP and Chief Architect of Cloud Architecture & Engineering at SAP. He is responsible for the architecture, design, and development of SAP’s groundbreaking HANA cloud infrastructure compute and storage. He also has devised a high-performance persistence architecture for in-memory databases which he described at a previous Flash Memory Summit. He was previously Founder/CEO at Unity Microsystems, a developer of memory virtualization technology. He also had a long career at Sun Microsystems where he focused on developing many highly successful SPARC processors and associated devices. He was also an executive-in-residence at Tallwood Venture Capital for several years. He earned an MSEE from Northwestern University.

Wednesday, August 8th
8:30-10:50 AM
TEST-201-1: Testing/Performance Analysis (Testing Track Track)
Organizer: Joseph Chen, VP Engineering, ULINK Technolgy

Co-Organizer + Co-Chair: Easen Ho, President, S3 Metrics

Paper Presenters:
Improved Drive Qualification Methods for Enterprise SSDs
Jeffrey Fritzjunker, Manager, Supply Chain Engineering, Storage Device Qualification, IBM

An Advanced Flash Emulator for Designing Today’s High-Capacity Controllers
Theodore Antonakopoulos, Professor, University of Patras

Design Register Accurate SSD Software Simulator
Haocheng Huang, IP Design Manager, Starblaze

How Will Your Enterprise SSD Handle Real Workloads?
Eden Kim, CEO, Calypso Systems

Diagnosing SSD Failures During Testing
Linden Hsu, R&D Engineer Expert, Advantest

Session Description:
Testing and performance analysis are an essential part of flash development and system evaluation. Conformance to standards, behavior under environmental stress, and the effects of varying workloads and system conditions must all be checked thoroughly. Performance analysis is also a key to determining how devices will behave in operation and in comparing devices during the evaluation stage. One problem of particular concern is wear, since the underlying memory elements are known to fail after a certain number of writes have been performed. Evaluations must be done with workloads that reflect actual client experience to ensure validity.
About the Organizer/Moderator:
Joseph Chen is VP of Engineering at Ulink Technology, a supplier of IT storage interface test tools. His focus areas include enterprise HDD/SSD development and qualification, SoC technical management, self-encrypted drives, and industry standards such as T10, IEEE 1667, and the Trusted Computing Group. He was previously Director of Systems Technology and Senior Firmware Manager at Samsung Electronics - SISA. At Samsung, he supervised SAS SSD design and development and managed the self-encrypting drive (SED) development project to produce Opal compliance. He has 30 years experience in the high-technology industry, including positions at Silicon Magic and Cirrus Logic. He holds an MS in computer science from Texas A&M University.

Easen Ho is the president of S3Metrics, a consultancy specializing in SSD testing. He was formerly CTO of Calypso Systems, a leading solid state technology test equipment and test services company. Easen has been active in test standards development, and has given many talks at events such as Flash Memory Summit. He is a principal architect of the SNIA Solid State Storage Performance Test Specification. He received his PhD from MIT and an MS from Tokyo Institute of Technology, both in laser and optical engineering. He has been involved in many storage ventures over the last 15 years, including being Founder and President of Digital Papyrus.

Wednesday, August 8th
9:45-10:50 AM
CMOB-201B-1: New PCIe/NVMe Memory Cards Open up New High-Speed Applications (Consumer/Mobile Applications Track Track)
Organizer + Chairperson: Yosi Pinto, Chairman, SD Association

Paper Presenters:
New Client Devices Using SD Express Cards as Expandable Storage
Jacek Wysoczynski, Software Strategic Planner, Intel

Adaptable/Expandable External Storage for Endpoints Using SD Express Cards
Lee Prewitt, Principal Program Manager, Microsoft

SD Express: Combining the Reliability of SD Cards with PCIe/NVMe
Yosi Pinto, Chairman, SD Association

Industrial IoT: Using SD Express Cards as Edge Storage Devices
Crystal Chang, Senior Manager, ATP Electronics

Session Description:
SD Cards have long been an easy way to add external storage to mobile devices. Now a new SD Express standard uses PCIe/NVMe to extend the card form to an even wider range of applications. Rates up to 985MB/s not only move data much faster, but also open up new applications. SD Express cards can serve as removable storage in mobile computing, high resolution cameras, gaming with 3D graphics, and automotive data collection. They also offer a simple expansion capability for existing devices and serve the needs of edge computing and the Industrial Internet of Things (IIoT).
About the Organizer/Moderator:
Yosi Pinto is Director of Standards at Western Digital (formerly SanDisk),and also serves as the Chairman of the Board and the Technical Committee Co-Chair at the SD Card Association (SDA). Mr. Pinto has played a major role in SD Card standards since they were first introduced in 1999. He developed the first SD card controllers, led the Memory Stick project, and was responsible for other SD/eMMC products and standards initiatives at SanDisk, JEDEC, and SDA. He holds more than 30 patents related to memory card technology, including many that are fundamental to the SD technology. He holds an MSEE from Stevens Institute of Technology and an MBA from Tel Aviv University.

Wednesday, August 8th
9:45 am-10:50 AM
SSDS-201B-1: New Flexible Form Factors for Enterprise and Datacenter SSDs (SSDs Track Track)
Co-Organizer + Co-Chair: Dave Landsman, Director Industry Standards, Western Digital

Organizer + Speaker: Amber Huffman, Intel Fellow, Intel

Co-Organizer + Co-Chair: Cliff Smith, Sr Product Line Manager, Enterprise SSDs, Micron

Co-Organizer: Anthony Constantine, Platform Architect, Intel

Paper Presenters:
How Form Factors Will Help Shape Tomorrow's Data Center World
Amber Huffman, Intel Fellow, Intel

Enterprise Designs Using the EDSFF Form Factors
Paul Kaler, Advanced Storage Technologist, HPE

EDSFF: Mainstream NVMe for the (Datacenter) Masses
Jonathan Hinkle, Principal Researcher, Lenovo

Datacenter Designs Using the EDSFF Form Factors
Mark A Shaw, Principal Hardware Engineering Manager, Microsoft

Session Description:
SSDs have now replaced hard drives (HDDs) in many storage applications. However, designers have simply continued to use form factors developed for HDDs. Such form factors reflect the sizes in which HDDs are commonly available, as well as their unique electrical, mechanical, and cooling requirements. SSDs, of course, have completely different characteristics. New form factors have now been standardized to allow for higher capacity, smaller footprints, more recent design best practices, and more flexibility. They are generally smaller and shorter to make room for more drives or other subsystems in racks and cabinets. They are also state-of-the-art with regard to electrical, mechanical, cooling, size, serviceability, power, connector types, and other factors. EDSFF (the Enterprise and Datacenter SSD Form Factor Working Group) has defined a series of form factors around a common connector aimed at handling a wide range of applications needs, including servers, storage systems, data centers, clouds, and megawebsites. The major new issue for designers is power dissipation which is always a problem in small or short form factors. However, past experience offers many solutions covering common situations.
About the Organizer/Moderator:
Dave Landsman is Director Industry Standards at Western Digital, where he manages storage standards across WD’s businesses. Dave is active in standards groups, including NVMe, PCI-SIG, JEDEC, SATA-IO, T10, T13, SNIA, SFF, SDA, CFA, and USB-IF. He is currently WD’s board representative for NVMe, SATA-IO, and the CompactFlash Association, and is co-chair of the Storage Work Group at the Trusted Computing Group. He has presented on standards at many conferences including Flash Memory Summit. Dave has over 30 years of experience in the semiconductor industry. He earned a BA in computer science from the University of California, San Diego.

Coming soon..

Cliff Smith is Enterprise NVMe SSD Business Line Manager at Micron, where he shapes Micron's SSD roadmap and strategy. He has recently completed an extensive analysis of the new EDSFF form factor standards, highlighting the benefits and trade-offs of this new approach to deploying SSDs in the datacenter. He also leads Micron's engagement in the hyperscale and OCP communities and launched the market-leading 9200 Enterprise SSD at Flash Memory Summit last year. He has over 20 years of experience innovating in non-volatile memory technologies. He earned an MBA and a BS in physics from University of California at Davis.

Anthony Constantine is a Platform Architect at Intel, where he focuses primarily on driving innovation to memory and storage from mobile to datacenter. He is active in the standards area, contributing to Open NAND Flash Interface, EDSFF, SFF, PCI-SIG, NVMe, and JEDEC. He serves as Technical Chair and Editor for both ONFI and EDSFF. He has over 18 years of experience in the technology industry with an expertise in physical interfaces, low power technologies, and form factors. Anthony earned a BS in Electrical Engineering from UC Davis.

Wednesday, August 8th
9:45-10:50 AM
CTRL-201B-1: Developing Controllers for Emerging Memory Technologies (Controllers Track Track)
Organizer + Chairperson: Dave Ebsen, Principal Architect, Seagate

Panel Members:
Panelist: Jeroen Dorgelo, Director Storage Marketing, Marvell

Panelist: Shai Fultheim, Founder, President and CEO, ScaleMP

Panelist: Stanley Huang, Sr Product Marketing Manager, Silicon Motion

Panelist: Rahul Advani, VP Marketing, Netlist

Session Description:
Emerging memory technologies, such as RRAM, MRAM, and 3D XPoint, have quite different characteristics from flash. So they require different controllers. Designers must become thoroughly familiar with the read and write cycle timings, wear, and error profiles, as well as special architectural features of each technology. Furthermore, the emerging technologies are still moving targets with major changes occurring in part size, density, and operating modes. Designers must not only solve today's problems, but must also provide the flexibility required in working with immature products.
About the Organizer/Moderator:
Dave Ebsen is an SSD Architect at Seagate Technology, where he focuses on system architecture and advanced development of firmware and ASIC technologies. A 20-year veteran of storage and storage related industries, he has been granted many patents for storage and networking innovation. He earned a BSCS from Augsburg University (Minneapolis, MN). For the past 10 years Dave has been focused on SSD's, and more recently, on specific features in controllers and firmware necessary to deploy SCMs in an enterprise product.

Wednesday, August 8th
9:45-10:50 AM
INVT-201B-1: Persistent Memory - The Answer to Today's Data Center Challenges (Persistent Memory Track Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Nathan Brookwood, Research Fellow, Insight 64

Paper Presenters:
Persistent Memory: The Answer to Today's Data Center Challenges
Andy Walls, Fellow/CTO/Chief Architect, IBM

Session Description:
Persistent memory, such as 3D XPoint or MRAM, offers close to DRAM speeds (and latency) at close to flash prices. Its use will lead to far better performance for cognitive computing, in-memory databases (such as Spark, Hadoop, and HANA), deep learning, pattern and real-time fraud detection, artificial intelligence, real-time analytics, data reduction, and cybersecurity. System and software developers will no longer have to work around relatively slow drive accesses, or worry about long latencies caused by data transfers that end up involving flash memory rather than DRAM. Of course, the transition will not be without its own challenges. Storage architects must deal with slower than DRAM speeds and endurance issues, and must develop innovative approaches including tiers and caches. Making effective use of persistent memory will take time, and will require advances in hardware, software, and applications.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. During his 40 year career in the industry, Mr. Brookwood has experience with Micronics Computers, Intergraph, Convergent Technologies, Prime Computer, and Digital Equipment. He is a graduate of MIT and has taken classes at Harvard Business School.

Wednesday, August 8th
9:45-10:50 AM
MRES-201B-1: NVMe Market Research Panel (Market Research Track Track)
Organizer + Chairperson: Jean Bozman, VP/Principal Analyst, Hurwitz & Associates

Panel Members:
Panelist: Andy Walls, Fellow/CTO/Chief Architect, IBM

Panelist: Mike Heumann, Managing Partner, G2M Communications

Panelist: Eric Burgener, Research Director Storage, IDC

Panelist: J Metz, Office of the CTO/Board Member, Cisco Systems

Panelist: Narayan Venkat, VP, Data Center Systems, Western Digital

Session Description:
NVMe has emerged rapidly as a major market since its introduction just a few years ago. It is intended as a standard package to enable designers to handle storage over the popular and widely supported PCIe bus. The largest part of the market is for simple adapters that connect a computer to a storage device. The advantage over the disk interfaces is higher speed. More recent extensions of NVMe have opened new markets for switches, software, management, and system-level storage devices. Markets also include all-flash arrays, storage appliances, NVMe over Fabrics (NVMe-oF) adapters, storage software, and intellectual property. NVMe-oF is the extension of NVMe to handle multiple computers, including clusters, multiprocessors, and distributed systems. As of 2017, over 100 companies had announced products based on NVMe, and over 100 had joined the NVM Express Organization, the governing body for NVMe. High-level members (known as promoters) include such important companies as Cisco, Dell EMC, Facebook, Intel, Micron, Microsemi, Microsoft, NetApp, Oracle, Samsung, Seagate, Toshiba, and Western Digital.
About the Organizer/Moderator:
Jean S. Bozman is Vice President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, cloud infrastructure, server and storage technology, and software-defined infrastructure (SDI). Before joining Hurwitz & Associates in 2016, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads . Bozman has more than 20 years of experience covering the worldwide markets for operating environments, servers, and the workloads that run on servers. She was Research Vice President of IDC’s Worldwide Server Group from 2002-2013. She has been widely quoted in the press and in online publications, such as Bloomberg, CNET, eWeek, Reuters and TechTarget. Ms. Bozman holds a B.S. degree from the State University of New York (SUNY) at Stony Brook, and a master's degree from Stanford University

Wednesday, August 8th
3:20-4:25 PM
AUTO-202A-1: The End-to-End Storage Challenge of Autonomous Transportation (Automotive Applications Track Track)
Organizer + Chairperson: Andy Marken, President, Marken Communications

Panel Members:
Panelist: Kun Zhou, Program Manager, California PATH, UC Berkeley

Panelist: Alan Messer, CTO of Global Connected Consumer Experience/VP of Software and Innovation, General Motors

Panelist: Clod Barrera, Distinguished Engineer/Chief Technical Strategist, IBM

Panelist: Ivan Ivanov, Distinguished Engineer, CoC Systems, Harman

Session Description:
Autonomous transportation isn’t just confined to the vehicle but a complete and comprehensive ecosystem of data capture, storage, distribution with different levels of speed, capacity, protection required at each point. This session is a global end-to-end view of the data and storage challenge facing automotive, storage, government and ancillary service providers - providing end-to-end security, privacy, data and storage support for Autonomous and AI.
About the Organizer/Moderator:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Wednesday, August 8th
3:20-4:25 PM
BMKT-202A-1: CMO Panel - Flash Will Be Everywhere but the Customer Still Rules (Business/Marketing Track Track)
Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Panel Members:
Panelist: Josh Epstein, Chief Marketing Officer, Kaminario

Panelist: Gary Lyng, CMO, Violin Systems

Panelist: Eric Herzog, CMO VP Worldwide Storage Channels, IBM

Panelist: Jason Nadeau, Storage Industry Disruptor, Pure Storage

Session Description:
Marketing enterprise flash storage isn't an easy job. The technology is complex and fast-changing, and customers are often very confused. How does one develop a clear message that responds to customer needs and offers the best return for the investment? Leading storage marketing leaders will discuss the changing dynamics of the customer journey. What role does marketing analytics play in gaining a competitive advantage? Has the marketing playbook really changed? What are the winning strategies with the shift to cloud, hyperconverged architecture, and software defined infrastructure? What magic do successful marketers have up their sleeve as they follow the golden rule of Know Your Customer?
About the Organizer/Moderator:
Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Wednesday, August 8th
3:20-4:25 PM
ENST-202A-1: Flash in Cloud Computing (Enterprise Storage Track Track)
Organizer + Chairperson: Jathin Ullal, Infrastructure Architect, Saygo

Paper Presenters:
Re-Architecting Cloud Storage with 3D XPoint and 3D NAND SSDs
Jack Zhang, Software Engineering Manager, Intel

Managing Flash in OpenSDS for Cloud-Native Frameworks
Steven Tan, VP & CTO Cloud Solution for Storage, Huawei

A Global-Scale Cloud Storage Platform Based on Nonvolatile Memory
Fei Liu, Storage Architect, Alibaba

AppNVM: A Framework for Application-specific FTLs on Tiered Storage
Ivan Picoli, PhD Fellow, IT University of Copenhagen

Session Description:
Storage is a crucial part of any cloud, regardless of its type or ownership. Cloud service providers have become major players in buying flash storage technology, looking for more IOPS even at higher cost to provide better performance. Providers also advertise SSDs as being available to users at extra cost Cloud providers also like the higher reliability of flash memory and its operating efficiency (space, power, and cooling requirements). However, the extra cost remains an issue, particularly in the amounts needed in cloud environments, as do the issues of wear and endurance.
About the Organizer/Moderator:
Jathin Ullal is a Global Product Line Manager at HPE, where he collaborates with customers and identifies their needs to translate them into successful products. He was previously an Infrastructure Architect at Saygo, where he was responsible for the design, deployment, and support of a hybrid cloud infrastructure covering over 80 cloud and IT offerings across legacy IT, private, public, and managed cloud. Before Saygo, he set up and led marketing and engineering teams at both venture-funded startups and large companies. He has held leadership positions at HP, Cisco, and Nortel, including being in charge of the design, deployment, and support of the networking, security, and management infrastructure for 15 SaaS applications hosted in 24 global data centers. Widely regarded as an expert in cloud computing and SaaS, he has presented at many conferences and led sessions and seminars. He holds an MSEE from the University of New Mexico.

Wednesday, August 8th
3:20-4:25 PM
INTL-202A-1: Reimagining the Data Center Memory and Storage Hierarchy (Intel Track)
Session Sponsor: Intel
Panel Members:
Panelist: Greg Matson, Director SSD Strategic Planning/Product Marketing, Intel

Panelist: James Myers, Director Data Center Solutions, Intel

Session Description:
The size and scale of information that must be captured, stored, and analyzed in data centers on a daily basis is astonishing. The more interesting aspect of this data is the potential business value it represents. However, the limitations of the traditional memory and storage hierarchy present a design challenge for data centers. This session will explore Intel® Optane™ DC, QLC 3D NAND and EDSFF innovations, highlighting new classes of memory and storage that rework the hierarchy to break through existing performance, capacity, and cost limitations. You will walk away with tips for re-architecting your solutions now, discover software tools and resources to further optimize your solutions, and learn how to make your solutions ready for exciting future innovations.
About the Organizer/Moderator:
Wednesday, August 8th
3:20-4:25 PM
INVT-202A-1: A Satellite-Based Architecture for High-Throughput Storage (Architectures Track Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Marc Farley, Principal, Idix

Paper Presenters:
A Satellite-Based Architecture for High-Throughput Storage
Michael Koets, Staff Engineer, Southwest Research Institute

Session Description:
There is an increasing need to provide high-throughput, high-capacity data storage for satellites which host instruments such as imaging sensors and synthetic aperture radars. NAND flash memories provide an attractive approach to meeting these data storage requirements, providing high storage density, power efficiency, and nonvolatile storage. However, flash memory for space applications also has some important limitations including slow and asymmetric access rates, block-based organization, and limited wear. This talk will describe an architectural approach to this problem that employs precise scheduling of accesses to numerous parallel flash devices to provide high-rate, multi-channel recording as well as simultaneous high-rate data playback. This presentation will also include a description of the methodology of a software-supported architectural design along with several case studies of data storage systems with varying capabilities.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Marc Farley is a Sr Product Manager at HPE and the author of Building Storage Networks and Fundamentals of Storage Networks. He has worked in the network storage industry for over 20 years.

Wednesday, August 8th
3:20-5:45 PM
CTRL-202-1: Controllers and Flash Technology, Part 2 - Error Correcting Codes (Controllers Track Track)
Organizer + Chairperson: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Presenters:
Eliminating the Error Floor for LDPC with NAND Flash
Shafa Dahandeh, Sr. Error Code Engineer, NGD Systems

Artificial Neural Network Coupled LDPC ECC for 3D-NAND Flash Memories
Toshiki Nakamura, Student, Japan/Chuo University

Ultra-Low Resource FPGA implementation of Finite Alphabet Iterative Decoders
David Declercq, CTO, CodeLucida

A Low-Cost LDPC Decoder for Flash Memory
Osso Vahabzadeh, Staff Design Engineer, Symbyon Systems

Fully Integrated LLR Calculation Flow
Lorenzo Zuolo, Flash Engineer, Microsemi

Generalized Tree Architecture with High-Radix Processing for an SC Polar Decoder
Taehwan Kim, Professor, Korea Aerospace University

Session Description:
This session describes recent developments in implementing LDPC (low density parity check) and other codes for error correction in NAND flash memories. You will learn practical aspects of power-efficient LDPC implementations, handling new NAND technologies, and developing an erasure recovery scheme. Get important insight from industry experts and have time for direct questions and answers!
About the Organizer/Moderator:
Erich Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Wednesday, August 8th
3:20-4:25 PM
NEWM-202A-1: RRAM (New Memory Technologies Track Track)
Organizer + Chairperson: Dave Eggleston, Principal, Intuitive Cognition Consulting

Panel Members:
Panelist: Etienne Nowak, Head Advanced Memory Laboratory, CEA-LETI

Speaker: Amigo Tsutsui, Senior Business Producer, Sony Semiconductor Solutions

Speaker: Hagop Nazarian, VP Engineering, Crossbar

Speaker: Stefan Mueller, CEO, FMC

Session Description:
RRAM (resistive RAM) development keeps progressing, with companies using a variety of approaches to pursue potential applications in high capacity storage, mid-range nonvolatile caches, and low cost embedded solutions. Come hear industry leaders offer views on the current state of RRAM technology, the target applications, and the road to commercialization.
About the Organizer/Moderator:
Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Wednesday, August 8th
3:20-5:45 PM
FTEC-202-1: 3D Flash (Flash Technology Track Track)
Organizer + Chairperson: Shawn Adams, Product Marketing Manager, Micron

Paper Presenters:
HeatWatch: Exploiting 3D NAND Self-Recovery and Temperature Effects
Yixin Luo, Doctoral Student, Carnegie-Mellon University

3D TLC NAND Component-Level Characterization Based on Real-World Enterprise Work
Patrick Breen, Flash Characterization Engineer, IBM

Improving 3D NAND Technology Scaling by Meeting Channel Hole Process Challenges
Bart van Schravendijk, Fellow, R & D Division, Lam Research

3D NAND Technology Scaling Helps Accelerate AI Growth
Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Measuring 3D TLC Voltage Distributions and Optimized Read Threshold Calibration
Oliver Hambrey, Research Engineer, Siglead

3D NAND Flash Cell Architecture: Recent Progress and Comparisons
Jeongdong Choe, Consulting Engineer, TechInsights

A Graphical Journey into 3D NAND Operations
Vic Ye, Flash Analysis Manager, YeeStor

Session Description:
3D NAND flash continues to advance and will soon dominate flash technology because of its lower cost and higher density. Issues in its widespread use include error-correction methods, manufacturing challenges, reliability, and lifespan. Manufacturers will need to continue to improve 3D processes to meet the needs of many applications. Situations requiring high reliability and extended lifetimes will require a great deal more development effort.
About the Organizer/Moderator:
Shawn Adams is a Product Marketing Manager at Micron Technology, where he focuses on client SSD and NAND marketing. A 16-year veteran of the technology industry, he has led product development, strategy, and marketing for hardware and software portfolios. He has experience in both domestic and international markets and in a broad range of virtual market segments. Before joining Micron Technology, he worked for Healthwise, DBSI, and MPC. He holds an MBA from Northwest Nazarene University and a Bachelor’s in Business Administration from Idaho State University.

Wednesday, August 8th
3:20-5:45 PM
NVME-202-1: NVMe-oF JBOFs/Testing and Interoperability (NVMe Track Track)
Session Sponsor: NVM Express
Chairperson: Bryan Cowger, VP Sales/Marketing, Kazan Networks

Organizer + Chairperson: Brandon Hoff, Software Architect, Broadcom

Panel Members:
Speaker: Fazil Osman, Distinguished Engineer, Broadcom

Speaker: Praveen Midha, Director Product Management/Strategic Marketing, Marvell

Speaker: Tim Sheehan, Manager Datacenter Technologies, UNH-IOL

Speaker: Mark Jones, Director Technical Marketing & Performance, Broadcom

Session Description:
Part 1 NVMe-oF JBOFs The use of JBODs/JBOFs in traditional arrays is well-known, but now designers want to extend the concept to cloud/hyperscale datacenters. By replacing DAS storage with composable infrastructure (disaggregated storage) based on JBOFs as the storage target, designers can improve business agility, simplify hardware upgrades, and lower both CAPEX and OPEX. This session will cover JBOF architecture, show how it is deployed in a composable infrastructure environment, and provide examples of real-world applications and benefits. Part 2 - Plugfests and Interoperability for NVMe Standards and Solutions NVMe covers a diverse universe of standards, products, and solutions. Interoperability and compliance are the subjects of a key technical group within the NVMe organization. Interoperability issues exist at three levels: 1) conformance to the standards such as NVMe, NVMe-MI, NVMe-oF, FC-NVMe, and RDMA, 2) proven interoperability between products at industry-sponsored plugfests, and 3) reliability and recovery capabilities from high stress testing – e.g., error injection and other sources. This session will cover the plugfests that test NVMe solutions, what each one covers, and where to find documentation and test results.
About the Organizer/Moderator:
Bryan Cowger, with over 25 years of storage industry experience, is VP Sales/Marketing at Kazan Networks, a startup developing ASICs that target new ways of attaching and accessing flash storage in enterprise and hyperscale datacenters. Kazan Networks’ products utilize emerging technologies such as NVMe and NVMe-oF. Bryan has spent his career defining and bringing to market successful high-performance storage networking ASICs for such protocols as Fibre Channel, SAS, SATA, Ethernet, PCIe, and NVMe. He has been awarded 4 patents in area of storage controller architecture. Before joining Kazan Networks, he was VP Sales/Marketing & Co-Founder at Sierra Logic, a developer of SATA-to-Fibre Channel controllers. He also spent over 10 years as a design engineer at Hewlett-Packard and Agilent Technologies. He holds a BS in Electrical Engineering from UC San Diego.

Brandon Hoff is Distinguished Software Architect at Broadcom, where he focuses on new product strategy, including product development interlock, business planning, and sales strategy development for growth initiatives. He has also worked on innovation initiatives, end user strategies, technology and strategy solutions for Web giants, and product portfolio leadership. He has been an active participant in NVM Express, the sponsoring organization for NVMe standards, and has also been IBTA Marketing Work Group Co-Chair. He is a frequent participant at industry events, including NVM Express meetings, SNIA conferences, and Ethernet Alliance events. He has over 25 years of industry experience, including a stint as Chief Strategy Officer/Chief Marketing Officer at CipherOptics, where he was responsible for managing all aspects of marketing, corporate strategy, product management, field and corporate marketing, marketing communications, public relations, branding, and lead generation. He holds an MBA from the University of Colorado (Boulder) and a BSEE from Colorado State University.

Wednesday, August 8th
3:20-5:45 PM
NVME-202-2: PCIe/NVMe Storage (NVMe Track Track)
Co-Organizer: Deepankar Das, CTO, Sureline Systems

Organizer + Chairperson: Rakesh Cheerla, Solution Planner, Intel

Paper Presenters:
Using Multi-Drive Fusion to Scale NVMe Performance
Jinling Chen, Field Engineering Manager, UNIC

Reconfigurable Compression Engine for NVMe-Based Storage Systems
David Sloan, Software Engineer, Eidetic communications

RAIN: Reinvention of RAID for the World of NVMe
Sergey Platonov, Chief Strategist, RAIDIX

FPGA based PCI Express Gen4 NVMe SSD Platform
Amit Saxena, VP Engineering, Mobiveil

Building Dense NVMe Storage
Mikhail Malygin, Principal Software Engineer, YADRO

Using Storage Accelerators to Provide Predictable NVMe SSD Performance
Shahar Noy, Sr Director Product Marketing, Marvell

Session Description:
PCIe SSDs have rapidly emerged as the devices of choice in the enterprise because of their high speed, well-understood and widely used interface, and extensive support from major vendors. The NVMe standard for storage operations over PCIe offers a base platform comparable to those available for disk interfaces such as SAS and SATA. Furthermore, continuing advances in the underlying PCI Express interface (now in Version 4.0) offer a solid path for the future. Attention has now moved to implementing a wide range of essential system-level features in PCIe/NVMe. These include server storage platforms, standards for remote monitoring and management, high-availability features such as dual-porting, and virtual implementations for use with VMware.
About the Organizer/Moderator:
Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Rakesh is a Senior Product Manager for Storage Solutions at Xilinx, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Wednesday, August 8th
3:20-5:45 PM
PMEM-202-1: Remote Persistent Memory (Persistent Memory Track Track)
Session Sponsor: SNIA, JEDEC, & OpenFabrics Alliance (OFA)
Organizer: Jonathan Hinkle, Principal Researcher, Lenovo

Chairperson: Rob Peglar, President, Advanced Computing and Storage

Organizer: Jim Pappas, Director, Initiative Marketing, Intel Server Platforms Group

Chairperson + Speaker: Paul Grun, OpenFabrics Alliance Chair; Storage I/O and Interconnect Architect, Cray

Paper Presenters:
Remote Persistent Memory-The Case for Use Cases
Paul Grun, OpenFabrics Alliance Chair; Storage I/O and Interconnect Architect, Cray

Remote Persistent Memory in Feature Animation Production
Scott Miller, Technology Fellow, Engineering and Infrastructure, DreamWorks Animation

HPC and Remote Persistent Memory
Jim Harrell, Director of Engineering, Cray

RPM Impacts on Network Architecture
Idan Burstein, Staff Silicon Architect, Mellanox

Session Description:
Remote persistent memory (RPM) has a wide range of potential applications and use cases, including scale-out file and object systems, in-memory databases, machine learning, artificial intelligence, and hyperconverged infrastructure. However, accessing PM over a fabric creates a whole new set of opportunities and challenges; for example, networks will need to evolve to leverage the potential of RPM. But successfully evolving networks and network stacks depends first on developing a crisp understanding of application requirements and the use cases to which RPM will be applied. This section begins with an update on industry-wide efforts to clearly identify possible use cases for RPM. It then explores the benefits and potential impacts in both the commercial and HPC spaces from the application perspective. The section concludes by exploring changes in network design necessary to enable applications to leverage remote persistent memory fully.
About the Organizer/Moderator:
Jonathan Hinkle is Director, Systems Platform Technologist at Lenovo, where he drives new server architecture and technologies in their Enterprise Product Group. Previously, Jonathan was Storage and Memory Systems Architect at Viking Technology, where he developed next-generation memory and storage products and technologies. Before Viking, Mr. Hinkle worked at IBM where he developed server systems ranging from high-end enterprise boxes to blade servers. He is the chairman of the JC45.1 RDIMM committee and the Hybrid Memory Module task group in the JEDEC standards organization. He also invented and drove first development of the VLP DIMM and the SATADIMM SSD. He is a senior member of the IEEE and has a Bachelors and Masters degree in Computer Engineering from North Carolina State University. He is a member of the Program Executive Committee for Flash Memory Summit.

Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. In this role, Jim is responsible for establishing broad industry ecosystems that comply with new technologies in the areas of Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has founded or served on several organizations in these areas, including: PCI Special Interest Group, InfiniBand Trade Association, Open Fabrics Alliance, the Green Grid, and several emerging initiatives in his newest focus area of Solid State Storage. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has previously been the Director of Technology Initiatives in Intel’s Desktop Products Group, and successfully led technologies such as AGP Graphics, DVD, IEEE 1394, Instantly Available PC, PCI, USB, and other advanced technologies for the Desktop PC. Jim has 30 years of experience in the computer industry, has been granted eight U.S. patents in the areas of computer graphics and microprocessor technologies, and spoken at major industry events, including the Intel Developer’s Forum (IDF), WinHEC, Storage Networking World, PC Strategy, Microprocessor Forum, Consumer Electronics Show, Server I/O and the Applied Computing Conference. He holds a B.S.E.E. from the University of Massachusetts, Amherst, Massachusetts.

Paul Grun, Chair, OpenFabrics Alliance, is a senior technologist in Cray’s Storage and Data Management group, where he focuses on applying I/O technology to building large-scale systems. He is also a member of the InfiniBand Trade Association’s Steering Committee and chair of the Technical Working Group. He was chair and principle author for the working group responsible for creating the RoCE (RDMA over Converged Ethernet) specification. He also played a key role in creating the InfiniBand transport protocol. During his more than 30 year career, he has been intimately involved in all aspects of server I/O beginning with storage for large mainframe systems and,turning to high performance network architecture. He earned a BSEE from Syracuse University.

Wednesday, August 8th
3:20-5:45 PM
SOFT-202-1: Improving Performance and Scalability for Advanced Systems (Software Track Track)
Co-Organizer: Matias Bjorling, Director Solid State System Software, Western Digital

Organizer + Chairperson: Renu Raman, VP Cloud Architecture and Engineering, SAP

Paper Presenters:
Ceph Optimizations for NVMe
Chunmei Liu, Senior Engineer, Intel

Storage Performance Challenges in Virtualization
Felipe Franciosi, Senior Staff Software Engineer, Nutanix

NVMe over Fabrics: Scaling Up with the Storage Performance Development Kit
Ben Walker, Storage Solutions Architect, Intel

LINSTOR: A Cluster-Wide Control Path for Storage Management
Philipp Reisner, CTO, Linbit

Open Source Data Reduction for High Performance Flash Storage
Louis Imershein, Principal Product Manager, Red Hat

Session Description:
There is no question that open-source software plays an ever-increasing role in data centers. For example, the companies that run mega-websites and clouds are able to achieve much higher economies of scale thanks to open-source projects like the Linux kernel, Ceph, and Open Stack. They would much rather contribute to open-source projects and than pay huge licensing or maintenance charges for the software they need. Flash memory and open-source software intersect in two ways: (1) flash-related system software may itself be open-source, e.g., the NVMe driver in Linux, F2FS (the Flash Friendly File System) and the LightNVM driver for open-channel SSDs, and (2) open-source software must be designed to utilize flash efficiently and take full advantage of its availability. The latter issue applies especially to storage software such as Ceph, which offers a combination of a traditional relational database and newer object-based methods. In addition, Ceph provides easy access to flash facilities, and provides efficiency in today’s flash-heavy environments.
About the Organizer/Moderator:
Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

Renu Raman is VP and Chief Architect of Cloud Architecture & Engineering at SAP. He is responsible for the architecture, design, and development of SAP’s groundbreaking HANA cloud infrastructure compute and storage. He also has devised a high-performance persistence architecture for in-memory databases which he described at a previous Flash Memory Summit. He was previously Founder/CEO at Unity Microsystems, a developer of memory virtualization technology. He also had a long career at Sun Microsystems where he focused on developing many highly successful SPARC processors and associated devices. He was also an executive-in-residence at Tallwood Venture Capital for several years. He earned an MSEE from Northwestern University.

Wednesday, August 8th
4:40-5:45 PM
CTRL-202B-1: Flash Storage with 24G SAS Leads the Way in Crunching Big Data (Controllers Track Track)
Session Sponsor: SCSI Trade Association (STA)
Organizer + Chairperson: Rick Kutcipal, President, SCSI Trade Association (STA)

Panel Members:
Panelist: Mohamad El-Batal, Sr. Director of Architecture, Seagate

Panelist: Kevin Marks, Principal Engineer, Dell

Panelist: Jeremiah Tussey, Product Marketing Manager (Alliances), Scalable Storage Business Unit, Microsemi

Session Description:
The recent data explosion is a huge challenge for storage and IT system designers. How do you crunch all that data at a reasonable cost? Fortunately, your familiar SAS comes to the rescue with its new 24 G speed. Its flexible connection scheme already allows designers to scale huge external storage systems with low latency. Now the new high operating speed offers the throughput you need to bring big data to its knobby knees! Our panel of storage experts will present practical solutions to today’s petabyte problems and beyond.
About the Organizer/Moderator:
Currently serving as a Marketing Manager in the Data Center Storage Group at Broadcom, Rick is a 25-year computer and data storage business veteran. He coordinates the majority of standards activities for Broadcom worldwide and serves at the President of the SCSI Trade Association. Rick received his bachelor’s and master’s degrees in electrical engineering from the University of Utah.

Wednesday, August 8th
4:40-5:45 PM
FTEC-202B-1: Annual Update on Flash Memory for Non-Technologists (Flash Technology Track Track)
Chairperson: Joni Clark, Business Development Manager, Seagate

Organizer: Jay Kramer, President, Network Storage Advisors

Panel Members:
Session Description:
"Why a four-year-old child could understand this report. Run out and find me a four-year-old child. I can't make head nor tail out of it."- Groucho Marx in Duck Soup Do you feel like the storage industry in which you participate every day is passing you by? Are you not sure about the meaning of QLC, NVDIMM, RoCE, and SDS and afraid to ask? Do you think I/O determinism might have something to do with Darwin? If so, come let an expert speaker tell you what you really need to know about the very latest flash technologies. You?ll then be ready for the next round of revolutionary, disruptive, transformative, paradigm-shifting, and singularity-destroying advances that will come our way next year!
About the Organizer/Moderator:
Coming soon..

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Wednesday, August 8th
4:40-5:45 PM
INTL-202B-1: Bringing New Capabilities to Client Computing (Intel Track)
Session Sponsor: Intel
Panel Members:
Panelist: David Lundell, Director Client SSD Strategic Planning and Product Marketing, Intel

Panelist: Jeff McLeod, Director Client Optane Solutions, Intel

Session Description:
The client computing memory and storage hierarchy is undergoing a major transformation. This session will review how Intel Optane™ and 3D NAND technologies enable new client architectures. Included is a review of key memory and storage technologies, as well as new and innovative solutions being delivered using them. Questions that will be answered include: How can Optane technology solutions address system needs as memory or storage? Why is QLC 3D NAND a disruptor in the industry? What is the future of TLC NAND?
About the Organizer/Moderator:
Wednesday, August 8th
4:40-5:45 PM
INVT-202B-1: NVMe-oF - Enabling this Next Gen Infrastructure (NVMe-over-Fabrics (NVMe-oF) Track Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Marc Staimer, President, Dragon Slayer Consulting

Paper Presenters:
NVMe-oF: Enabling the Next Generation Infrastructure
David Black, Distinguished Engineer, Dell EMC

Session Description:
With NVMe poised to take over as the interface of choice for connecting super-fast storage devices to servers, the next logical question is: "What about the network between servers and storage?" Enter NVMe over Fabrics (NVMe-oF), the high-bandwidth, low-latency protocol for enabling shared (multi-host) access to NVMe storage. This talk will describe the system-level performance improvements that have been experienced so far from using NVMe-oF. Although speed and throughput increases are compelling, additional capabilities are required for NVMe-oF to serve as a robust, general-purpose, enterprise-class storage fabric. As such, this talk will also review the state of such capabilities for NVMe-oF over Fibre Channel and Ethernet fabrics. NVMe-oF over Fibre Channel is maturing quickly into a solid offering in the near-term, whereas NVMe-oF over Ethernet will take more time. The talk will close by describing surprising side effects in the SCSI world that have been created by the advent of NVMe technology.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Marc Staimer, as President and CDS of the 20-year-old Dragon Slayer Consulting business with 38 years in the industry. He is well known for his in-depth and keen understanding of user problems, especially with storage, networking, applications, cloud services, data protection, and virtualization. Marc has published thousands of technology articles and tips from the user perspective for internationally renowned online trades including many of TechTarget’s Searchxxx.com websites and Network Computing and GigaOM. Marc has additionally delivered hundreds of white papers, webinars, and seminars to many well-known industry giants such as: Brocade, Cisco, DELL, EMC, Emulex (Avago), HDS, HPE, LSI (Avago), Mellanox, NEC, NetApp, Oracle, QLogic, SanDisk, and Western Digital. He has additionally provided similar services to smaller, less well-known vendors/startups including: Asigra, Cloudtenna, Clustrix, Condusiv, DH2i, Diablo, FalconStor, Gridstore, Nexenta, Neuxpower, NetEx, NoviFlow, Pavilion Data, Permabit, Qumulo, SBDS, StorONE, Tegile, and many more. His speaking engagements are always well attended, often standing room only, because of the pragmatic, immediately useful information provided

Wednesday, August 8th
4:40-5:45 PM
NEWM-202B-1: MRAM (New Memory Technologies Track Track)
Organizer + Chairperson: Dave Eggleston, Principal, Intuitive Cognition Consulting

Panel Members:
Panelist: James Singer, Director Applications Engineering, Everspin

Panelist: Andy Walker, VP of Product, Spin Transfer Technologies

Panelist: Tetsuo Endoh, Professor, Tohoku University

Panelist: Barry Hoberman, , Independent Consultant

Panelist: Brent Yardley, Senior Technical Staff Member/Master Inventor, IBM Systems

Session Description:
MRAM is rapidly entering the marketplace with the commercial availability of 256Mb standalone STT-MRAM parts, and the integration of embedded MRAM with 28nm logic. The world?s fastest SSDs leveraging an MRAM cache have been announced, and non-volatile (NV) logic with MRAM elements has been proposed. The distinguished panelists will discuss the enormous range of MRAM applications, the current state of development and commercialization, and the disruption and opportunities MRAM creates.
About the Organizer/Moderator:
Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Thursday, August 9th
Thursday, August 9th
8:30-9:35 AM
ENST-301A-1: Application Acceleration (Enterprise Storage Track Track)
Organizer + Chairperson: KRS Murthy, CEO, I Cubed

Paper Presenters:
Benefits and Challenges of using SmartNICs for Distributed Shared Storage
Kirill Shoikhet, Chief Technical Architect, Excelero

Increasing Database Performance by Placing Transactional Functions in an SSD
Woo Suk Chung, Director, SK hynix

An NVMe-based FPGA Storage Workload Accelerator
Sean Gibb, VP Software, Eideticom

Session Description:
One of the main purposes for employing flash memory is to accelerate applications. Many of the most popular recent applications, such as business analytics and NoSQL databases, often run quite slowly, particularly as their datasets increase in size. Furthermore, high-speed SSDs may themselves require acceleration as their requirements are beyond the capabilities of many low-end processors.
About the Organizer/Moderator:
KRS Murthy is an experienced venture capitalist, serial entrepreneur and corporate strategist. He is currently focused on mergers and acquisitions, corporate governance, and competitive strategy. He has developed national level technology and industry strategies in multiple key areas. He has led many companies at many different stages and has grown companies to sales of over $500 million. He is a popular speaker at conferences around the world and a leader in many technical societies, including IEEE Nanotechnology Council, IEEE Engineering Management Society, IEEE Computer Society, Silicon Valley Engineering Council, and IEEE Standards Board. Murthy also has experience as a USA Country Manager for AT&T and AT&T Bell Labs and as a professor of computer engineering at California State University, Pomona & Fullerton. He has received a Distinguished Service Award from the IEEE Engineering Management Society and a Distinguished Achievement Award from the President of India.

Thursday, August 9th
8:30-9:35 AM
FNET-301A-1: Networking Flash with Ethernet and Fibre Channel (Flash Storage Networking Track)
Chairperson: Alan Weckel, CEO/Founder, 650 Group

Organizer: Rob Davis, VP Storage Technology, Mellanox

Paper Presenters:
Fibre Channel Networked Flash Storage
Curt Beckmann, Product Architect Nvme Over Fibre Channel, Brocade

Ethernet Is the Obvious Way to Network Flash Storage
J Metz, Office of the CTO/Board Member, Cisco Systems

Session Description:
When you think of computer networking, which protocol comes to mind first? Obviously, Ethernet! What is next? How about Fibre Channel? So why not use these well-known interfaces to share flash storage among multiple compute nodes, allowing them to maximize utilization and perform system-wide operations such as clustering and failover. Ethernet is surely the most widely used, most commonly supported, and most familiar solution. And Fibre Channel technology was the basis for the SAN architecture. If an application (such as high-performance computing, video transmission, or financial transactions) needs higher throughput or lower latency than common versions offer, higher-speed versions are available, as are low-latency extensions such as NVMe over Fabrics (NVME-of), Remote Direct Memory Access (RDMA) and iSCSI Extensions for RDMA (iSER). Designers must consider many issues, including their familiarity with particular approaches, existing uses, latency and performance requirements, scalability, and ecosystem (including management tools).
About the Organizer/Moderator:
Alan Weckel is Technology Analyst/Co-Founder at 650 Group, where he is in charge of Ethernet switch research and new areas such as SDN forecasting and WAN optimization. He has written many articles for the trade and technical press, and is frequently quoted in such leading publications as Bloomberg, Businessweek, Forbes, Network World, and the Wall Street Journal. Before co-founding 650 Group, he was VP/analyst at Dell’Oro Group and had engineering and software development experience at Raytheon, General Electric Power Systems, and Cisco. He holds a BSEE and an MS in Management from Rensselaer Polytechnic Institute.

Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 9th
8:30-9:35 AM
HPCA-301A-1: Non-Volatile Memory Accelerates High-Performance Computing (High-Performance Computing Applications Track)
Chairperson: Addison Snell, Analyst, Intersect360 Research

Organizer: Gary Grider, HPC Division Leader, Los Alamos National Laboratory

Paper Presenters:
Get Software Out of the Way of High Performance Flash Arrays
Tom Matson, Business Development Manager, One Stop Systems

Next-Generation NVMe-Native Parallel Filesystem for Accelerating HPC Workloads
Liran Zvibel, CTO And Co-Founder, WekaIO

OpenFAM API for Efficient Access to Global, Non-volatile Fabric-attached Memory
Dave Emberson, ,

Session Description:
High-performance computing requires maximum resources for solving enormous problems in genetics, drug discovery, weapons development, power plant simulation, computer-aided design and manufacturing, computational physics and chemistry, virtual reality, weather prediction, and economic analysis. The latest non-volatile memory technologies can provide a much needed speed boost, eliminating the need to wait for slow disk accesses. However, much needs to be done at the operating system, filesystem, and management levels to make this all practical. Data sets are often very large, and data of varied types must be handled efficiently. FPGAs can provide additional speed boosts when needed, and networking via NVMe-oF can provide fast access to large amounts of distributed storage. Advances can be phenomenal if the right set of supporting tools and technologies can be developed quickly.
About the Organizer/Moderator:
Addison Snell is the CEO of Intersect360 Research and a veteran of the high performance computing (HPC) industry. He has established Intersect360 Research as a premier source of market information, analysis, and consulting. He was named one of 2010's "People to Watch" by HPCwire. He is a regular participant at both Supercomputing and the ISC High-Performance conferences as a speaker, panelist, and chairperson. Before co-founding Intersect360, Addison was an HPC industry analyst for IDC, where he was well-known among industry stakeholders. Before joining IDC, he was a marketing leader and spokesperson for SGI's super-computing products and strategy. Addison holds a master's degree from the Kellogg School of Management at Northwestern University and a bachelor's degree from the University of Pennsylvania.

Gary Grider is the Leader of the High-Performance Computing (HPC) Division at Los Alamos National Laboratory (LANL). He is responsible for all aspects of high performance computing technologies and deployment. He also manages the R&D portfolio for providing HPC solutions to the Lab through funding of university and industry partners. Additionally, he is the US Department of Energy Exascale Storage, IO, and Data Management National Co-Coordinator, helping manage US government investments in data management, mass storage, and I/O. Gary has 30 active patents or applications in the data storage area and has been working in HPC and HPC related storage for over 30 years. Gary earned BSEE and MBA degrees at Oklahoma State University and has presented at many events, including the OpenFabrics Workshop, Usenix HotStorage Workshop, Storage Developer Conference, and past Flash Memory Summits.

Thursday, August 9th
8:30-9:35 AM
INVT-301A-1: Machine Learning and Storage Applications (Enterprise Applications Track Track)
Chairperson: Rohit Gupta, Segment Manager, Enterprise Storage Solutions, Western Digital

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Machine Learning and Storage Applications
Nisha Talagala, CTO, ParallelM

Session Description:
Today we are experiencing the intersection of multiple trends, each of which changes the storage and data landscape in powerful ways. Machines and applications generate massive quantities of new data whose value degrades over time unless it can be efficiently analyzed. Both new and long-existing machine learning and deep learning algorithms have shown promise at extracting insight from data for a wide range of usages. Hardware innovations in CPUs, DRAM, and persistent memory are now able to scale these analytic techniques. In addition, new architectures for data processing and storage have emerged, while existing architectures such as in-memory databases have also been extended to address these workloads. This talk will describe the intersections between machine learning and storage applications, covering the implications of machine learning and analytics as a new use case for storage, as well as how machine learning can be used within the storage infrastructure and applications.
About the Organizer/Moderator:
Coming soon..

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Thursday, August 9th
8:30-9:35 AM
NEWM-301A-1: Life Beyond Flash - New Non-Volatile Memory Technologies (New Memory Technologies Track Track)
Chairperson: Jim Cantore, President, JLC Associates

Organizer: Dave Eggleston, Principal, Intuitive Cognition Consulting

Paper Presenters:
Emerging Memory and Capital Spending Trends
Thomas Coughlin, President, Coughlin Associates

NRAM Offers Huge Speed Increases for Storage Applications While Simplifying the
Bill Gervasi, Principal Systems Architect, Nantero

Achieving Higher-Density Code Storage with Flash Memory
K C Shekar, Sr Director Strategic Marketing, Winbond Electronics

Session Description:
Is there life after flash? Or will flash memory keep improving and dominate all NVM technology into the next decade? The panelists will peer into their crystal balls, and provide perspective on the great non-volatile beyond. They will provide insight and analysis on technology trends, disruption, singularities, product roadmaps and completion dates, and other memory issues that may go beyond human predictive capabilities. Bring your opinions, comments or Ouija board, tarot cards, fortune cookies, astrological instruments, tea leaves, or magic lamps and join in the discussion!
About the Organizer/Moderator:
Jim Cantore has been the President and Chief Analyst with JLC Associates, a high technology consulting firm since September 2003. Mr. Cantore consults in high technology, business development, strategic marketing and market intelligence to financial and high technology companies. He has over 29 years' combined experience in semiconductor, computer and solar industries. Mr. Cantore specializes in microprocessors, Intel; computer virtualization, graphics, nVidia, storage and network processors; DSP; power and analog chips; semiconductor business cycle analysis; DRAM; 3D NAND ReRAM, Storage Class Memory, SCM and NOR flash; solid state drives, SSD based systems; advanced non-volatile memory; STTRAM; CBRAM; 3D-Xpoint; Micron; Samsung; SK Hynix; Wafer procurement and supply, polycrystalline silicon, thin film PV; intellectual property; wafer foundry; 450 mm wafer fabs; semiconductor process roadmaps; EUV; optical critical dimensioning; front-end and back-end semiconductor manufacturing capital equipment; AMAT, ASML, LRCX; wafer scale and TSV packaging; back end assembly, OSATs; Data Center storage systems; Cloud technology; laptop PCs; tablet PCs; smart phones; advanced integrated fan-out wafer-level packaging (FO-WLP); advanced motion control; PCB laminate industry; Flexible PCBs; machine vision; flexible electronics and advanced ceramics semiconductor applications; motion control; wearable electronic devices; Cloud Systems; ioT.

Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave’s extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Thursday, August 9th
8:30-9:35 AM
TEST-301A-1: Testing Issues (Testing Track Track)
Chairperson: Marilyn Kushnick, R & D Engineer, Advantest

Paper Presenters:
Testing Dual-Port NVMe SSDs
Sneha Nadig, R&D Applications Engineer, Advantest

Enabling Realistic Simulations of the Latest Multi-Queue SSDs
Saugata Ghose, Special Faculty Systems Scientist, Carnegie-Mellon University

Open Source Software for Managing Performance Analysis of Flash Storage
Shing Lee, R&D Senior Manager, ADATA Technology

Session Description:
Testing is essential to ensuring that flash devices will meet system requirements. It may involve modeling as well as testing and must include a wide variety of effects. It also depends on the type of flash devices being tested, which may range from cards through entire arrays. It must reflect real-world conditions and include the effects of both hardware and software.
About the Organizer/Moderator:
Marilyn Kushnick is a Research and Development Engineer at Advantest, where she is currently an RTL designer for FPGAs in testers. She specializes in low power mode testing of SSD drives. She has experience in both the hardware and software sides of test equipment, having worked on embedded Linux drivers, tester controller software and GUI, and test programs. She holds a BS in electrical and computer engineering from UCLA.

Thursday, August 9th
8:30-10:50 AM
COMP-301-1: Increasing Performance by Moving Compute Closer to Data (Computational Storage Track Track)
Chairperson: Jim Handy, Director/Chief Analyst, Objective Analysis

Organizer: Stephen Bates, CTO, Eideticom

Paper Presenters:
Unleashing Data-Driven Applications with Computational Storage
Thad Omura, EVP Marketing, ScaleFlux

A Scalable Architecture for Image Similarity Search using Intelligent Storage
Richard Mataya, Executive VP Products/Co-Founder, NGD Systems

Bringing Intelligence to Enterprise Storage Drives
Neil Werdmuller, Director, Storage Solutions, Arm Holdings

Adding FPGA-based Acceleration to Flash Memory for Real-Time Analytics
HK Verma, Principal Engineer, Xilinx

Scalable Data Pipeline over Shared NVMe
Kais Belgaied, Storage & Servers Division CTO, Sanmina

Intelligent SSDs Can Handle a Larger Computing Load at the Edge
Noam Mizrahi, VP Technology, CTO Office, Marvell

Session Description:
As big data begins to dominate applications, far too much time is spent simply moving large datasets from one place to another. Data transfers waste central CPU cycles and clog networks. An obvious solution is to move compute closer to the data in what is called "computational storage". The end result is to reduce bus and network traffic, as well as limiting it to results rather than raw inputs. Computational storage devices are now widely available, and can be particularly useful in such applications as video or image processing, database searches, and IoT.
About the Organizer/Moderator:
Jim Handy is General Director of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy is the author of the Chip Talk blog for Forbes online and writes two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Stephen Bates is CTO at Eideticom, a developer of leading edge storage, compute, and applications for programmable platforms in the cloud or at the network edge. He focuses on applying emerging technologies such as NVMe, RDMA, new non-volatile memories, and advanced programmable logic to create complex storage and communications systems. He has combined several such technologies to implement computational storage that offers performance well above today’s production systems. He is also an active contributor to the Linux kernel. Before joining Eideticom, he worked in the CTO office at PMC-Sierra and was a professor of computer engineering at the University of Alberta. He holds a PhD in signal processing from the University of Edinburgh, Scotland. He has given presentations at Storage Developer Conference and at past Flash Memory Summits.

Thursday, August 9th
8:30-10:50 AM
CTRL-301-1: Flash Controller Design Options (Controllers Track Track)
Chairperson: Roman Pletka, Research Staff Member, IBM Zurich Research Lab

Organizer: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Presenters:
Adapting Controllers for STT-MRAM
Joe OHare, Marketing Director, Everspin

A New Erasure Pointer Generation Scheme for Storage Class Memory
Mai Ghaly, Sr. Technologist, WDC

Layer-by-layer Adaptively Optimized ECC for NAND Flash SSD Storing CNN Weights
Keita Mizushina, Student, Chuo University

Self-Adaptive NAND Flash DSP
Wei Xu, Vice President, Maxio Technology

Adapting STAR Code for Non-Volatile Memory Systems
Rui Chen, PhD student, Wayne State University

A New Circuit Level Controllable SSD Emulation System
Lihua Sun, R&D Chief Architect, UNIC

Session Description:
NAND flash technology has produced several breakthroughs in the last few years which have consolidated its position as the leading type of nonvolatile memory. What's in store now? Will there be new types of 3D technology? How about variations on QLC providing even more levels in a cell? How about new approaches to scaling cells that could provide higher performance and less wear? There are many possibilities out there, but the investment is high and the simple concepts have already been developed. Obviously, the lack of any major breakthrough would help open the door to other non-volatile technologies such as MRAM, RRAM, 3D XPoint, and memristors.
About the Organizer/Moderator:
Roman Pletka is a research staff member for cloud storage and security at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He has published 20 articles and obtained over 50 patents in security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over ten years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).

Roman Pletka is a research staff member for cloud storage and security at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He has published 20 articles and obtained over 50 patents in security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He has over ten years experience in storage systems research. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne).

Thursday, August 9th
8:30-10:50 AM
NVME-301-1: PCIe/NVMe Technology Update (NVMe Track Track)
Organizer + Chairperson: Rakesh Cheerla, Solution Planner, Intel

Co-Organizer + Co-Chair: Deepankar Das, CTO, Sureline Systems

Paper Presenters:
PCI Express: What's Next for Flash Storage
Justin Wenck, Senior Technical Marketing Engineer, Datacenter SSD Technical Marketing Group, Intel Corporation, PCI-SIG

Boost Application Performance with Persistent Memory Region (PMR) Technology
Chander Chadha, Sr Product Marketing Manager, Toshiba

Fast MRAM Write Buffers Make I/O Determinism Practical
Rizwan Ahmed, VP Corporate Marketing, Everspin

NVMe-oF Aware Filesystem Accelerates Machine Learning Workloads
Liran Zvibel, CTO And Co-Founder, WekaIO

Using PCIe Fabric Switches in an NVMe-Based Storage System
Brian Pan, General Manager, H3 Platform

Session Description:
PCIe SSDs have rapidly emerged as the devices of choice in the enterprise because of their high speed, well-understood and widely used interface, and extensive support from major vendors. The NVMe standard for storage operations over PCIe offers a base platform comparable to those available for disk interfaces such as SAS and SATA. A further step in its acceptance is the development of a wide variety of added facilities. They include more efficient I/O frameworks (typically open-source), solutions for performance and power tradeoffs, ways to handle latency problems, and specially designed software such as file systems. Obviously, such added facilities grow the PCIe/NVMe ecosystem, further encouraging developers to use it in their storage systems.
About the Organizer/Moderator:
Rakesh is a Senior Product Manager for Storage Solutions at Xilinx, where he manages the product life cycle, key customer accounts, and customer deliverables. He has created a new product line to address cloud and datacenter markets, defined new product features based on customer inputs, expanded the addressable market, and driven strategic investments. He focuses on understanding customer needs, developing innovative solutions, and applying his experience in product management and engineering to meet requirements in the cloud, datacenter, telecom, and enterprise markets. Before joining Xilinx, he held management positions at CNEX Laboratories, SMART Modular Technologies, LSI, and Infineta. He has given presentations at past Flash Memory Summits and has also served as a session organizer and chairperson. He is also the co-author of a publication on NV-DIMMs. He earned an MSEE from Arizona State University and an MBA from University of Calfiornia at Berkeley.

Deepankar Das is CTO of Sureline Systems, driving the leading edge in application mobility to allow machines, VMs, and applications to move seamlessly between physical, virtual, and cloud infrastructure. Before joining Sureline, he was Head of Engineering for the EMC Data Domain file system where he delivered the next generation Data Domain Data Protection in the Cloud products. He was previously Head of Software Engineering at MRAM startup Avalanche Technology, where he was in charge of creating software for a super-high-performance all-flash storage array, including Block/File Storage, Kernel/ Platform, HA/Clustering, Flash Management, SSD Firmware, and GUI. He has also been Head of Software Engineering at Violin Memory, where he was engineering leader for the overall Violin Software, including high performance vMOS stack, Violin-Symantec Data Management stack, OEM/Platform software, Target Device Drivers, Violin Memory Array Device Drivers, Virtualization, User Interface, and Release Engineering. He has also worked for EMC, Panasas, and Sun Microsystems. He earned a Master’s degree in computer science from Andhra University (India).

Thursday, August 9th
8:30-10:50 AM
NVMF-301-1: Exploring NVMe-oF Designs, Architectures, and Acceleration Options (NVMe-over-Fabrics (NVMe-oF) Track Track)
Organizer + Speaker: Muli Ben Yehuda, CTO and Co-Founder, Lightbits Labs

Organizer + Chairperson: John Kim, Director Storage Marketing, Mellanox

Paper Presenters:
NVMe/TCP Is the Best Way to Disaggregate Flash Storage
Muli Ben Yehuda, CTO and Co-Founder, Lightbits Labs

FPGA Accelerator Disaggregation using NVMe-over-Fabrics
Andrew Maier, Software Engineer, Eideticom

Optimizing NVMe-over-Fabric Targets using Offload, Peer-2-Peer and NVMe CMBs
Stephen Bates, CTO, Eideticom

Accelerating NVMe over Fabrics with Hardware Offloads at 100Gb/s and Beyond
Idan Burstein, Staff Silicon Architect, Mellanox

Scale-Out Architecture Using SSD Attached NVMe-oF Controllers
Shahar Noy, Sr Director Product Marketing, Marvell

How are you going to manage disaggregated NVMe-oF storage?
Barrett Edwards, Director of Product Management, Western Digital

Enabling Smart NVMe-Based Storage Solutions with FPGAs
Deboleena Sakalley, Principal Engineer, Xilinx

Developing Powerful JBOFs with NVMe-oF
Patrice Couvert, Product Manger, Kalray

Enabling Scalable Ethernet JBOF with a Native NVMe-oF SSD
Shingo Tanaka, Chief Specialist, Toshiba Memory Corporation

Session Description:
NVM Express over Fabrics (NVMe-oF) enables users to connect remote subsystems with a flash appliance to achieve faster application response times and better scalability across virtual data centers. NVMe over fabrics offers high transfer speeds, low latency, full standardization, and access to a large ecosystem. Data centers can employ it to get higher utilization, huge performance benefits, and high levels of scalability over hundreds or thousands or local and remote SSDs. It is thus well-suited to large sites such as clouds, megawebsites, and hyperconverged data centers.
About the Organizer/Moderator:
Muli Ben-Yehuda is the co-founder and CTO of Lightbits Labs, a startup focused on developing cloud infrastructure including networked storage. He was previously Chief Scientist at Stratoscale, where he helped develop software that provides AWS-like features in private clouds, including block and object storage and database-as-a-service. He has also been a researcher and master inventor at IBM, where he was instrumental in developing hypervisor support for zero-cost high-speed I/O: all of the benefits of virtualized I/O with none of the overhead. He is widely recognized as an expert in machine and I/O virtualization and has given talks at many conferences, workshops, and universities, including OSDI (where he received the best paper award), ASPLOS, EuroSys, SYSTOR, VEE, Linux OLS, and FAST. He holds an MSc in Computer Science (summa cum laude) from the Technion (Israel Institute of Technology) and a BA (cum laude) from the Open University of Israel.

John F. Kim is Director of Storage Marketing at Mellanox Technologies, where he helps storage customers and vendors benefit from high performance interconnects and smart offloads, including RDMA (Remote Direct Memory Access). He is a frequent conference participant, including several past Flash Memory Summits, and a frequent blogger on storage and networking topics. He is also chair of the Ethernet Storage Forum. Before joining Mellanox, he created storage solutions and alliances at NetApp and EMC. He has a BA from Harvard University. Follow him on Twitter: @Tier1Storage

Thursday, August 9th
9:45-10:50 AM
BMKT-301B-1: VC Forum (Business/Marketing Track Track)
Organizer + Chairperson: Wayne Rickard, Advisor, Radian Memory Systems

Panel Members:
Panelist: Stephen Socolof, Managing Partner, Tech Council Ventures

Panelist: Pete Pappanastos, Consultant, Vonzos Partners

Panelist: Gaurav Tewari, Managing Director, Citigroup Ventures

Session Description:
The flash memory area is bursting out all over with many startups and high-priced acquisitions. What are the short-term and long-term investment prospects? What are VCs looking for in funding flash storage companies and what do they think will be the key factors in achieving success? Is there enough room for all the current flash storage companies? Do the current and projected revenues justify the valuations? Which companies are most likely to succeed? When (if ever) will MRAM, RRAM, and other alternative NVM technologies be ready for prime time? What effect will the current industry storage industry slowdown have? How do such current hot topics as NVMe (and NVMe over fabrics), persistent memory, NVDIMM, and 3D XPoint? look as investment prospects?
About the Organizer/Moderator:
Wayne Rickard is VP of Business Development at Radian Memory Systems. Prior to taking on this role, Wayne was Radian’s first advisor and helped build out the company’s extended leadership team and strategic initiatives. Wayne has been a pioneer in storage networking, working hands on with the early versions of fibre channel and initiating standardization efforts through industry consortiums such as SNIA and FCIA. He was Co-Founder and held VP of Engineering and CTO roles at Gadzoox Networks, an early leader in fibre channel SAN switches. As a Director of Engineering at Emulex, Wayne led an Advanced Technology group that developed the industry’s first fibre channel HBA. He has held VP and division Chief Technologist positions at Seagate and been an Advisory Board member at PMC Sierra.

Thursday, August 9th
9:45-10:50 AM
ENAP-301B-1: How Flash Will Transform Enterprise Applications (Enterprise Applications Track Track)
Chairperson: Marc Staimer, President, Dragon Slayer Consulting

Organizer: Tom Burniece, President, Burniece Consulting Services

Paper Presenters:
Session Description:
Flash memory has already increased the performance of enterprise applications tremendously. However, we have just begun to see the long-term effects. Flash will find even more uses with all-flash arrays dominating local storage, server-side and storage-side caches providing higher performance, and even cold storage moving to flash rather than disk or tape. Real-time analytics will be a key area of interest with both computational performance and access to big data being essential. New developments such as flash on the memory bus and persistent and storage-class memory will maker flash even more important. Data centers will need to take full advantage of flash memory at every level ? in computers, in servers, in networks, and in storage systems.
About the Organizer/Moderator:
Marc Staimer, as President and CDS of the 20-year-old Dragon Slayer Consulting business with 38 years in the industry. He is well known for his in-depth and keen understanding of user problems, especially with storage, networking, applications, cloud services, data protection, and virtualization. Marc has published thousands of technology articles and tips from the user perspective for internationally renowned online trades including many of TechTarget’s Searchxxx.com websites and Network Computing and GigaOM. Marc has additionally delivered hundreds of white papers, webinars, and seminars to many well-known industry giants such as: Brocade, Cisco, DELL, EMC, Emulex (Avago), HDS, HPE, LSI (Avago), Mellanox, NEC, NetApp, Oracle, QLogic, SanDisk, and Western Digital. He has additionally provided similar services to smaller, less well-known vendors/startups including: Asigra, Cloudtenna, Clustrix, Condusiv, DH2i, Diablo, FalconStor, Gridstore, Nexenta, Neuxpower, NetEx, NoviFlow, Pavilion Data, Permabit, Qumulo, SBDS, StorONE, Tegile, and many more. His speaking engagements are always well attended, often standing room only, because of the pragmatic, immediately useful information provided

Tom Burniece is an independent business consultant with over 30 years of senior management experience in the networking and storage markets. He specializes in strategy formulation, business development, marketing, and due diligence. He has worked with well over 50 companies from unfunded startups to large public corporations, including venture and private equity firms. He is a highly experienced CEO and board member and has been a general manager with profit and loss responsibility for a billion-dollar division of Digital Equipment. Before becoming an independent consultant, he was also Chairman of Ciprico and a senior executive at Maxtor and Control Data. He holds a BEE from the University of Minnesota and an MSEE from Arizona State University. He is also a graduate of MIT’s Sloan Senior Executive Program.

Thursday, August 9th
9:45-10:50 AM
FNET-301B-1: Networking Flash with PCIe and InfiniBand (Flash Storage Networking Track)
Chairperson: Chris DePuy, Research Analyst/Co-Founder, 650 Group

Organizer: Rob Davis, VP Storage Technology, Mellanox

Paper Presenters:
PCIe Networked Flash Storage
Peter Onufryk, Fellow Data Center Solutions BU, NVM Express

InfiniBand Networked Flash Storage
Motti Beck, Director Enterprise Market Develop, Mellanox

Session Description:
PCIe and InfiniBand are popular networking technologies that provide lower latency and higher bandwidth than Ethernet or Fibre Channel. Either technology can be used to share flash storage among multiple compute nodes, allowing them to maximize utilization and perform system-wide operations such as clustering and failover. If an application (such as high-performance computing, compute storage disaggregation, or back end scale out) needs higher throughput or lower latency than common versions offer, higher-speed versions are available, as are low-latency extensions such as NVMe over Fabrics (NVME-of), Remote Direct Memory Access (RDMA), and iSCSI Extensions for RDMA (iSER) and NTB. Designers must consider many issues, including their familiarity with particular approaches, existing uses, latency and performance requirements, scalability, and ecosystem (including management tools).
About the Organizer/Moderator:
Chris DePuy is Research Analyst/Co-Founder at 650 Group, a leading market intelligence research firm for communications, data center, and cloud markets. He was previously a Vice-President at Dell’Oro Group, responsible for the Carrier IP Telephony, Enterprise Edge, Wireless LAN, Wireless Packet Core, and Storage market research programs. He has over 20 years of financial analysis, business analysis, and engineering experience. He has been a consultant with TS Cap and a research analyst covering software, communications, and Internet with Bowman Capital and Morgan Stanley. He was named the top ranking Equity Research Analyst in the data networking sector by Institutional Investor and Greenwich Research Survey. The co-author of a book, he holds a Masters in engineering from Cornell and a BS in engineering from Union College.

Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 9th
9:45-10:50 AM
HIST-301B-1: Breaking Through Impenetrable Barriers (History Track Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Alan Weissberger, Content Manager, IEEE Communications Society

Paper Presenters:
Breaking through Impenetrable Barriers - The Key to the Evolution of Solid State
Andy Walker, VP of Product, Spin Transfer Technologies

Session Description:
NAND flash is now the dominant semiconductor storage technology. What made it so special and might limit its future at smaller process dimensions (such as 10 or 7 nm)?. The basic underlying concept is tunneling, the passage of electrons through a seemingly impenetrable substrate. Two FMS Lifetime Achievement Award recipients, Eli Harari and Simon Sze, harnessed the effect many years ago and laid the foundation for the mobile data storage revolution. Today it is not only the key to 3D flash, but it is also a basic mechanism in other solid state memory technologies. This talk will describe how tunneling works as well as the origins of current market implementations of NVM. An understanding of tunneling will give designers insight into the advantages and disadvantages of different approaches. It will also help them see which applications make sense, and evaluate the future likelihood of success for candidates in today's world of ever-smaller dimensions.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Alan Weissberger is the Content Manager for the global IEEE ComSoc Community websites (techblog.comsoc.org and community.comsoc.org), Manager and Moderator of the IEEE Member Discussion list, NA Correspondent for the IEEE Global Communications Newsletter, Chairman Emeritus and Advisor to IEEE ComSocSCV. Alan was the founder and past Chairman of the IEEE Silicon Valley Technology History committee. He is an IEEE Sr Life Member who was an adjunct professor at SCU EE Dept and also taught a EE graduate class at UC Berkeley. Mr. Weissberger specializes in telecommunications and enterprise networking technologies, market positioning, competitive analysis and applications as well as intellectual property research. These are reflected in his posts at techblog.comsoc.org.

Thursday, August 9th
9:45-10:50 AM
INVT-301B-1: Big Data Analysis Using Hardware-Accelerated Flash (Enterprise Applications Track Track)
Chairperson: Chanson Lin, Founder/CEO, EmBestor Technology

Organizer: Brian Berg, President, Berg Software Design

Paper Presenters:
Big Data Analysis Using Hardware-Accelerated Flash
SangWoo Jun, Assistant Professor, UC Irvine

Session Description:
Enterprises are currently collecting huge amounts of data which they need to analyze rapidly. Since datasets rapidly exceed the DRAM capacity of even the largest affordable machines, designers need to create storage systems that can approach DRAM performance. A new system architecture achieves the required performance level by using FPGA-based hardware accelerators, large amounts of high-performance flash memory, and cross-layer optimizations. It provides the equivalent of large cluster speed and capabilities for such important applications as graph analytics and database operations (including object-based and NoSQL stores).
About the Organizer/Moderator:
Chanson Lin is the founder/CEO of EmBestor Technology, a company specializing in industrial embedded storage applications. He has over 20 years experience designing NAND flash memory controllers and holds over 100 patents in the area. Before founding EmBestor, he was General Manager of the NAND flash memory controller business unit of ITE Technology, General Manager of USBest, and co-founder of RiCHIP. He has published 17 articles on embedded systems and has given many conference presentations, including several at previous Flash Memory Summits. He earned a PhD in electrical engineering from the National Chiao Tung University (Taiwan) and an MSEE from the National Taiwan University.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Thursday, August 9th
9:45-10:50 AM
INDT-301B-1: CTO Forum (Industry Trends Track Track)
Organizer + Chairperson: Rob Peglar, President, Advanced Computing and Storage

Panel Members:
Panelist: Val Bercovici, CEO, Pencil Data

Panelist: J Metz, Office of the CTO/Board Member, Cisco Systems

Panelist: Stephen Bates, CTO, Eideticom

Panelist: Muli Ben-Yehuda, CTO and Co-Founder, Lightbits Labs

Session Description:
CTOs and their staff do not have an easy life in the flash memory industry. Things are changing rapidly, and the road ahead is almost impossible to discern or understand. So what are these people thinking currently? What do they see as basic trends that will determine the course of nonvolatile memory technology? And what do they think are just transient issues that will soon be forgotten? What prized techniques can they recommend (such as crystal balls, Ouija boards, and tarot cards) for gauging the future?
About the Organizer/Moderator:
Rob Peglar is President of Advanced Computation and Storage, a consulting company. He was previously Sr VP/CTO of Formulus Black (formerly Symbolic IO), where he led development efforts in next-generation software for persistent in-memory computing. Before that, he was VP Advanced Storage at Micron Technology, where he led efforts in advanced storage systems strategy, contributed to the CTO function and executive-level planning with key customers and partners worldwide for Micron’s Storage Business Unit, and defined future storage portfolio offerings. He also has executive experience at EMC Isilon and Xiotech. Mr. Peglar serves on the Board of Directors of the SNIA, is the former co-chair of the SNIA Analytics and Big Data Committee and the SNIA Tutorials, and is the former director of the SNIA Solid State Storage Initiative. He also serves as an advisor to the Flash Memory Summit and is a highly sought-after keynote speaker and panelist at leading storage and computing-related seminars and conferences worldwide. He earned a BS in computer science at Washington University in St. Louis.

Thursday, August 9th
2:10-3:25 PM
CTRL-302A-1: Flash Controller Design Methods (Controllers Track Track)
Chairperson: Ludovic Danjean, Staff Engineer, Seagate

Organizer: Erich Haratsch, Director, Engineering Flash Channel Architecture, Seagate

Paper Presenters:
LDPC Codes Expand Enterprise-Level Reliability
Shiuan Hao Kuo, Supervisor Engineer, Silicon Motion

Optimizing Error Recovery Flows to Minimize SSD Read Latency
Viet Dzung Nguyen, Senior Staff Engineer, Marvell Semiconductor

Take Full Advantage of LDPC Soft Bit Decoding
Licheng Xue, Sr. Staff Engineer, Starblaze

Programmable Storage Controllers Permit Rapid Response to New Technologies
Chris Bergman, Sr Firmware Architect, Burlywood

Session Description:
SSDs are playing a critical role in enterprise applications. Enterprise end users, storage designers, and engineers need to understand how the choices of NAND flash memory and controllers affect performance, endurance, and the resulting applications. This session will give participants important information on new developments in controllers, including programmable devices that increase flexibility and shorten design cycles and approaches that keep error correction from causing major increases in latency.
About the Organizer/Moderator:
Ludovic Danjean received his PhD degree in Electrical and Computer Engineering from the University of Cergy Pontoise, France in 2012 and from the University of Arizona in 2013. His dissertation was focused on low-complexity iterative algorithms for LDPC decoders and for compressed sensing. Dr. Danjean is currently working at Seagate Technology in Paris, France as an SSD Architect which involves the performance modeling and validation as well as the media management features for the current and next generation of 3D-NAND based SSDs.

Erich F. Haratsch is Director of Engineering at Seagate Technology, where he is responsible for the architecture of flash controllers. He leads the development of hardware and firmware features that improve the performance, quality of service, endurance, error correction and media management capabilities of solid-state drives. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in more than one billion chips. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 40 peer-reviewed journal and conference papers, and holds more than 100 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Thursday, August 9th
2:10-3:25 PM
ENST-302A-1: Top 10 Ways to Make Enterprise Storage Meet Performance Goals (Enterprise Storage Track Track)
Organizer + Chairperson: Camberley Bates, Managing Director/Analyst, Evaluator Group

Panel Members:
Panelist: Andy Walls, Fellow/CTO/Chief Architect, IBM

Panelist: Siamak Nazari, Fellow/CTO, HPE

Panelist: Randy Kerns, Senior Strategist, Evaluator Group

Panelist: Dan Cobb, Fellow, Dell EMC

Session Description:
Quite frequently, the wonderful new flash storage system, despite incorporating NVMe, 3D flash, and other advanced technologies, doesn't run fast enough. The customer needs the specified performance for the current environment and the next breakthrough now, if not even sooner! This session will look at the issues facing systems performance and the approaches that might blast through the bottlenecks. We will look at current and future solutions that address demands in data centers, clouds, and research applications. Our storied industry-leading experts will provide the warnings, tips, and insight that will help you deliver on the performance promises of solid state storage. Audience participation is welcomed in the process of devising a top ten list that will make you a superhero!
About the Organizer/Moderator:
Camberley Bates is Managing Director/Analyst at Evaluator Group, a leading analyst firm covering IT infrastructure and services. She has dedicated Evaluator Group to delivering unbiased in-depth research on information management and data storage - and helping customers use that research to develop the infrastructure they need. She is responsible for corporate leadership and coverage of go-to-market and channel strategies. She has over 20 years of executive experience leading sales and marketing teams at VERITAS, GE-Access, EDS, and IBM. Her achievements include developing a new market category at Copan Systems, restructuring channel programs at Veritas, and growing a new division of GE Access from $14 million to $500 million in revenue through a solution-practice methodology. Camberley is a frequent panelist and chairperson at such events as Interop and Flash Memory Summit, as well as being frequently quoted in the trade and technical press. She holds a BS degree in International Business from California State University Long Beach and executive certificates from Wellesley and Wharton School of Business.

Thursday, August 9th
2:10-3:25 PM
FNET-302A-1: Networking Flash Technology Showdown (Flash Storage Networking Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology, Mellanox

Panel Members:
Panelist: Curt Beckmann, Product Architect Nvme Over Fibre Channel, Brocade

Panelist: Peter Onufryk, Fellow Data Center Solutions BU, NVM Express

Panelist: J Metz, Office of the CTO/Board Member, Cisco Systems

Panelist: Motti Beck, Director Enterprise Market Develop, Mellanox

Session Description:
Choosing the right protocol for flash storage networking is a complex business. Ethernet, Fibre Channel, PCI Express, and Infiniband are all in wide use, have large ecosystems, and provide high throughput. All allow systems to share storage readily among multiple compute nodes and perform clustering, failover, and other system-wide operations. So which is best for your situation? Obviously, there are tradeoffs in terms of cost, complexity, speed, and latency. Each interface has its advocates, its favored applications (sweetspots), its technology roadmap, and its drawbacks. As flash storage networking becomes commonplace, designers and managers must make their choices carefully to maximize their investments and avoid long-term problems.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 9th
2:10-3:25 PM
FTEC-302A-1: The Next Great Breakthrough in NAND Flash (Flash Technology Track Track)
Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMD

Chairperson: Bob Witkow, President, Westwood Marketing

Panel Members:
Panelist: Ed Doller, , Micron

Panelist: Jung Yoon, Sr Technical Staff Member - Silicon Technology & Quality, IBM Procurement Engineering

Panelist: Rob Peglar, President, Advanced Computing and Storage

Session Description:
NAND flash technology has produced several recent major breakthroughs, including 3D flash and QLC flash, which have consolidated its position as the leading nonvolatile memory. What?s in store now? Will there be new types of 3D technology? How about variations on QLC providing even more levels in a cell? How about new approaches to scaling cells that could provide higher performance and less wear? There are many possibilities out there, but the required investment is huge, the technology is complex and risky, and the simple concepts have already been developed. Obviously, the lack of a major breakthrough would help open the door to other non-volatile technologies such as MRAM, RRAM, 3D XPoint, and memristors.
About the Organizer/Moderator:
Leah Schoeb currently works at Rubrik as a Master Technologist and brings expertise ranging from cloud infrastructure and virtualization to system and data infrastructure performance. Her latest work with infrastructure optimization and solid state technology. She draws over many years of experience in the computer industry helping systems companies with performance engineering and optimization, market positioning, benchmark evidence creation, and guiding industry standards development for system, virtualized, containerized, and data solutions. Leah has served in several leadership roles for performance architecture for companies, such as, Turbonomic, VMware, Sun Microsystems, Dell, Intel, and Amdahl.

Bob Witkow is President/Principal Consultant at Westwood Marketing, a memory and storage consulting company. He is currently helping companies build roadmaps for NAND and emerging NVM and their place in AI, IoT, and cloud systems. His consulting clients have included such major flash companies as Samsung, where he developed value-add offerings; Intel, where he developed go to market and distribution plans for flash memory; Micron, where he suggested best sales practices that increased product margins by several percent; and Spansion, where he launched the Quad-Bit NOR product. He has also helped startups find funding injections and sell assets. In the legal and financial world, he has testified as an expert witness, advised hedge and mutual funds, and consulted with activist investors. Before founding Westwood Marketing, he had extensive sales and marketing experience with M-Systems, Lexar Media, and SMART Modular Technologies. He has over 20 years’ experience in the flash storage industry and has assisted with strategies and positions that produced returns of millions of dollars. He has been active at Flash Memory Summit for many years as a highly-regarded chairperson and panelist.

Thursday, August 9th
2:10-3:25 PM
INDT-302A-1: New Flash Applications No One Ever Imagined (Industry Trends Track Track)
Chairperson: Gil Russell, Principal Analyst, WebFeet Research

Organizer: Axel Kloth, President/CEO, SSR Labs

Panel Members:
Panelist: Alan Niebel, CEO/Founder, WebFeet Research

Panelist: Michael Kanellos, Technology Analyst, OSIsoft

Panelist: Michael Krause, Lead Architect, Gen Z Consortium

Panelist: Kazunori Nakano, Chief Specialist, Toshiba Japan

Session Description:
Flash memory has opened up new applications even science fiction writers never imagined. Who would have thought 20 years ago that everyone would have a smartphone that was a powerful computer, communications device, and entertainment center in a pocket-sized package? And how about personal fitness trackers, tiny drones, autonomous cars, and SSDs? So what could be the next billion-dollar product category? We’ll hear from candidates and raise other possibilities as well. If something never happens, you didn’t hear about it from us – just fake news you should have recognized! Who ever heard of Palm, Google Glass, and Blackberry anyways? Terrible!
About the Organizer/Moderator:
Gil Russell is Principal Technology Analyst at WebFeet Research, a market research firm focused on memory and storage. Mr. Russell specializes in dynamic and non-volatile memory technologies and their application in memory storage systems. He is the architect of Reduced Latency DRAM (RLDRAM), a widely used high-density, high-performance memory popular in communications networks. Previously, he managed new product introductions and external partnerships at Infineon Technologies, Siemens Microelectronics, Samsung Semiconductor, and NEC. His industry standards and organizations work includes Synchronous DRAM; DDR1; DDR2; DDR3; DDR4; LPDRAM; RDIMM; LRDIMM; RLDRAM; SLDRAM; JEDEC Board Director - JC42/16 Chairs and M11 Memory Steering Committee; and CAB Member – Flash Memory Summit.

Axel is the Founder, President & CEO of Scalable Systems Research Labs (SSRLabs). He is the inventor of SSRLabs' processor and memory architectures. He was a founder, CTO and member of the executive management team of a Silicon Valley startup focused on real-time image and video analysis. At Parimics, he created the underlying architecture for and supervised the implementation of a parallel chipset targeted at image and video analysis in real-time by deploying parallel processors before Intel or even Google had discovered the need to go parallel. Other successes include the turnaround of a company that was considered a $36M loss to investors into a $394M acquisition target within less than a year. Axel convinced the Technical Advisory Board and subsequently the Board of Directors to strategically reorient the company. He was instrumental in designing, implementing and marketing the first CML-type transceivers designed for bulk CMOS, and the first fully functioning combined virtually output queued switch fabric. Axel has over 20 years of experience in high performance computing, networking, fault tolerance, High Availability and low latency switching, as well as experience in architecting, designing and implementing large ASICs. He has been granted 8 U.S. patents in processor architectures, real-time image and video processing and analysis, communications protocols and device architecture. He sits on the Technical Advisory Boards of HotRail, Z-Force - which later became Attune Systems - and 3Tera (acquired by CA). He taught the CTO classes in the Silicon Valley Executive Business Program ("mini-MBA") at the University of California Santa Cruz (UCSC). Axel finished his post-grad studies in physics at University of Kiel in Germany (CAU Kiel), where his diploma thesis covered what has become the basic technology in High Intensity Discharge (HID) automotive headlights.

Thursday, August 9th
2:10-3:25 PM
INVT-302A-1: Effective Use of QLC Flash in Hyperscale Datacenters (High-Performance Computing Applications Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Dave Bursky, Technology Editor, Chip Design Magazine

Paper Presenters:
Effective Use of QLC Flash in Hyperscale Datacenters
Rado Danilak, CEO, Tachyum

Session Description:
QLC flash is much denser and considerably cheaper than TLC flash. However, its endurance is limited to between 150 and 1,000 writes, far below the values for TLC. To take advantage of QLC as primary storage in hyperscale datacenters, its life / endurance must be increased. A novel technique called life-amplification can achieve the endurance required for a datacenter-level storage architecture. Rack-level redundancy must replace today's conventional triple redundancy, or mirrored RAID-6, but without amplifying write operations. The amount of data to be written is reduced by global deduplication, global compression, and pattern removal to reach almost zero overhead for snapshots and clones. The management of hot and cold data must be done in a way to minimize both write amplification and the amount of overprovisioning needed. Implementing such changes will enable QLC flash to reduce storage costs significantly in hyperscale datacenters.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley (SCV) Section, Director and past Chair of the Consultants’ Network of Silicon Valley (IEEE-CNSV), Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for “outstanding service to the Consulting and Electrical Engineering profession,” and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Dave Bursky is the President and Founder of PRN Engineering Services, a Technical Writing and Market Consulting company, Dave has over 40 years experience working as an engineer and editor. In addition to running PRN Engineering, he is also a Contributing Editor for Chip Design Magazine, and from 2006 through early 2011 was the technical editorial manager at Maxim Integrated Products. Prior to Maxim, Dave had over 33 years of experience as an editor, writing for publications such as Electronic Design and EE Times. In 2005 he was inducted into the Communications Society Hall of Fame for Lifetime achievement at the City College of New York. Additionally, in 1988 he was described by an article in the San Jose Mercury News newspaper as one of the 100 most influential people in Silicon Valley. Dave has served on the program committees of numerous IEEE and commercial conferences, and has authored six books on topics ranging from personal computers to semiconductor memories. Dave holds both Bachelor's and Master's degrees in Electrical Engineering from the City College of the City University of New York.

Thursday, August 9th
2:10-3:25 PM
NVMF-302A-1: Ultra-fast NVMe Storage Networks for Next Generation Flash Arrays (NVMe-over-Fabrics (NVMe-oF) Track Track)
Session Sponsor: FCIA (Fibre Channel Industry Association)
Organizer: J Metz, Office of the CTO/Board Member, Cisco Systems

Chairperson: Mark Jones, Director Technical Marketing & Performance, Broadcom

Panel Members:
Panelist: Craig Carlson, Technologist, Marvell

Panelist: Dennis Martin, Sr Analyst, Principled Technologies

Panelist: David Rodgers, Sr Product Marketing Manager, Teledyne LeCroy

Panelist: Rupin Mohan, Director R&D/Board Member, HPE / FCIA

Session Description:
Shared storage is essential for large-scale applications to provide fast access to huge amounts of storage in a cost-effective, scalable way. Fortunately, NVMe can take full advantage of the unique properties of pipeline-rich, random access, memory-based storage arrays. The FCIA panel offers unique insight into how to create powerful flash storage networks, including: - Reference design that shows a simple way to add FC-NVMe to your current infrastructure - Use case focused on how FC-NVMe can help you share an all flash array to speed up an entire range of applications - Description of how to extend Fibre Channel prioritization to provide prioritization for virtualized environments - Discussion of how to take advantage of Fibre Channel Forward Error Correction (FEC) and end-to-end support from purchase through deployment
About the Organizer/Moderator:
J is currently an R&D Engineer for the Office of the CTO for the Compute and Server Group for Cisco Systems, but has a broad and eclectic background of both academic, corporate, and industry experience. He is an award-winning public speaker, author, and contributor to industry trade publications. He has been active in industry standards, with membership on the Board of Directors for the Fibre Channel Industry Association (FCIA), Storage Networking Industry Association (SNIA), and the Non-Volatile Memory Express (NVMe) Promoter’s Board. He received his Ph.D from the University of Georgia.

Mark Jones has worked in the enterprise computing industry since 1984. Currently is the Director of Technical Marketing for Broadcom Inc. Emulex Connectivity Division. Mr. Jones comes to Broadcom via the acquisition of Emulex Corporation in 2015 for which he has worked since 2002. For the 18 years prior he worked as a Strategic Solutions Manager for Burroughs/Unisys. Mr. Jones has a Computer Science degree from the University of Redlands and currently serves as the President of the Fibre Channel Industry Association.

Thursday, August 9th
2:10-5:00 PM
CMOB-302-1: Mobile Applications Reach New Frontiers (Consumer/Mobile Applications Track Track)
Session Sponsor: UFSA
Organizer: HeeChang (Steve) Cho, Chairperson, UFSA Marketing Committee, UFSA

Organizer: Mian Quddus, JEDEC Board Of Directors Member, Samsung

Chairperson: Desi Rhoden, Executive VP, Montage Technology

Panel Members:
Panelist: Mikko Valimaki, CEO, Tuxera

Panelist: Zhineng Fan, Sr Field Applications Engineer,, Amphenol

Panelist: Perry Keller, Program Manager, Standards & Applications, Keysight Technologies

Panelist: Filipe Rios, Project Manager, Phison Electronics

Panelist: Lee Prewitt, Principal Program Manager, Microsoft

Panelist: Robert Hsieh, Product Marketing Director, Silicon Motion

Session Description:
Mobile is everywhere today with billions of cellphones as well as health monitors, drones, wearables, instruments, data collection devices, cameras, tablets, music players, toys, vehicles, and much more. However, users and developers alike want higher data rates, more standardization and interoperability, more powerful protocols, and easier handling of documents, video, images, and other data types. The answer is UFS! Universal Flash Storage (UFS) cards offer new higher levels of performance in a standard form. They can do the job for 4K/8K video, 3D games, virtual and augmented reality, high-resolution cameras, surveillance systems, cloud data storage, and other applications we cannot yet imagine. UFS also has fully documented standards along with a certification program, compatibility tests, strong industry backing, and a large ecosystem of hardware, software, and services suppliers. It is the right memory platform for mobile everywhere, which will connect the whole world and make resources available to everyone at any time.
About the Organizer/Moderator:
Hee Chang (Steve) Cho is a Principal Engineer and Software Architect at Samsung Electronics, where he focuses on standards and the development of firmware, specifications, and IP. He has been Vice-Chair of the JEDEC JC64.1 committee on embedded memory storage and removable memory cards and Marketing Committee Chairperson for UFSA. He holds over 20 patents in storage, security, and memory. He earned his Master’s and Bachelor’s in computer science at KAIST, the Korean Advanced Institute of Science and Technology in Daejong, Korea.

Coming soon..

Desi Rhoden has been a key figure in semiconductor standards for many years. He initiated the spinoff of JEDEC as an independent organization and led the coordination with Chinese organizations and industry, firmly establishing JEDEC as the worldwide leader in semiconductor industry standards. He has been JEDEC’s Chairman of the Board and is currently chairman of the JC-42 Memory Committee. Desi has also helped establish the semiconductor industry as a major worldwide business. He was one of the first to recognize the importance of industry coordination and the building of international relationships, particularly in Asia. His current day job is as Executive Vice President of Montage Technology, a producer of low power, high performance mixed signal devices for data centers and smart entertainment. At Montage, Desi has coordinated business development and professional relationships with all the key players in the memory industry. Montage is now an established leader in memory interface logic and the only vendor with DDR3 and DDR4 full buffer solutions validated by the industry leaders.

Thursday, August 9th
2:10-5:00 PM
NVMF-302-1: NVMe-over-Fabrics Use Cases, Customers and Ecosystems (NVMe-over-Fabrics (NVMe-oF) Track Track)
Organizer + Chairperson: Muli Ben-Yehuda, CTO and Co-Founder, Lightbits Labs

Organizer: John Kim, Director Storage Marketing, Mellanox

Paper Presenters:
State of the Fabric: NVMe-oF Interop Plugfest
Tim Sheehan, Manager Datacenter Technologies, UNH-IOL

Handling Common Challenges When Designing with NVMe-over-Fabrics
Nikhil Jain, Memeber Consulting Staff, Mentor Graphics

Show Me the Money! Measuring the TCO of NVMe-over-Fabric JBOF Systems
Ziv Serlin, VP System Architecture, E8 Storage

NVMe-oF File System Accelerating Machine Learning Workloads
Liran Zvibel, CTO And Co-Founder, WekaIO

Evaluating NVMe Storage over different transports with Pavilion Data Systems
Jeff Sosa, Head of Products, Pavilion Data

Scaling stateful containers for cloud applications with high-performance NVMe-oF
Sudhakar Mungamoori, Director of Storage Solutions, Toshiba Memory America

Venkat Ramakrishnan, , Portworx
Ceph and NVMe-over-Fabric: Fewer Servers and Higher Performance
Taufik Ma, CEO & Co-Founder, Attala Systems

Achieving High Performance and Low Latency with NVMe over TCP/IP
Sagi Grimberg, Principal Architect, Lightbits Labs

Developing Low-Latency Data Services on NVMe-oF Shared Storage
Chaan Beard, Chief Solution Architect, AccelStor

Session Description:
NVM Express over Fabrics (NVMe-oF) enables users to connect remote subsystems with a flash appliance to achieve faster application response times and better scalability across virtual data centers. NVMe over fabrics offers high transfer speeds, low latency, full standardization, and access to a large ecosystem. Data centers can employ it to get higher utilization, huge performance benefits, and high levels of scalability over hundreds or thousands or local and remote SSDs. It is thus well-suited to large sites such as clouds, megawebsites, and hyperconverged data centers.
About the Organizer/Moderator:
Muli Ben-Yehuda is the co-founder and CTO of Lightbits Labs, a startup focused on developing cloud infrastructure including networked storage. He was previously Chief Scientist at Stratoscale, where he helped develop software that provides AWS-like features in private clouds, including block and object storage and database-as-a-service. He has also been a researcher and master inventor at IBM, where he was instrumental in developing hypervisor support for zero-cost high-speed I/O: all of the benefits of virtualized I/O with none of the overhead. He is widely recognized as an expert in machine and I/O virtualization and has given talks at many conferences, workshops, and universities, including OSDI (where he received the best paper award), ASPLOS, EuroSys, SYSTOR, VEE, Linux OLS, and FAST. He holds an MSc in Computer Science (summa cum laude) from the Technion (Israel Institute of Technology) and a BA (cum laude) from the Open University of Israel.

John F. Kim is Director of Storage Marketing at Mellanox Technologies, where he helps storage customers and vendors benefit from high performance interconnects and smart offloads, including RDMA (Remote Direct Memory Access). He is a frequent conference participant, including several past Flash Memory Summits, and a frequent blogger on storage and networking topics. He is also chair of the Ethernet Storage Forum. Before joining Mellanox, he created storage solutions and alliances at NetApp and EMC. He has a BA from Harvard University. Follow him on Twitter: @Tier1Storage

Thursday, August 9th
3:40-5:00 PM
EMBD-302B-1: Flash and the Internet of Things (Embedded Applications Track Track)
Organizer: Tom McCormick, Chief Engineer/Technologist, Swissbit

Organizer + Chairperson: Sanhita Sarkar, Global Director, Analytics Software Development, Western Digital

Paper Presenters:
Computing Storage in the AI IoT Era
Tang Sun, Director, Design Verification, Beijing Starblaze Technology Co. Ltd.

Developing IoT-Based Factory Automation Using F-RAM
Doug Mitchell, Product Marketing Engineer MPS, Cypress Semiconductor

Session Description:
The Internet of Things (IoT) has been described as the largest opportunity of the next decade. But what is IoT? What role does flash memory have in enabling IoT? This session will discuss why the merger of sensors, micro-controllers, and flash memory into a mesh of Things will improve life for all mankind.
About the Organizer/Moderator:
Tom McCormick is currently Chief Engineer/Technologist at Swissbit, where he leads market focused R&D for product development and full life cycle support. He has over twenty years experience designing PC and embedded computer systems, including over fifteen years focused on flash memory product research and development.. His ongoing research is focused on flash memory and next generation non-volatile memory systems for highly reliable storage in embedded applications. He has presented at Flash Memory Summit and the Non-Volatile Memory Workshop, and has published an article on embedded flash in EE Times. He holds a PhD in Computer Engineering from Northeastern University, an MBA and an MS in Computing Engineering from the University of Massachusetts at Lowell, and an MSME and BSME (summa cum laude) from Drexel University.

Sanhita Sarkar is a Global Director Analytics at Western Digital, where she focuses on software design and development of analytical features and solutions spanning edge, data center, data lake, and cloud. She has expertise in key vertical markets such as the Industrial Internet of Things (IIoT), Defense and intelligence, Financial Services, Genomics, and Healthcare. Sanhita previously worked at Teradata, SGI, Oracle, and several startups. She was responsible for overseeing design, development, and delivery of optimized software and solutions involving large memory, scale-up, and scale-out systems. Sanhita has authored four patents, published several papers, and spoken at several conferences. She received her Ph.D in Electrical Engineering and Computer Science from the University of Minnesota, Minneapolis.

Thursday, August 9th
3:40-5:00 PM
FNET-302B-1: Flash Storage Networking (Flash Storage Networking Track)
Organizer: Rob Davis, VP Storage Technology, Mellanox

Chairperson: Anu Murthy, VP Marketing, FADU

Paper Presenters:
Multi-Host Sharing of NVMe Drives and GPUs Using PCIe Fabrics
Vincent Hache, Principal Applications Engineer, Microsemi

Ethernet Offers the Speed and Affordability Required for Storage Networking
David Iles, Senior Director, Ethernet Switching, Mellanox

Session Description:
Flash storage networking is coming into its own as system designers realize the advantages of having large amounts of shared flash available as-needed. However, accessing the shared flash may be relatively slow, particularly if a lot of the data is stored remotely. A high-speed fabric can help. The most popular protocol is Ethernet, since it is reasonably fast, widely available, well-supported, and familiar to most designers and data centers. PCIe is an obvious next step, since it provides better throughput than Ethernet in a common form. However, PCIe was not intended for networking, so there remain issues to be worked out. Designers can expect to see both fabric options in wide use in the coming years.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at Mellanox where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved Mellanox into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generations of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Anu Murthy is Director of Business Development at Seagate Technology, where she focuses on developing new/high-growth businesses, analyzing and segmenting markets, defining new product architectures, and evangelizing new technologies. She was previously Manager Technology Strategy, in which role she focused on creating growth for Seagate’s SSD business. She has also worked at Toshiba, SanDisk, Samsung, and Cypress Semiconductor during her 20+ years in the technology industry. She holds 12 patents and has studied at the University of California Berkeley Haas School of Business.

Thursday, August 9th
3:40-5:00 PM
MRES-302B-1: Top 10 Things You Need to Know about Flash Memory Today (Market Research Track Track)
Organizer + Chairperson: Jean Bozman, VP/Principal Analyst, Hurwitz & Associates

Panel Members:
Panelist: Rakesh Radhakrishnan, Director, Product Management, VMware

Panelist: Jim Handy, Director/Chief Analyst, Objective Analysis

Panelist: Adam Roberts, Independent Consultant, Independent Consultant

Panelist: Rob Peglar, President, Advanced Computing and Storage

Panelist: Marc Staimer, President, Dragon Slayer Consulting

Session Description:
Flash memory has morphed rapidly from an exciting new technology that had to be justified for specific use cases to a standard part of every data center. What other kind of storage would you be buying today? So what do vendors and users alike need to know about flash? Is it the emergence of 3D technology, the rapid rise of the high-speed NVMe standard, the promise of persistent memory (storage at memory speeds), the role of flash in scalable systems such as clouds and megawebsites, new methods for flash storage networking (such as NVMe-oF), ways to make software take advantage of flash memory, or large, hierarchical storage systems that cover everything from high-speed cache to long-term archiving? Our top industry experts will present a few of their own candidates for the "top ten" list. We will then open nominations to the audience and finally vote on the top ten for 2018.
About the Organizer/Moderator:
Jean S. Bozman is Vice President and Principal Analyst at Hurwitz and Associates, where she covers data center infrastructure, cloud infrastructure, server and storage technology, and software-defined infrastructure (SDI). Before joining Hurwitz & Associates in 2016, she was Senior Product Marketing Manager at SanDisk, where she drove the discussion of enterprise workloads. Bozman has more than 20 years of experience covering the worldwide markets for operating environments, servers, and the workloads that run on servers. She was Research Vice President of IDC’s Worldwide Server Group from 2002-2013. She has been widely quoted in the press and in online publications, such as Bloomberg, CNET, eWeek, Reuters and TechTarget. Ms. Bozman holds a B.S. degree from the State University of New York (SUNY) at Stony Brook, and a master's degree from Stanford University