Thursday, August 10th
Thursday, August 10th
8:30-9:35 AM

Open
DRAM-301-1: DRAM System Factors (DRAM Track)
Organizer: Dave Eggleston, Sr Business Development Manager, Microchip Technology

Room: Ballroom E
Paper Presenters:
Addressing Memory Bottleneck with Type 3 Memory Controllers
Ranjit Gupte, Technical Staff Applications Engineer, DCS, Microchip Technology

Fundamentally Understanding and Solving RowHammer
Onur Mutlu, Professor of Computer Science, SAFARI Research Group at ETH Zurich

Breaking the Latency Barrier: HW-SW Co-Design
Durgesh Srivastava, Senior Director, NVIDIA

Securely reducing on-chip RAM requirements for CXL memory controllers
Ariel Sibley, Sr. Technical Staff Firmware Engineer, DCS, Microchip Technology



Session Description:
This session examines a variety of DRAM system factors. CXL memory can provide significant total cost of ownership benefits, but its additional latency can significantly impact performance. The session discusses a proposal to include critical components in the hardware/silicon for monitoring page hotness and assisting in page movement, resulting in faster response times. A paper presentation argues for two major directions to amplify research efforts on a RowHammer widespread system security vulnerability. A presentation explores a method for secure execution of device firmware stored in flash, while keeping on-chip RAM requirements at reasonable levels. CXL memory expansion can greatly improve system performance by reducing the need for data movement between the CPU and other memory subsystems.
About the Organizer/Moderator:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Thursday, August 10th
8:30-9:35 AM

Open
DSEC-301-1: Ensuring Data Security in SSDs (Data Security and Protection Track)
Organizer + Chairperson: Camberley Bates, VP and Practice Lead, Futurum Group

Room: Ballroom A
Paper Presenters:
Future Direction of Cybersecurity for SSDs
David Verburg, System Technical Staff Member, IBM Supply Chain Engineering, IBM

Enhancing Data Protection with Advanced Security Features of PBSSD
SUNGKYU PARK, , Samsung Electronics

Attestation in Client SSDs for Ensuring Data Security
David Yeh, Product Marketing, Silicon Motion

Implementation of IDE in SSD Controllers for Data Centers
Radjendirane Codandaramane, Sr. Manager, Applcations Engineerin, Microchip Technology



Session Description:
Securing Composable Disaggregated Infrastructure with IDE in SSD Controllers for Data Centers requires protection from the origin to the destination of user data. With SSDs transitioning to PCIe Gen5, there is a need for Integrity and Data Encryption support. This presentation covers various security requirements, such as PCIe Link Encryption, authentication mechanisms, and system vendor authentication secure boot methods with configurability options.
About the Organizer/Moderator:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Thursday, August 10th
8:30-9:35 AM

Open
INVT-301-1: Invited Talk - Debendra Das Sharma (Invited Talks Track)
Session Sponsor: UCIe Consortium
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Leah Schoeb, Sr. Developer Relations Manager, AMD

Room: Ballroom C
Paper Presenters:
UCIe™: Building an Open Chiplet Ecosystem
Debendra Das Sharma, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel



Session Description:
UCIe Consortium is creating an open chiplet ecosystem through its die-to-die interconnect standard that offers high-bandwidth, low-latency, power-efficient, and cost-effective connectivity between chiplets. It caters to growing demands of compute, memory, storage, and connectivity across cloud, edge, enterprise, automotive, high-performance computing, and hand-held segments. The presentation will introduce UCIe 1.0 specification features and explore the innovations enabled by UCIe.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Thursday, August 10th
8:30-9:35 AM

Open
NETC-301-1: NVMe-oF Is Mainstream (Networks and Connections Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

Room: Ballroom F
Paper Presenters:
Networked flash storage solutions implemented on DPUs
Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

VMware vSphere NVMe features in 2023 and beyond
Arvind Jagannath, Sr Product Line Manager, VMware

Can NVMe/TCP replace NVMe/Fibre Channel?
Kamal Bakshi, Director Technical Marketing, Cisco

Catch the Wave: Managing NVMe-oF in the Enterprise
Richelle Ahlvers, Storage Technology Enablement Architect, Intel



Session Description:
VMware vSphere NVMe features in 2023 and beyond will focus on current and future support for NVMe drivers and ESXi storage stack, with a focus on NVMe Over Fabrics. DPUs are highlighted as a solution for accelerating, offloading and securing networked flash storage solutions. The Session will also address the debate between NVMe/TCP and NVMe/Fibre Channel, providing in-depth testing data and real network and storage configs. Additionally, the session cover managing NVMe-oF in the enterprise, and update attendees on the latest Swordfish capabilities for managing NVMe and NVMe-oF devices.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 10th
8:30-9:35 AM

Open
SARC-301-1: Computational Storage Killer Apps (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer: Willie Nelson, Technology Enabling Architect, Intel

Organizer + Moderator: JB Baker, VP Marketing, ScaleFlux

Room: Ballroom G
Panel Members:
Panelist: Andy Walls, IBM Fellow, CTO FlashSystem, IBM

Panelist: David McIntyre, Director Product Planning, Samsung Electronics

Panelist: Donpaul Stephens, CEO, AirMettle



Session Description:
Computational Storage has been a hot topic for several years now, with promises of easing datacenter pains by moving compute tasks closer to the data. What's the real status? Where are these benefits being realized by end-users? What challenges have popped up and been overcome (or are still being worked through) to enable deployment? How have the vendor & user perspectives on computational storage evolved? What's next for computational storage? Join this panel of leaders from IBM, Netflix, Samsung, and ScaleFlux to get the answers to these questions and your questions about the computational storage's winding road from concept to broad adoption.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

JB Baker, VP of Product Management & Marketing at ScaleFlux, is a technology business leader with a 20+ year track record of driving top and bottom line growth through new products for enterprise and data center storage. He joined ScaleFlux in 2018 to lead Product Planning & Marketing to expand the capabilities of Computational Storage and its adoption in the marketplace. Prior to ScaleFlux, he held various product management and leadership roles at Intel, LSI, and Seagate.

Thursday, August 10th
8:30-9:35 AM

Open
SOFT-301-1: Virtualization and Orchestration (Software for Storage and Memory Track)
Organizer: Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Room: Ballroom J
Paper Presenters:
Virtualization Technologies for Next Generation Storage Devices
Phil Colline, Senior Principal Architect, Marvell Technology Inc

On-Demand Storage Development Infrastructure orchestration
Vijila Navaraj, , Samsung Electronics

Advancements in Virtualization technology in Cloud Computing SSDs
Douglas Arens, Technical Staff, Applications Engineer, DCS, Microchip Technology

HW Accelerated Key Value as a Service
Andy Tomlin, CEO, QiStor



Session Description:
In the world of engineering, effective infrastructure is key to success. Provisioning deployment, app and cluster deployment, and automated data prediction are vital. Virtualization technology is essential for scalability while SSDs are now more popular for storage. Innovative virtualization techniques and HW Accelerated Key Value storage are the future of managing data centers effectively and with minimal overheads.
About the Organizer/Moderator:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.

Thursday, August 10th
8:30-9:35 AM

Open
SSDS-301-1: The Latest on Form Factors - A Panel Discussion (SSD Technology Track)
Organizer + Moderator: Cameron Brett, Director Marketing Enterprise and Data Center, KIOXIA

Room: Ballroom B
Panel Members:
Panelist: Paul Kaler, Future Storage Architect, HPE

Panelist: Jonmichael Hands, VP Storage, Chia Network

Panelist: Trent Johnson, SSD Hardware Architect, IBM

Panelist: Don Jeanette, Vice President, TrendFocus

Panelist: Bill Lynn, Fellow, Systems Design Engineering, AMD



Session Description:
Discover the latest on E1 and E3 innovations in form factors in this riveting panel discussion. A family of scalable and flexible form factors allows optimized performance for diverse media types on SSDs, increased scalability and cost efficiency in data centers. Join industry experts as they discuss new product and application introductions, while highlighting the latest SNIA specifications.
About the Organizer/Moderator:
Cameron Brett is the Director of Enterprise SSD Marketing at Kioxia, where he manages a team of product line managers to drive product strategy and revenue growth. Cameron has over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies.He is currently the co-chair of the SNIA Solid State Drive Special Interest Group.

Thursday, August 10th
8:30-9:35 AM

Open
TEST-301-1: Performance Analysis (Testing and Performance Track)
Organizer: Marilyn Kushnick, Engineer, Advantest

Room: Ballroom D
Paper Presenters:
Impact of NAND Flash Consistency on Performance and QOS
Shuxun Liu, Senior product Manager, Starblaze Technology

Game of I/Os: Disk Activity in the Real World
Ace Stryker, Product Marketing Lead, Solidigm

Intelligent SSD Performance Anomaly Detection
Vijila Navaraj, , Samsung Electronics

Exploring Performance Paradigm of HMB NVMe SSD's
Pradeep S R, Staff Engineer, Samsung Electronics



Session Description:
The study delves into the Performance Paradigm of HMB NVMe SSD's in the Value SSD segment. It focuses on the Cost to Performance trade-off and identifies optimal tuning of HMB for a given workload. Anomaly Detection and SSD Evaluation are also discussed. Furthermore, the presentation examines the real-world impact of variables like read/write mix, transfer size, and queue depth on storage devices. Finally, the paper explores the significance of NAND flash consistency on enterprise-class SSD Performance and QoS.
About the Organizer/Moderator:
Marilyn Kushnick is a Research and Development Engineer at Advantest, where she is currently an RTL designer for FPGAs in testers. She specializes in low power mode testing of SSD drives. She has experience in both the hardware and software sides of test equipment, having worked on embedded Linux drivers, tester controller software and GUI, and test programs. She holds a BS in electrical and computer engineering from UCLA.

Thursday, August 10th
9:45-10:50 AM

PRO
DRAM-302-1: Composable Memory Systems using CXL (DRAM Track)
Organizer + Moderator: Manoj Wadekar, Hardware System Technologist, Meta

Room: Ballroom E
Panel Members:
Panelist: Durgesh Srivastava, Senior Director, NVIDIA

Panelist: Siamak Tavallaei, CXL™ Consortium President, CXL Consortium

Panelist: Sungwook Ryu, Lab Head, Samsung Electronics

Panelist: Gerry Fan, CEO and Founder, Xconn Technologies

Panelist: Anjaneya (Reddy) Chagam, Chief Software Defined Storage Architect, Intel

Panelist: Samir Rajadnya, Principal Architect, Microsoft



Session Description:
AI/ML, Cache, Database, Data Warehouse and Virtualized servers are driving the need for higher memory capacity and bandwidth. The current memory hierarchy and solutions are limited to CPU-attached memory. However, CXL now opens up new potential “Composable Memory Systems” in the next generation data center solutions. First, we have the potential to dramatically increase memory capacities in some platforms using memory expansion. Second, we can now build TCO-optimized memory tiers. This requires the industry to come together to develop HW/SW co-designed solutions. Panelists will discuss their plans to enable Composable Memory Systems which are driving its future AI/ML and TCO-optimized memory servers.
About the Organizer/Moderator:
Manoj (Meta): Manoj Wadekar is a Hardware Systems Technologist driving storage and memory technology and roadmaps at Meta. Manoj has been designing and building servers, storage, and network solutions for over 30 years. He is leading the Composable Memory Systems group in OCP. Manoj has evangelized Memory and Storage Disaggregation, NVMe over Fabric, Lossless Ethernet (DCB/CEE) in the industry conferences. Before joining Meta, he held senior engineering positions at eBay, QLogic and Intel. TBD (Intel, Microsoft, NVidia, Micron/Samsung etc.)

Thursday, August 10th
9:45-10:50 AM

PRO
DSEC-302-1: Advanced Technologies and Addressing the Cyber Security Challenges (Data Security and Protection Track)
Organizer: Camberley Bates, VP and Practice Lead, Futurum Group

Room: Ballroom A
Paper Presenters:
Securing CXL Memory Devices
Joseph Tinc, Sr. Applications Engineer, Microchip Technology

Platform Resiliency (NIST SP800-193) enabled with Certified Secure Flash
Adrian Cosoroaba, Technical Marketing Manager, Winbond Electronics

Six real world blockchain use cases
Jonmichael Hands, VP Storage, Chia Network

A Moving Target Defense for Data Storage Devices
Don Matthews, President and CEO, NexiTech



Session Description:
Protect your code and data during boot and OTA updates with Certified Secure Flash, which provides NIST SP800-193 guideline compliance through platform firmware protection, detection, and recovery. Explore real-world blockchain uses in creating efficient markets, promoting process integrity, offering digital identification and credentialing, and enabling secure custody and payment systems. Learn how to safeguard against data breaches and tampering by using CXL Integrity and Data Encryption (IDE) and Secure Boot features. Implement Moving Target Defense techniques in data storage devices to increase uncertainty and cost of attack efforts.
About the Organizer/Moderator:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Thursday, August 10th
9:45-10:50 AM

Open
INVT-302-1: Invited Talk - Andy Walls (Invited Talks Track)
Chairperson: Leah Schoeb, Sr. Developer Relations Manager, AMD

Organizer: Brian Berg, President, Berg Software Design

Room: Ballroom C
Paper Presenters:
Smart Ransomware Detection Assistance in SSDs
Andrew Walls, IBM Fellow, CTO FlashSystem, IBM



Session Description:
As ransomware attacks continue to rise, there is a need to identify and recover from these attacks urgently. One innovative approach is to utilize SSDs to detect anomalous behavior that could be due to ransomware. SSDs can spot suspicious data changes and access patterns, allowing for detection with machine learning models for current and future attacks.
About the Organizer/Moderator:
Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Thursday, August 10th
9:45-10:50 AM

PRO
NETC-302-1: Networking Flash for AI and HPC (Networks and Connections Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

Room: Ballroom F
Paper Presenters:
Introducing the Need for NFS-SSD
David Flynn, CEO, Hammerspace

TRUCKS KEEP RIGHT: Maximizing Efficiency with Fibre Channel Virtual Lanes
Nishant Lodha, Director, Emerging Technologies, Marvell

Accelerating Data Movement Between GPUs and Flash Storage or Memory
Kiran Modukuri, Principal Software Engineer - Systems, NVIDIA



Session Description:
This session highlights the latest trends in NVMe-oF to improve connectivity and performance. It explores various architectures of using NVMe over fabric and compares protocols like TCP, Fibre Channel, and RDMA. Additionally, it covers accelerating data movement between GPUs and flash storage or memory and introduces the need for NFS-SSD to make data more usable in decentralized workflows.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 10th
9:45-10:50 AM

PRO
SARC-302-1: Computational Storage Use Cases (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
Computational storage and file system collaboration
Viacheslav Dubeyko, Linux kernel engineer, ByteDance

Hardware-accelerated data integrity check on a CSD
Hermes Costa, Senior Software Engineer, Solidigm

Ceph Enhancements to Handle Computational Storage Using IBM's Flash Core Modules
Mohit Kapur, Senior Engineer, IBM

Novel memory-efficient computer architecture integration in RISC-V with CXL
Peter Marosan, CTO, Blueshift Memory



Session Description:
Computational storage and file system collaboration can improve file system performance by offloading metadata operations to computational storage. Ceph can efficiently handle self-compressing and encrypting drives, like IBM FCM, using computational storage devices (CSDs). Hardware-accelerated data integrity checks on SSDs can significantly improve storage performance and reduce data transfer overhead. A novel memory-efficient computer architecture using a customized RISC-V core and specialized RAM connected with CXL will increase memory bandwidth and improve energy efficiency for various memory-intensive applications.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Thursday, August 10th
9:45-10:50 AM

PRO
SOFT-302-1: Databases and Composable Infrastructure (Software for Storage and Memory Track)
Organizer: Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Room: Ballroom J
Paper Presenters:
Realizing Instant Database Crash Recovery over SSDs with Transparent Compression
Tong Zhang, Chief Scientist, ScaleFlux

Repatriation of IP: New opportunities for the U.S. Memory and Storage Industry
Bill Cory, Regional Vice President, Sales, Flexential

Building High Performant & Scalable Data Infrastructure for Database Deployments
Prasad Venkatachar, Solutions Director, Pliops

Automated File Data Orchestration in a Global Parallel File System
David Flynn, CEO, Hammerspace



Session Description:
In this session, experts will discuss how to minimize overhead on DBAs and Op-Teams and significantly reduce the cost of open-source database deployments in multiple customer engagements. Discover a solution that allows database systems to achieve almost instant crash recovery without sacrificing operational speed performance. Explore the implications of geopolitical challenges, supply chain constraints, and governmental incentives on the memory and storage industry. Lastly, see how it is possible to provide uninterrupted access to data while orchestrating data movement across incompatible storage tiers.
About the Organizer/Moderator:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.

Thursday, August 10th
9:45-10:50 AM

PRO
SSDS-302-1: Form Factors and Innovations (SSD Technology Track)
Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Room: Ballroom B
Paper Presenters:
Unlocking the Power of Cloud Storage/Compute with EDSFF: Benefits & Use Cases
Elsa Assadian, Sr Product Manager, Solidigm

Maximizing EDSFF E3 SSD design
Trent Johnson, SSD Hardware Architect, IBM

Scalable Management of Ethernet-Attached Drives and EBOFs with SNIA Swordfish
Richelle Ahlvers, Storage Technology Enablement Architect, Intel

Best Design practices for PCIe Gen5 Performance Scaling in EDSFF SSDs
York Chen, Senior Enterprise Marketing Manager, Silicon Motion



Session Description:
In this session, experts will discuss how to maximize EDSFF E3 SSD design and overcome challenges of fitting more components on board and finding E3 enclosures; explore how to pack in computational storage components in the E3 1T form factor while maintaining thermal control within the constraints of EDSFF E3 specs; best design practices for PCIe Gen5 performance scaling in EDSFF SSDs; how to maximize IOPs/TB performance by optimizing ASIC, hardware, and firmware design in EDSFF SSDs; how to unlock the power of cloud storage/compute with EDSFF SSDs; and how to perform achieve management of Ethernet-attached drives and EBOFs with SNIA Swordfish.
About the Organizer/Moderator:
Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Thursday, August 10th
9:45-10:50 AM

PRO
TEST-302-1: SSD Verification and Simulation (Testing and Performance Track)
Organizer: Marilyn Kushnick, Engineer, Advantest

Room: Ballroom D
Paper Presenters:
Instruction Accurate FW Simulation on a QEMU-based Simulator
Bruce Cheng, Senior Staff Engineer, Starblaze Technology

Advancing the Verification of SSDs over Fabrics
Dhruv Garg, Verification Engineer, Siemens EDA

Accelerating Verification of CXL-Based Designs
PRASHANT DIXIT, Senior Engineering Manager, Siemens EDA

Client SSD Traps and Pitfalls
Crane Chu, Director, Geng Yun Technology



Session Description:
Navigating the changing landscape of Client SSD design can be challenging, with new technologies like PCIe Gen4 and QLC. That's why proper testing is critical to ensure product quality and project deadlines. This session will discuss testing tools that evaluate SSDs from LFRSP aspects, identifying common pitfalls to help SSD manufacturers and vendors ensure successful product launches.
About the Organizer/Moderator:
Marilyn Kushnick is a Research and Development Engineer at Advantest, where she is currently an RTL designer for FPGAs in testers. She specializes in low power mode testing of SSD drives. She has experience in both the hardware and software sides of test equipment, having worked on embedded Linux drivers, tester controller software and GUI, and test programs. She holds a BS in electrical and computer engineering from UCLA.

Thursday, August 10th
11:00-12:05 PM

Open
ACAD-303-1: DRAM Applications (Academic Track)
Chairperson: Jim Handy, General Director, Objective Analysis

Organizer: Tom Coughlin, President, Coughlin Associates

Room: Ballroom J
Paper Presenters:
pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables
Onur Mutlu, Professor, ETH Zurich and Carnegie Mellon University

Open Source and Easy-to-Use DRAM Testing Infrastructure
Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich

GenPIP: In-Memory Acceleration of Genome Analysis
Haiyu Mao, Postdoc Researcher, ETH Zurich



Session Description:
This session covers the latest research in DRAM applications. Presenters will discuss GenPIP, a method to improve the performance of genome analysis; open source infrastructure DRAM Bender, an easy-to-use testing interface for DDR4 DRAM chips; and DRAM-based PuM pLUTo for low-cost, bulk memory reads for complex operations, reducing energy consumption and outperforming CPU and GPU baselines.
About the Organizer/Moderator:
Jim Handy is President of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy writes the Chip Talk blog for Forbes online and contributes to two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Tom Coughlin, President, Coughlin Associates is a digital storage analyst as well as a business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies. Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in its second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs. Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI, now CMSI), the IEEE, (he is an IEEE President Elect Candidate in 2021, Past Director for IEEE Region 6, Past President of IEEE USA, Past Chair of the IEEE New Initiatives and Public Visibility Committees and active in the Consumer Electronics Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conference (www.storagevisions.com) as well as the Creative Storage Conference (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is a Fellow of the IEEE and a board member of the Consultants Network of Silicon Valley (CNSV)

Thursday, August 10th
11:00-12:05 PM

PRO
DCTR-303-1: Enterprise Storage Part 1 (Data Center Applications Track)
Chairperson: Richelle Ahlvers, Storage Technology Enablement Architect, Intel

Organizer: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology

Room: Ballroom E
Paper Presenters:
NVMe SSDs with RAID for the Data Center: Testing & Performance Results
Thomas Paquette, Senior Vice President and General Manager, GRAID Technology

DPU + CSD: Build Secure and Dependable Data Storage at Lower Cost
Keith McKay, Sr. Director Applications Engineering, ScaleFlux

Balancing conflicting design constraints of GPUs, CPUs, SSDs
Larry Freymuth, Senior Manager of System Validation and Test, Viking Enterprise Solutions

DPU Use case: QLC/PLC adoption using DPU offload.
Tim Lieber, Lead Solution Architect, Kalray



Session Description:
This session discusses how data centers and enterprise customers can exploit the potential performance of their NVMe drives to the maximum – maintaining excellent throughput, while freeing-up CPU resources in a system that is simple to install. It will also examine a number of DPU use cases and explore the challenges faced when adopting QLC NAND, such as limited durability and incompatible workloads. They will discuss how a large QLC Write Indirection Unit (WIU) is coupled with low write endurance, making QLC SSDs incompatible with most filesystems; and how a DPU can perform Write Shaping operations while still exposing standard 4KB Write Indirection Unit to the host.
About the Organizer/Moderator:
Richelle is a Storage Technology Enablement Architect at Intel, where she promotes and drives enablement of new technologies and standards strategies. Richelle has spent over 25 years in Enterprise R&D teams in a variety of technical roles, leading the architecture, design and development of storage array software, storage management software user experience projects including mobility, developing new storage industry categories including SAN management, storage grid and cloud, and storage technology portfolio solutions. Richelle has been engaged with industry standards initiatives for many years and is actively engaged with many groups supporting manageability including SNIA, DMTF, NVMe, OFA and UCIe. She is Vice-Chair of the SNIA Board of Directors, Chair of the Storage Management Initiative, leads the SSM Technical Work Group developing the Swordfish Scalable Storage Management API, and has also served as the SNIA Technical Council Chair and been engaged across a breadth of technologies ranging from storage management to solid state storage, to cloud, to green storage. She also serves on the DMTF Board of Directors as the VP of Finance and Treasurer.

In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Thursday, August 10th
11:00-12:05 PM

PRO
DSEC-303-1: Cyber Security: MFA, X-Ray, and Moving Targets - Oh My! (Data Security and Protection Track)
Chairperson: Troy Hegr, Sr. Manager, Technical Sales, Ontrack

Organizer: Camberley Bates, VP and Practice Lead, Futurum Group

Room: Ballroom A
Paper Presenters:
Phishing-Resistant, Multi-Factor Web Authentication Using Roaming Authenticators
Vishwas Saxena, Technologist, Firmware Engineering, Western Digital

Using X-Ray Technology in Data Recovery
Matthew Burger, Data Recovery Engineer, DriveSavers Data Recovery

Eliminating controller-based reverse-engineering in chip-off data recovery
Robin England, Senior Research and Development Engineer, Ontrack



Session Description:
Eliminating controller-based reverse-engineering in chip-off data recovery is a complex process due to encryption and error correction codes in NAND flash controllers. A novel technique optimizes the interpretation of voltage distribution in NAND flash to recover data in such situations. DriveSavers is also utilizing X-Ray technology in data recovery for diagnostics, evaluation, verification, and R&D. WebAuth is a phishing-resistant multi-factor authentication system that requires additional verification information for user identity. The Roaming Authenticator generates a public key credential registered by the server to provide strong attested public key-based credentials.
About the Organizer/Moderator:
Troy Hegr is a Sr. Manager at Ontrack, the world leader in data recovery, data erasure, and data protection. Mr. Hegr helps facilitate discussion and fosters partnerships in the technical community with leading data storage and computer system designers, SSD manufacturers and industry groups. Mr. Hegr benefits from over 25 years of experience in the data recovery and digital forensics industries and has been a Flash Memory Summit CAB member, session organizer, and presenter for several years. Mr. Hegr is based in the Tampa Bay, Fl. area and has an Electronics Technician degree from DeVry Institute of Technology and holds a certification in project management from the University of Minnesota, Carlson School of Management.

Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Thursday, August 10th
11:00-12:05 PM

Open
INVT-303-1: Invited Talk - Scott Stetzer (Invited Talks Track)
Organizer: Brian Berg, President, Berg Software Design

Chairperson: Leah Schoeb, Sr. Developer Relations Manager, AMD

Room: Ballroom C
Paper Presenters:
A Software-Defined Flash Architecture Tuned for Hyperscale
Scott Stetzer, VP, Memory and Storage Strategy Division, KIOXIA



Session Description:
Hyperscale clouds place unique and extreme demands on flash memory. They require tenant isolation, quality of service, latency predictability, placement control, and maximizing usable capacity in replicated or erasure coded environments. KIOXIA presents a new way to meet these challenges that makes flash memory a software-defined component of the complete hyperscale data center stack. This talk will examine a new flash storage architecture that provides this software-defined view of flash memory, Software-Enabled Flash. We will examine synthetic tests addressing cloud-scale pain points, present results run on the first engineering samples of this new technology, and delve into how the optimized storage stack and hardware capabilities of Software-Enabled Flash help address them.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Thursday, August 10th
11:00-12:05 PM

PRO
NETC-303-1: NVMe Flash Challenges (Networks and Connections Track)
Organizer + Chairperson: Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

Room: Ballroom F
Paper Presenters:
PCIe Gen5 NVMe MR-IOV solution
Brian Pan, General Manager, H3 Platform

Redefining Data Redundancy with RAID Offload
Mahinder Saluja, Director, SSD Strategy, KIOXIA

PCIe Fabrics Advanced Solutions
Chetana Kaushik, Senior Applications Engineer, Microchip Technology

System design challenges and performance impacts on Gen5-based NVMe solutions
Odie Killen, VP Hardware Engineering, Viking Enterprise Solutions



Session Description:
This session focuses on system design challenges and performance impacts for end-to-end Gen5-based NVMe solutions. It will cover power, packaging, signal integrity, and cooling trade-offs, as well as high-level trade-offs on performance and sample solutions. Additionally, addressing power-performance challenges of system data redundancy by offloading compute resources to NVMe controller. The very first PCIe Gen5 NVMe MR-IOV solution in the market will also be discussed, along with PCIe fabrics advanced solutions for high-performance computing and data centers.
About the Organizer/Moderator:
Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Thursday, August 10th
11:00-12:05 PM

PRO
SARC-303-1: Computational Storage Optimization (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
Compression and decompression as a service using CSDs
Vladimir Alves, Director Pathfinding Architecture, Solidigm

Python-Based Application Acceleration Through Computation Storage Drive
Raj kumar Dani, Associate Director, Samsung Electronics

Hybrid Transactional/Analytical Processing over Computational Storage Drives
Tong Zhang, Chief Scientist, ScaleFlux

Effective Resource Utilization with the Hardware Accelerators in SSD Controllers
Ram Edupuganti, Staff Applications Engineer, Microchip Technology



Session Description:
This session will discuss the benefits of using computational storage drives to provide compression and decompression as a service. The NVMe standards workgroup is developing enhancements that will ensure interoperability of CSDs and enable offloading of computing tasks. The session will also explore different approaches to delivering compression and decompression as a service and will discuss the programming model that enables this functionality.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Thursday, August 10th
11:00-12:05 PM

PRO
SARC-303-2: CXL Usage Models (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom B
Paper Presenters:
Data Acceleration Approaches on the CXL Memory
Harry Kim, CPO, MetisX

Providing Capacity & TCO to Applications using VMware Software Memory tiering
Arvind Jagannath, Sr Product Line Manager, VMware

Not a magic wand! Performance considerations for CXL-attached memory
Nishant Lodha, Director, Emerging Technologies, Marvell

CXL Memory Controllers (DRAM)
Tim Symons, Associate Technical Fellow, Microchip Technology

Providing Capacity & TCO to Applications using VMware Software Memory tiering
Sudhir Balasubramanian, Senior Staff Solution Architect & Global Oracle Practice Lead, VMware



Session Description:
This session discusses a variety of CXL usage models. VMware's virtualization platform leverages CXL technology to provide benefits such as TCO reduction, enhanced memory scale, and improved application bandwidth. The software memory tiering feature enables efficient capacity utilization and caters to Oracle's business critical database workloads. Explore data acceleration and intelligent memory structures to enhance CXL based data applications. CXL type-3 DRAM memory controllers enable core memory expansion and enhance memory bandwidth. Factors such as memory capacity and access latency impact CXL-attached memory performance and system architects should carefully optimize capacity expansion, tiering, pooling, and acceleration to achieve optimal performance.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently serves on the SNIA Board of Directors and is the chairman of the CXL Consortium. Jim has over 37 years of experience in the computer industry, holds eight US patents, and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Thursday, August 10th
11:00-12:05 PM

PRO
TEST-303-1: SSD Testing Strategy (Testing and Performance Track)
Organizer: Joseph Chen, VP Engineering, ULINK Technolgy

Room: Ballroom D
Paper Presenters:
NLP based Auto Test Suite Generator (ATSG) for NVMe protocol
Karthik Balan, Associate Director, Samsung Electronics

Ten Years of Testing NVMe Solutions
Carter Snay, Technical Manager, UNH-IOL

Linux Testing of NVMe SSDs with Python and SPDK
Don Matthews, VP of Engineering, High Performance Storage



Session Description:
Over the last 10 years, the NVMe standard has evolved significantly, thanks to the partnership between NVMe and the IOL. Current trends in compliance testing include Performance Characteristics Reporting feature and Dispersed namespaces, with future testing planned for ZNS over Fabrics and Flexible Data Placement. For efficient and accurate testing, an NLP-based Auto Test Suite Generator has been developed, while the SPDK and Python allow for highly-customized testing of NVMe SSDs. Lastly, N_Port ID Virtualization presents a challenge in testing that can be overcome with innovative solutions using available tools.
About the Organizer/Moderator:
Joseph Chen is VP of Engineering at Ulink Technology, a supplier of IT storage interface test tools. His focus areas include enterprise HDD/SSD development and qualification, SoC technical management, self-encrypted drives, and industry standards such as T10, IEEE 1667, and the Trusted Computing Group. He was previously Director of Systems Technology and Senior Firmware Manager at Samsung Electronics - SISA. At Samsung, he supervised SAS SSD design and development and managed the self-encrypting drive (SED) development project to produce Opal compliance. He has 30 years experience in the high-technology industry, including positions at Silicon Magic and Cirrus Logic. He holds an MS in computer science from Texas A&M University.

Thursday, August 10th
12:10-1:15 PM

Open
ACAD-304-1: Flash Applications (Academic Track)
Chairperson: Leah Schoeb, Sr. Developer Relations Manager, AMD

Organizer: Tom Coughlin, President, Coughlin Associates

Room: Ballroom J
Paper Presenters:
Sibyl: Data Placement in Hybrid Storage Systems Using Reinforcement Learning
Onur Mutlu, Professor, ETH Zurich and Carnegie Mellon University

Flash-Cosmos: High-Performance and Reliable In-Flash Bulk Bitwise Operations
Rakesh Nadig, Ph.D. Student, SAFARI Research Group at ETH Zurich

Ransomware Defense via File System Forensics and Flash Data Extraction
Josh Dafoe, , Michigan Tech



Session Description:
This session will examine the latest academic work in flash applications. Presenters will discuss: Flash-Cosmos: a high-performance and reliable in-flash bulk bitwise operations technique that accelerates data computation processing inside flash memory; Utilizing Multi-Wordline Sensing and Enhanced SLC-mode Programming mechanisms; Sibyl: an adaptive and extensible data placement technique that uses reinforcement learning for data placement in hybrid storage systems. It observes workload and device features to make system-aware data placement decisions and continuously optimizes its policy. Outperforming the best previous policy by up to 48.2%, Sibyl maximizes storage benefits; BlockFlex: a learning-based storage harvesting framework that enables transparent harvesting of both allocated and unallocated storage for evictable VMs; and FFRecovery: a new ransomware defense strategy that supports fine-grained data recovery by restoring the file system metadata and file data via raw data extraction from the flash translation layer.
About the Organizer/Moderator:
Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Tom Coughlin, President, Coughlin Associates is a digital storage analyst as well as a business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies. Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in its second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs. Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI, now CMSI), the IEEE, (he is an IEEE President Elect Candidate in 2021, Past Director for IEEE Region 6, Past President of IEEE USA, Past Chair of the IEEE New Initiatives and Public Visibility Committees and active in the Consumer Electronics Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conference (www.storagevisions.com) as well as the Creative Storage Conference (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is a Fellow of the IEEE and a board member of the Consultants Network of Silicon Valley (CNSV)

Thursday, August 10th
12:10-1:15 PM

PRO
DCTR-304-1: Enterprise Storage Part 2 (Data Center Applications Track)
Organizer: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology

Room: Ballroom E
Paper Presenters:
CXL Based Storage Use Cases
Brent Yardley, STSM, IBM

PCIeŽ 7.0 Specification: 128 GT/s bandwidth for Future Data-Intensive Markets
Al Yanes, STSM, PCI-SIG

Identifying latency outliers in workload testing
Sayali Shirode, Systems Performance Engineer, Micron Technology

New Paradigms for Data Resilience
Mike Kieran, Product Marketing Manager, Pure Storage



Session Description:
This session discusses a variety of enterprise storage areas, including identifying latency outliers in workload testing; and exploring how IT leaders can transform their data resilience operations to meet today's threats with AI-assisted threat detection, remediation, and recovery. Highlights of the upcoming PCIe 7.0 specification which doubles the data rate of PCIe 6.0 to 128 GT/s and supports PAM4 signaling, Flit-based encoding, and improved power efficiency, will be covered. The session will also delve into how CXL storage use cases, such as dual porting, sharing, and persistence, could benefit and transform highly available storage architectures. It explores how CXL can be utilized alongside NVMe as the next major use case for memory architectures.
About the Organizer/Moderator:
In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Thursday, August 10th
12:10-1:15 PM

PRO
DSEC-304-1: This Data Needs To Be Hidden! (Data Security and Protection Track)
Organizer + Chairperson: Camberley Bates, VP and Practice Lead, Futurum Group

Room: Ballroom A
Paper Presenters:
Encrypted disk design based on NVMe NameSpace
Wang Yilei, VP RD, Starblaze Technology

Memory Centric Deterministic Chaos Data Encryption Solutions
W David Schwaderer, CEO, ShapeShift ™ Ciphers

Data Sanitization Developments and Trends
Paul Suhler, Principal Engineer SSD Standards, KIOXIA

Privacy Preserving Searchable Encryption for Content Index
Vishwas Saxena, Technologist, Firmware Engineering, Western Digital



Session Description:
This session will discuss a variety of methods to keep data hidden, including an encrypted disk design based on NVMe NameSpace; Memory Centric Deterministic Chaos Data Encryption Solutions; Privacy Preserving Searchable Encryption for Content Index; and Data Sanitization Developments and Trends.
About the Organizer/Moderator:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Speaker Bio: W. David Schwaderer is the ShapeShift Ciphers LLC CEO. He has 14 issued and pending patents. David has authored dozens of industry articles and eleven technical books that explain complex technology in approachable ways. He has delivered Erasure Coding seminars at Usenix™ conferences. His October 2007 MIT joint Sloan School of Management and Department of Electrical Engineering conference innovation lecture was selected best in conference. David has a MS in Applied Mathematics from the California Institute of Technology and an MBA from the University of Southern California.

Thursday, August 10th
12:10-1:15 PM

PRO
SARC-304-1: Future of Computational Storage (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
Standardizing Computational Storage
Jason Molgaard, Principal Storage Solutions Architect, Solidigm

Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics
Programming with Computational Storage
Oscar Pinto, Principal Engineer, Samsung Electronics

Does Computational Storage Have a Future?
Scott Shadley, Strategic Planner, Solidigm

Leveraging Computational Storage for Cost Efficiency: TCO Case Study
Jonmichael Hands, VP Storage, Chia Network



Session Description:
This session focuses on the future of computational storage. SNIA and NVMe are actively developing Computational Storage standards. The Computational Storage Technical Work Group in SNIA is enhancing the Architecture and Programming Model and the Computatioinal Storage Application Programming Interface (API). Experts will discuss the current state of the standards and their alignment with NVMe standards.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Thursday, August 10th
12:10-1:15 PM

Open
SARC-304-2: CXL Usage Models Panel (System Architectures Track)
Session Sponsor: SNIA
Organizer + Moderator: Kurtis Bowman, CXL Consortium MWG Co-Chair, CXL Consortium

Room: Ballroom B
Panel Members:
Panelist: Mark Orthodoxou, VP Strategic Marketing, Data Center Products, Rambus

Panelist: Khurram Malik, Director of Product Marketing, Marvell

Panelist: Kapil Sethi, Senior Manager DRAM Product Planning, Samsung Electronics

Panelist: Timothy Pezarro, Senior Manager, Product Marketing, Microchip Technology



Session Description:
The Compute Express Link (CXL) Device Ecosystem and Usage Models - Panel Session will delve into how CXL maintains memory coherency, enabling resource sharing for optimal performance. The CXL 3.0 specification will be discussed, along with the devices currently available and what can be expected in the next year. The panel of experts will explore usage models enabled by CXL's memory pooling and sharing capabilities.
About the Organizer/Moderator:
Kurtis Bowman is the Marketing Working Group Co-Chair of the CXL Consortium and Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Thursday, August 10th
12:10-1:15 PM

Open
SARC-304-3: Computational Storage and AI (System Architectures Track)
Session Sponsor: SNIA
Organizer + Chairperson: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom F
Paper Presenters:
KV-CSD: Accelerating Scientific Data Analytics Using Ordered, Hardware-Accelerat
Qing Zheng, Scientist, Los Alamos National Laboratory

Edge AI: The Future of Smart Devices
Daniel Fan, Flash Product Manager, Innodisk

Does Running Linux on a CSD impact the standards-based approach?
Hermes Costa, Senior Software Engineer, Solidigm

Architecture of a query accelerating KVCSD in a HPC System
Woo Suk Chung, Head of Computational Storage, SK hynix



Session Description:
This session provides some unique perspectives on computational storage architectures and artificial intelligence.
About the Organizer/Moderator:
Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Thursday, August 10th
12:10-1:15 PM

PRO
SSDS-304-1: SSD Performance and Optimization (SSD Technology Track)
Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Chairperson: Shuhei Tanakamaru, Senior Principal Engineer, Marvell Technology Inc

Room: Ballroom C
Paper Presenters:
Navigating SSD Tail Latency: Profiling, Analysis, and Optimization
Guanying Wu, Principal Engineer, Silicon Motion

Low-voltage PLP IC for enterprise SSDs for Reliability and Cost savings
Junguei Park, Principal Analog Design Engineer, FADU

Solid State Active Cooling Chip enables full M.2 PCIe SSD NVMe performance
Seshu Madhavapeddy, CEO, Frore Systems

Will Hard Disk Drives Outlive NAND Flash?
Mats Oberg, Sr. Director, DSP, Marvell



Session Description:
This presentation will introduce a new technological advancement in memory systems, specifically a low-voltage PLP IC for enterprise SSDs. The IC eliminates the need for high-voltage capacitors, which can cause issues with reliability and take up valuable space during integration. Instead, energy is stored in a low voltage charging capacitor, providing cost savings and improved reliability for memory systems.
About the Organizer/Moderator:
Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Shuhei Tanakamaru is a Senior Principal Engineer in the Storage Products Group at Marvell, where he is focused on optimizing SSD architecture, performance, and power. He has a broad experience in the storage field from the NAND flash memory device, SSD controller, to system-level reliability enhancements. He has (co-)authored a book chapter and over 30 peer-reviewed journal and conference papers which have been cited over 600 times. He has also reviewed papers submitted to IEEE journals. He earned master’s and PhD degrees in Electrical Engineering and Information Systems from The University of Tokyo, Japan.

Thursday, August 10th
12:10-1:15 PM

PRO
TEST-304-1: SSD Test and Performance (Testing and Performance Track)
Organizer: Joseph Chen, VP Engineering, ULINK Technolgy

Room: Ballroom D
Paper Presenters:
What Exactly are Low Power States and How Can They Be Tested and Measured?
Anthony Andrews, Senior Softwar Engineer, SerialTek

Challenges to CXL Device Test and Qualification
Justin Treon, Applications Engineer, Advantest

An approach for impact analysis of flash behavior on QoS in DC/Enterprise SSDs
Ravishankar Singh, Staff Engineer, Samsung Electronics

Connecting Performance to Productivity, Revenue, & Cost Savings
Marc Staimer, President, Dragon Slayer Consulting



Session Description:
The SSD Test and Performance session will discuss how to measure low power states of NVMe SSDs for optimal performance and energy efficiency and explore real-world scenarios using three separate tools to test and measure low power states. It will delve into impact analysis of flash behavior on QoS for enterprise/server SSD storage and how to connect performance to productivity, revenue, and cost savings. Finally, the session will discuss solutions for CXL device development and qualification using a CXL 1.1 host.
About the Organizer/Moderator:
Joseph Chen is the CEO of ULINK Technology. He has worked on the design and development of HDD’s and SSD’s supporting a variety of interfaces including NVMe, SATA, and SAS. Joseph worked as the Director of Engineering at Samsung SSD and HDD, Oak Technology, and Cirrus Logic. Joseph Chen leads SATA, SAS, NVMe, and TCG Test Suite development and certification in ULINK. Under his leadership, ULINK has developed the Opal Family Certification Test Suites and has been certified by the TCG SWG as the compliance test lab. In addition, Joseph also lead the ULINK DA Drive Analyzer development and deployment for the AI based disk drive failure prediction services.

Thursday, August 10th
2:30-3:35 PM

Open
SPEC-305-1: AI and the Top 10 FMS Takeaways (Special Sessions Track)
Organizer + Chairperson: Jean S. Bozman, President, Cloud Architects Advisors

Room: Ballroom G
Panel Members:
Panelist: Dr. Sumit Gupta, Sr. Director of Infra Products, Google, Google

Panelist: Chuck Sobey, Chief Scientist, ChannelScience

Panelist: Tom Coughlin, President, Coughlin Associates

Panelist: Willie Nelson, Technology Enabling Architect, Intel

Panelist: Dave Eggleston, Sr Business Development Manager, Microchip Technology

Panelist: Jim Handy, General Director, Objective Analysis



Session Description:
This session will wrap up this year’s conference. It will begin with a special talk by Dr. Sumit Gupta of Google, who brings a deep knowledge of AI and Machine Learning (ML) to his role as Head of Product Management for Google Infrastructure. Gupta previously was Chief AI Strategy Officer and CTO of AI at IBM, and GM of NVIDIA’s AI business and its GPU-Accelerated Data Center. It will then continue with a panel of experts who will take a closer look at AI, including showing how today’s hardware infrastructure can better support important AI areas including GenAI and enterprise AI services using new data storage techniques and architectures. They will provide their top 10 takeaways from all of the tracks in our 3-day conference. FMS attendees will not want to miss this discussion to ensure that they don’t miss any of the major news and developments that “bubbled up” throughout the conference. Participants in this Expert Panel will be: Charles Sobey, FMS Conference Chair and Chief Scientist at Channel Science, Plano, TX Tom Coughlin, FMS Program Chair, IEEE President-Elect, and President of Coughlin Associates, San Jose, CA Willie Nelson, Technology Enabling Manager at Intel Corp., Hillsboro, OR David Eggleston, Sr. Business Development Mgr. of Microchip Licensing at SST, San Jose, CA Jim Handy, President of Objective Analysis, a market-research and consulting firm Jean S. Bozman, President of Cloud Architects, and the Expert Panel moderator After the Expert Panel provides their Top 10 Lists, attendees will be able to ask questions of the panelists. Don’t miss this fun and informative session on Thursday afternoon, Aug. 10, at the conclusion of this year’s conference!
About the Organizer/Moderator:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.