Wednesday, August 9th
Wednesday, August 9th
8:30-9:35 AM

Open
BMKT-201-1: IDC Panel:Current State-Future Direction Storage System Investments (Business Strategies and Memory Markets Track)
Session Sponsor: IDC
Moderator: Carol Sliwa, Research Director, IDC

Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Room: GAMR 1 (Great America Meeting Room 1)
Panel Members:
Panelist: Stephen Foskett, Organizer in Chief, Foskett Services

Panelist: Miroslav Klivansky, Global Practice Leader Analytics/AI, Pure Storage

Panelist: David Flynn, CEO, Hammerspace

Panelist: Rupin Mohan, Sr Director Strategic Planning, HPE



Session Description:
IDC Panel: The current state and future direction of storage system investments for Generative AI and Analytics Workloads Artificial intelligence (AI) has emerged as the most disruptive technology innovation of our lifetime. According to IDC research, global spending on AI is positioned to exceed $301 Billion by 2026. AI unlocks the latent value in data to fast-track innovation and more effective decision making to achieve business results. What are the AI and Big Data Analytic applications fueling customer investments in data storage systems? What does the future hold for AI with the storage solution vendors?
About the Organizer/Moderator:
Carol Sliwa is a Research Director for Storage Systems in IDC's Enterprise Infrastructure Practice. Her core research area spans block, file, and object storage, with a special focus on the storage of unstructured data. With more than 25 years of experience as a technology journalist, including 13 years covering enterprise storage, Carol gained extensive insight into the ways in which the industry has adapted systems over time to address the evolving needs of IT customers.

Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales. He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication. He has served as board member to technology industry associations and event development/professional conference companies.

Wednesday, August 9th
8:30-9:35 AM

Open
DSEC-201-1: Archive Technology (Data Security and Protection Track)
Organizer: Chuck Sobey, Chief Scientist, ChannelScience

Organizer + Moderator: Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA

Room: GAMR 2 (Great America Meeting Room 2)
Paper Presenters:
The New Tape Technology in Cold Data Storage
Alistair Symon, Vice President, Head of Development, IBM

Delivering the Data Factory
Brian Pawlowski, Chief Development Officer, Quantum Corp.

Inside the Cloud: A Deep Dive into Cold Data Archiving
Vikranth Etikyala, Sr. Staff Software Engineer, Fintech SoFi



Session Description:
Discover the innovative and improving world of Tape technology for cold data storage, with a strong case for its resurgence. This session highlights its low total cost of ownership and increased demand in storing larger volumes of data. Discussions of sustainability and new use cases, especially when paired with flash, explore the potential of this aging technology to optimize applications and reduce carbon footprint.
About the Organizer/Moderator:
Chuck Sobey is Conference Chair of Flash Memory Summit (FMS). Under his leadership, FMS has increased its size, scope, and influence worldwide, while navigating the unprecedented effects the pandemic has had on the global events industry. Chuck is a respected memory and storage technology strategist, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging memory and storage technologies and in maximizing their reliability and performance. He uses probability analysis to match a technology’s projected capabilities to an application’s requirements. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording, on which practically all of the hyperscale and cloud services rely. Chuck’s clarity of explanation and extensive experience and industry network make him a sought-after technical and business development consultant. He has taught storage/memory technology seminars around the world. Chuck is also General Chair of SmartNICs Summit, which he is co-developing to support the hyperscale and cloud data center ecosystem. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.

As Head of Tape Evangelism for FUJIFILM Recording Media U.S.A., Inc., Rich is responsible for driving industry awareness and end user understanding of the purpose and value proposition of modern tape technology. Rich joined Fujifilm in 2003 as Director of Product Management, Computer Products Division, where he oversaw marketing of optical, magnetic, and flash storage products.

Wednesday, August 9th
8:30-9:35 AM

Open
INDA-201-1: Space Panel Part 1 (Industry Applications Track)
Chairperson + Speaker: Thomas Boone, Senior Technologist, Western Digital

Organizer: Andy Marken, President, Marken Communications

Room: Ballroom J
Panel Members:
Panelist: Dr. Mark Fernandez, Chief Scientist, Space Technologies and Solutions, HPE

Panelist: Crystal Chang, Senior Manager, ATP Electronics

Panelist: Jean Yang Scharlotta, Senior Microelectronics Specialist/Group Supervisor, Jet Propulsion Laboratory

Panelist: Rafi Some, Principal, RSCK Consulting



Session Description:
NAND storage is being used in LEO satellites and CubeSats to store data for communication and earth observation. National Central University Department of Space Science & Engineering is investigating CubeSats for educational and research purposes. Data centers in space are required to meet the increasing demand and advanced sensing and to be resilient to environmental extremes. Emerging storage requirements for deep space missions require commensurately more, highly reliable storage. Robust memory technology is vital for space exploration to enable us to investigate and understand the universe.
About the Organizer/Moderator:
Thomas Boone, Ph.D. is Senior Technologist at Western Digital where he leads defense and aerospace research. With over 20 years’ experience in R&D management and program leadership within the microelectronics and data storage industries, he specifically focuses on HiRel rad-hard microelectronic solutions for defense and aerospace applications. He has broad experience in technology development, strategic technical resource planning and timeline execution to achieve challenging milestones. He is co-inventor of over 20 issued U.S. patents and co-author of 26 peer-reviewed journal articles. He received his Ph.D. in Applied Physics and Electrical Engineering , MSEE from Purdue University and BSEE University of Texas at Arlington

Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Wednesday, August 9th
8:30-9:35 AM

Open
NVME-201-1: Computational Storage and Subsystem Local Memory (NVM Express Track)
Chairperson + Speaker: Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics

Room: Ballroom F
Paper Presenters:
Computational Storage & Subsystem Local Memory
Jason Molgaard, Principal Storage Solutions Architect, Solidigm

Kim Malone, Storage Software Architect, Intel



Session Description:
Learn what is happening in NVM Express to support Computational Storage devices. Computational Storage requires two new command sets: The Computational Programs Command Set and the Subsystem Local Memory Command Set. We will introduce you to how these two command sets work together, the details of each command set, and how they fit within the NVMe I/O Command Set architecture. We will then discuss use cases that show how system performance and efficiency can be improved through the use of NVM Express Computational Storage.
About the Organizer/Moderator:
Bill Martin has over 30 years of experience in the storage industry. He is currently responsible for driving Solid State Storage forward within the industry for Samsung in a variety of standards arenas, e.g,. as Co-Chair of the SNIA Technical Council, Chair of the SCSI T10 Committee, NVMe board member, Author of the NVMe-KV Command Standard, Secretary of ATA T13 Committee, and editor of the SCSI T10 Block Commands document. He has also had extensive experience in the Fibre Channel arena including with the T11 Standards committee and leading FC interoperability events. His employers have included HP, Gadzoox, Brocade, Sierra Logic, Emulex and now Samsung. His industry work has been recognized with numerous awards from INCITS, the FCIA and the SNIA.

Wednesday, August 9th
8:30-9:35 AM

Open
OMEM-201-1: Emerging Memory and Flash Innovations (Other Memory Technologies Track)
Organizer + Instructor: Bill Gervasi, Principal Systems Architect, Discobolus Designs

Room: Ballroom E
Paper Presenters:
Got 175C? Got 48V? Got PMICs? eFlash powers your EVs!
Dave Eggleston, Sr Business Development Manager, Microchip Technology

LPDDR Flash innovation enables real-time performance for next-gen automotive SoC
Sandeep Krishnegowda, Sr Director of Marketing and Applications, Infineon Technologies

Emerging Memory 2023. The Calm after the Storm
mark webb, Analyst, MKW Ventures

The Great Convergence; How CXL and UCIe Challenge the Memory Wall
Bill Gervasi, Principal Systems Architect, Discobolus Designs



Session Description:
Got eFlash? It powers your EVs! The shift to Electric Vehicles is driving semiconductor needs, from 175C Automotive grade 0 requirements, to 48V motor controllers, to high voltage PMICs. Discover why eFlash is the best tech to meet these needs. The Great Convergence of CXL and UCIe is explored to challenge the Memory Wall. LPDDR Flash innovation enables real-time performance for next-gen automotive SoC. Emerging Memory 2023 means the hype has settled, with new memories not expected to make an impact soon. We explore progress in MRAM and ReRAM and show the overall scorecard for all memories.
About the Organizer/Moderator:
Bill Gervasi is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.

Speaker Bio: Bill Gervasi is a long-time prominent leader in the memory business, active since the days of 1Kb DRAMs and EPROMs. As an analyst/consultant, he has led seminars, made conference presentations, written articles, taught courses, acted as an expert witness in major patent cases, and provided comments and quotations for many industry publications. He has been very active in JEDEC, where he currently serves as Vice-Chair of the DRAM modules committee. He has served on the JEDEC Board of Directors and has chaired committees for DRAM parametrics and small form factor memory modules. He worked on the definition of all Double Data Rate SDRAMs since inception. He also helped form the JEDEC committee on SSDs and is active in the definition of NVDIMMs. Before becoming an independent analyst, he spent almost 20 years at Intel as a Systems Hardware Designer and Software Designer. He holds 10 patents in memory and packaging design. He studied computer science at University of Portland and the Oregon Graduate Center.

Wednesday, August 9th
8:30-9:35 AM

Open
SARC-201-1: CXL Tiering (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
CXL 2.0 Composable Memory Implementations
Brian Pan, General Manager, H3 Platform

Software Defined Memory with CXL
Ravi Kiran Gummaluri, Director , CXL System Architecture, Micron Technology

CXL 3.x - Advancing Data Center Architectures with Memory Tiering
Danny Moore, Senior Manager, Product Managment and Strategy, Rambus



Session Description:
In this session, leading experts discuss a variety of CXL tiering methods. CXL 2.0 Composable Memory Implementations explores the use of an external 256-lane CXL switch to form a composable memory cluster. CXL 3.x - Advancing Data Center Architectures with Memory Tiering provides a forward-looking view of data center architectures that includes additional tiers of memory. Software Defined Memory with CXL explains how CXL can expand memory capacity and bandwidth in a cost-effective and power-efficient manner.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Wednesday, August 9th
8:30-9:35 AM

Open
SOFT-201-1: Open Source Innovation Part 1 (Software for Storage and Memory Track)
Organizer: Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Room: Ballroom B
Paper Presenters:
Overview of CXL support in the Linux Kernel
Adam Manzanares, Senior Manager, Samsung Electronics

Enabling data placement in Cachelib using FDP
Arun George, Senior Staff Engineer, Samsung Electronics

CacheLib: Open Source High Performance DRAM/SSD Hybrid Caching Engine
Jaesoo Lee, Software Engineer, Meta



Session Description:
The Linux kernel community is developing CXL support for type 3 devices, which are used for memory expansion of compute platforms. CacheLib is an open source high performance DRAM/SSD hybrid caching engine that powers 100's of services within Meta. Enabling flexible data placement (FDP) using NVMe can help reduce the write amplification factor (WAF) on SSD devices in Cachelib software from Meta. This talk covers integrating FDP to Cachelib to achieve reduced WAF without changes in its core logic or APIs.
About the Organizer/Moderator:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.

Wednesday, August 9th
8:30-9:35 AM

Open
SPOS-201-1: JEDEC Standards-Part 1: Future-forward Insights (Sponsored Sessions Track)
Session Sponsor: JEDEC
Organizer + Chairperson: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology

Room: Ballroom C
Paper Presenters:
JEDEC Standards for the Future
Mian Quddus, JEDEC Board of Directors Chairman and VP Standards and Technology, Samsung, JEDEC

DDR5: High Momentum Standards for the Next Generation of DRAM
Marc Greenberg, , Cadence Design Systems

Breaking Past Expansion Limits: CXL-Attached Memory Standards
Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology

Rita Gupta, Server System Memory, IO and CXL Architect, AMD
MR-DIMM Technology
George Vergis, Senior Principal Engineer, Intel



Session Description:
JEDEC is the global standards organization that leads the development of the industry's memory standards including DRAM and NAND flash. With more than 3,000 volunteers representing over 350 member companies, JEDEC is the key forum where companies come together to decide and define the future for memory. The presentations in this session will provide an overview of the industry's key standards related to DRAM and Flash plus related implications for performance, power, and reliability, and will highlight new technology initiatives important to the industry and emerging trends critical to planning for the future.
About the Organizer/Moderator:
In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Wednesday, August 9th
8:30-9:35 AM

Open
SSDS-201-1: SSD Innovations (SSD Technology Track)
Organizer: Erich Haratsch, Senior Director Architecture, Marvell

Room: Ballroom D
Paper Presenters:
Challenge and Opportunity for PCIe 5.0 SSD
John Li, , DapuStor

DIY SSDs for Cloud Data Centers
Vasanthi Jagatha, Senior Manager, Product Marketing, Marvell

Vertically Integrated High-resilience SSDs Designed for Cloud Computing
Ayberk Ozturk, Director, Microsoft

How New Client Platforms Are Shaping the Evolution of SSDs
Sanjay Subbarao, SSD architect, Solidigm



Session Description:
The rapid pace of PCIe 5.0 is attracting industry attention, with high bandwidth and low latency indicating an opportunity for enterprise SSD companies. However, fully utilizing its potential remains a challenge. Combining PCIe 5.0 SSD's high-speed characteristics with ZNS can further improve SSD performance by reducing write amplification. Microsoft is proactively addressing SSD failure in cloud infrastructure through vertically integrated solutions and essential capabilities. Meanwhile, SSD manufacturers are adapting to new use cases in mobile, gaming, and workstation segments as DIY SSDs become ideal for the diverse storage needs of cloud data centers.
About the Organizer/Moderator:
Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).

Wednesday, August 9th
8:30-9:35 AM

Open
SUST-201-1: Sustainable Data Centers and Energy Efficiency Part 1 (Sustainability Track)
Organizer + Chairperson: Wayne M. Adams, SNIA Chairman Emeritus, SNIA

Room: Ballroom A
Paper Presenters:
Maximizing Energy Efficiency for High Fidelity Storage Platforms
Mike Bennet, Solution Architect, Ampere Computing

Low-Voltage PLP IC for Enterprise SSDs for Reliability and Cost Savings
Junguei Park, Principal Analog Design Engineer, FADU

SNIA Specifications for Energy Efficiency Measurement
Wayne Adams, SNIA Chairman Emeritus, SNIA



Session Description:
Maximizing energy efficiency is crucial in evaluating SSDs, especially amidst a global energy crisis. We must consider the hardware and software driving the IOPS, along with the drive level. In this talk, we discuss techniques for optimizing the host component of the IOPS/Watt metric, highlighting the role of Arm-based CPUs. SNIA Emerald specifications for energy efficiency measurement provide a vendor-neutral foundation for organizations to compare industry options. Finally, low-voltage PLP IC offers cost-effective, compact energy storage for memory systems with improved reliability.
About the Organizer/Moderator:
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.

Wednesday, August 9th
9:45-10:50 am

Open
CRER-202-1: Three Science-Based Strategies to Elevate Your Confidence (Career Strategies Track)
Chairperson: Carol Sliwa, Research Director, IDC

Room: Ballroom D
Paper Presenters:
Boost Your Confidence with Three Science-Based Strategies
Anna Gradie, Confidence Coach, Anna Gradie - Confidence Coach



Session Description:
Does lack of confidence hold you back at work or at home? Do you ever wish you had the confidence to go after what you truly want? The good news is that confidence is a skill you can build. It is the belief in your success that stimulates action. It is your willingness to try. Stop getting in your own way. Learn how you can increase your confidence at any stage of your life by using three science-based strategies. What would be possible in your life if you had more confidence?
About the Organizer/Moderator:
Carol Sliwa is a Research Director for Storage Systems in IDC's Enterprise Infrastructure Practice. Her core research area spans block, file, and object storage, with a special focus on the storage of unstructured data. With more than 25 years of experience as a technology journalist, including 13 years covering enterprise storage, Carol gained extensive insight into the ways in which the industry has adapted systems over time to address the evolving needs of IT customers.

Wednesday, August 9th
9:45-10:50 AM

Open
BMKT-202-1: Market Research Panel (Business Strategies and Memory Markets Track)
Organizer + Moderator: Jean S Bozman, President, Cloud Architects Advisors

Room: GAMR 2 (Great America Meeting Room 2)
Panel Members:
Panelist: Tom Coughlin, President, Coughlin Associates

Panelist: Chris DePuy, Research Analyst/Co-Founder, 650 Group

Panelist: Camberley Bates, VP and Practice Lead, Futurum Group

Panelist: Simone Bertolazzi, Technology and Market Analyst, Yole Dveloppement

Panelist: Jeff Janukowicz, Vice President, IDC



Session Description:
In this session, four highly-regarded analysts will present their views about the state of today’s flash memory market – and what’s ahead for flash technology. Come hear what some of the leading minds of the industry think of the current business – and what they expect the future to bring. You will be able to ask the panel about your top-of-mind issues during the question-and-answer session. Bring your best questions, and participate!!
About the Organizer/Moderator:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.

Wednesday, August 9th
9:45-10:50 AM

Open
DSEC-202-1: Does Your Data Ever Retire - The Truth about Cold Data and Archives (Data Security and Protection Track)
Organizer: Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA

Moderator: John Monroe, , Further Market Research

Room: GAMR 1 (Great America Meeting Room 1)
Panel Members:
Panelist: Gregory Servos, Executive Chairman, Ovation Data

Panelist: Charles Sobey, Chief Scientist, ChannelScience

Panelist: Georg Lauhoff, Hardware Design Engineer, IBM

Panelist: Steffen Hellmold, President, Pithos LLC



Session Description:
As data storage demands continue to skyrocket, companies are facing challenges in preserving and accessing their archives. Hyperscalers are turning to tape technology to back up vast amounts of data, while DNA and optical storage offer potential new solutions. A panel of industry experts will discuss the uses and challenges of archiving, as well as the need for new, more cost-effective storage technologies to manage the explosion of data in the future.
About the Organizer/Moderator:
As Head of Tape Evangelism for FUJIFILM Recording Media U.S.A., Inc., Rich is responsible for driving industry awareness and end user understanding of the purpose and value proposition of modern tape technology. Rich joined Fujifilm in 2003 as Director of Product Management, Computer Products Division, where he oversaw marketing of optical, magnetic, and flash storage products.

John Monroe has been involved with the storage industry for more than 40 years, beginning in 1980. From October 1997 to February 2022, Monroe was a VP Analyst at Gartner. He covered the history and forecasted the future of consumer and enterprise storage markets, from components—the interplay of HDDs, SSDs, and tape—to external controller-based (ECB) networked/fabric-attached storage systems and server direct-attached storage (DAS). From 1990 to 1997, he was the VP of all storage lines at SYNNEX Information Technologies (now TD SYNNEX), a global distribution and manufacturing services firm, responsible for the profitable resale and OEM integration of HDDs, controllers, subsystems, and tape. From 1988 to 1990 he was Director of North American Sales for Kalok Corporation (a startup HDD manufacturer). From 1983 to 1988 he was part owner and general manager of Media Winchester, Ltd., a storage products distributor and integrator which was one of Seagate’s inaugural “SuperVARs.” He began his career in 1980 at Electrolabs, selling ICs, power supplies, cables, monitors, printers, 8-inch floppy disk drives, and 8-inch HDDs (“oddments of all things” related to computing electronics). Unlike most industry analysts, Monroe has had balance-sheet accountability for the stuff that he studies. Monroe earned a BA degree summa cum laude, Phi Beta Kappa from Amherst College in 1976 and a master’s degree in fine arts (MFA) with a merit scholarship from Columbia University in 1980.

Wednesday, August 9th
9:45-10:50 AM

PRO
INDA-202-1: Space Panel Part 2 (Industry Applications Track)
Organizer: Andy Marken, President, Marken Communications

Moderator: Allan McLennan, Chief Executive / Analyst, PADEM Media Group

Room: Ballroom J
Panel Members:
Panelist: Dr. Jon Jenkins, Research Scientist, NASA

Panelist: Paul Chopelas, GM Aerospace & Defense Solutions, Avalanche Technology

Panelist: Mark Katsumura, Scientist, NASA Jet Propulsion Laboratory



Session Description:
Coming soon..
About the Organizer/Moderator:
Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.

Allan McLennan is a Technologist/Analyst of the US based PADEM Media Group, one of the world’s recognized voices* in the advancement of IP (web/broadband/mobile) based television/OTT/VOD, video streaming and AI/ML engagement through connected devices. Allan is an established IP market technology executive in next generation digital media innovations/networks, consumer products and market capitalization deployments worldwide. His current work with global corporations and innovators addresses the deployments and acquisitions across multi-device IP networks, OTT/TV/VOD network programming and multi-platform video distribution. He actively participates in the advancement of data analytics, advanced advertising (ACR, RTB, Programmatic APIs) and the overall revision of the entertainment/media multi-platform video consumption models being explored today. He has participated in the creation/innovation, packaged and/or sold multiple new offerings throughout the world in 17 countries with close to four billion households as both a corporate executive and innovator. Allan has held five patents in targeted advertising and worked with corporations such as Ericsson, Siemens, Microsoft, TIVO, COMCAST, APPLE, Universal, Disney and more involving the advancement of IP/digital media distribution. Additionally, he was the founding AMI divisional president of the US publicly traded entertainment data analytics corporation – RENTRAK (NASDAQ: RENT), serving 100% of the studio and network marketplace.

Wednesday, August 9th
9:45-10:50 AM

Open
NVME-202-1: How to Use an Encryption Key Per IO and Flexible Data Placement (NVM Express Track)
Room: Ballroom F
Paper Presenters:
Flexible Data Placement (FDP) Overview
Chris Sabol, Software Architect, Google

Mike Allison, Sr. Director, Samsung Electronics
Ross Stenfort, , Meta
How to Use an Encryption Key Per IO
Festus Hategekimana, SSD Security Architect, Solidigm



Session Description:
How to use an Encryption Key per IO: The Key Per IO (KPIO) project was a joint initiative between NVM Express and the Trusted Computing Group (TCG) Storage Work Group to define a new KPIO Security Subsystem Class (SSC) under TCG Opal SSC for the NVM Express® (NVMe®) class of storage devices. Self-Encrypting Drives (SED) perform continuous encryption on user-accessible data based on contiguous LBA ranges per namespace. This is done at interface speeds using a small number of keys generated/held in persistent media by the storage device. KPIO allows a large number of encryption keys to be managed and securely downloaded into the NVM subsystem. Encryption of user data then occurs on a per command basis (each command may request to use a different key). These specifications are now available. This presentation will examine how to use this new capability to support use cases such as Support of EU - GDPR Support of data erasure when data is spread over many disks, support of data erasure of data that is mixed with other data needing to be preserved (multitenancy), assigning an encryption key to a single sensitive file or host object. * Flexible Data Placement (FDP) Overview: Please join Mike Allison, the lead author of the technical proposal, as he provides an overview of the ratified NVM Express® (NVMe®) TP4146 FDP and shows how to capitalize on lower WAF, extended endurance, and improved write performance of SSDs. This presentation covers: o How to configure and enable FDP. o How to manage FDP resources across multiple namespaces. o The behavior of writing to the drive by software that does and does not utilize FDP. o The differences between FDP, zoned namespaces, and streams.
About the Organizer/Moderator:
Wednesday, August 9th
9:45-10:50 AM

PRO
OMEM-202-1: Life Beyond Flash (Other Memory Technologies Track)
Organizer + Moderator: Dave Eggleston, Sr Business Development Manager, Microchip Technology

Room: Ballroom E
Paper Presenters:
Emerging Memories – The Next Big Market
Jim Handy, General Director, Objective Analysis

Introducing ULTRARAM: A high-performance, ultra-efficient, non-volatile memory
Manus Hayne, Chief Technology Officer, Quinas Technology

A memory cell based on RKKY interaction
Boris Tankhilevich, CEO, Magtera, Inc.

Feature extraction from disturbed algorithmic patterns for DNA data storage
Suyoun Park, Postdoctoral researcher, Sungkyunkwan University

Stacked Dynamic Flash Memory (DFM) for a High-Density Memory
Koji Sakui, Executive Technical Manager, Unisantis Electronics Singapore Pte Ltd.



Session Description:
This Session discusses a new high-density memory technology called Dynamic Flash Memory (DFM) which can be built using a conventional silicon process. DFM is scalable and has no special material requirements, making it a cost-effective alternative to emerging memory technologies. The proposed double stacked DFM has a variety of structures and eliminates the need for capacitors, resulting in smaller cell sizes. With its potential to outperform DRAM, ULTRARAM is an efficient, non-volatile memory that is poised to become the next big thing in the memory market. Meanwhile, emerging memories are expected to grow into a $44 billion market by 2032, with MRAM, ReRAM, FRAM, and PCM at the forefront of this wave of innovation. Lastly, due to the limited capacity of existing storage devices, researchers are exploring DNA sequencing technology for its high information density as a possible replacement for silicon-based storage devices.
About the Organizer/Moderator:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Wednesday, August 9th
9:45-10:50 AM

PRO
SARC-202-1: CXL RAS (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
Challenges and Opportunities for RAS & ECC in CXL 3.x based Systems:
Larrie Carr, VP Engineering, Rambus

RAS in CXL Memory Controllers
Ranjit Gupte, Technical Staff Applications Engineer, DCS, Microchip Technology

Server-grade RAS and advanced ECC functions for resilient CXL-based systems
Sandeep Dattaprasad, Senior Product Manager, Astera Labs



Session Description:
CXL 3.x based systems bring both challenges and opportunities in RAS and ECC. The CXL standard supports multiple features such as Error Detection, End-to-End protection, and Fault Isolation. These RAS capabilities ensure the robustness of CXL system and provide easy diagnosis and correction of problems. CXL 2.0 also provides advanced ECC capabilities ensuring resilient operation of data-centric workloads. Attendees will gain insights into these RAS capabilities, which are essential for mission-critical server operations.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Wednesday, August 9th
9:45-10:50 AM

PRO
SOFT-202-1: Open Source Innovation Part 2 (Software for Storage and Memory Track)
Organizer: Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Room: Ballroom B
Paper Presenters:
SSDFS + ZNS SSD: Deterministic Architecture Decreasing TCO Cost
Viacheslav Dubeyko, Linux kernel engineer, ByteDance

ZNS in the Cloud with Ceph Crimson
Aravind Ramesh, Principal Engineer, Western Digital

New Developments in Cloud Storage Acceleration Layer (CSAL), an FTL in SPDK
Kapil Karkra, Sr. Principal Engineer, Solidigm



Session Description:
In this session, experts discuss the benefits of the SSDFS file system, designed for prolonging SSD lifetime and guaranteeing strong reliability and stable performance; the Cloud Storage Acceleration Layer (CSAL) implemented at Alibaba that doubled VM density and cut time to insight. project on an open-source software platform that supports RAID5F and SLC; and ZNS in the Cloud with Ceph Crimson.
About the Organizer/Moderator:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.

Wednesday, August 9th
9:45-10:50 AM

Open
SPOS-202-1: JEDEC Standards Part 2: Future-forward Insights (Sponsored Sessions Track)
Session Sponsor: JEDEC
Organizer + Chairperson: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology

Room: Ballroom C
Paper Presenters:
LPDDR5 and Beyond
Hung Vuong, Director of Technical Standards, Qualcomm

Universal Flash Storage (UFS) and Embedded NVM Update
Hung Vuong, Director of Technical Standards, Qualcomm

SSD Updates: Providing New Critical Guidance & Requirements for SSDs to industry
Dave Landsman, Director Standards Group, Western Digital

Introduction to JEDEC's Separate Command Address (SCA) Protocol
JOSE REY DE LUNA, SENIOR MEMBER OF TECHNICAL STAFF NAND APPLICATIONS, Micron Technology



Session Description:
JEDEC is the global standards organization that leads the development of the industry's memory standards including DRAM and NAND flash. With more than 3,000 volunteers representing over 350 member companies, JEDEC is the key forum where companies come together to decide and define the future for memory. The presentations in this session will provide an overview of the industry's key standards related to DRAM and Flash plus related implications for performance, power, and reliability, and will highlight new technology initiatives important to the industry and emerging trends critical to planning for the future.
About the Organizer/Moderator:
In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Wednesday, August 9th
9:45-10:50 AM

PRO
SUST-202-1: Sustainable Data Centers and Energy Efficiency Part 2 (Sustainability Track)
Organizer: Wayne M. Adams, SNIA Chairman Emeritus, SNIA

Chairperson + Speaker: Tejas Chopra, Sr. Software Engineer, Netflix

Room: Ballroom A
Paper Presenters:
Building Sustainable Data Centers with Innovative Technology
Prasad Venkatachar, Solutions Director, Pliops

Beyond Carbon Footprints: The Holistic View of Sustainability in ICT
Jonmichael Hands, VP Storage, Chia Network

Methods to improve system lifecycles to improve Sustainability
Odie Killen, VP Hardware Engineering, Viking Enterprise Solutions

Environmentally-Friendly Storage Architectures
Tejas Chopra, Sr. Software Engineer, Netflix



Session Description:
This series of talks explores various ways to improve the lifecycle of systems to promote sustainability. From balancing trade-offs between operating costs and component life to optimizing key parameters for specific user needs, the talks address the importance of sustainability in modern data centers and the ICT industry at large. The discussions also highlight the role of environmental considerations in storage architecture and provides tools to help developers estimate and mitigate the carbon footprint associated with their code.
About the Organizer/Moderator:
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.

Tejas Chopra is a Sr. Software Engineer at Netflix where he is responsible for building Storage and Transfer services that are media optimized for Netflix Studios Infrastructure. Tejas is an Advisor at Nillion, Inc. and is a National Diversity Council recognized 40 under 40 Technology Leader. He is a TedX and an International Keynote speaker and talks on Cloud Computing, Software Engineering and Blockchain. Tejas has more than a decade of software engineering experience at companies such as Box, Datrium, Samsung, Cadence and Apple. He holds a Masters Degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh.

Wednesday, August 9th
3:30-4:35 PM

Open
BMKT-203-1: Case Studies (Business Strategies and Memory Markets Track)
Organizer + Moderator: Jean S. Bozman, President, Cloud Architects Advisors

Room: Ballroom D
Paper Presenters:
Complex Cloud Environments Demand Storage that Exceeds Expectations
Alex Ivanov, Product Lead, StorPool Storage

SSD Use Case Evolution for Cloud and Enterprise
Tahmid Rahman, Director of Product Marketing, Solidigm

Enabling Performant, dense and reliable Storage for AI & HPC
Tony Afshary, Head of Marketing, Pliops

How to optimize performance for AI Edge computing
Chris Lien, Senior Manager, ATP Electronics

The Apollo Mission repeats itself in the shape of Data Centers in Space
Danny Sabour, VP of Marketing, Avalanche Technology

Economy, geopolitics to dominate 2023 DRAM market game theory
Avril Wu, Senior Research Vice President, TrendForce Corp.



Session Description:
The 2023 DRAM market will be dominated by the economy and geopolitics under a recession. DDR5 and Artificial Intelligence offer growth opportunities despite supply and demand challenges. Complex cloud environments demand storage that meets massive I/O parallelization, reliability, and low latency at scale. AI Edge computing requires optimized performance within limited space, exploring the latest NAND technology, and hardware design consolidation. The SSD market has evolved over the decade, and data integrity must expand beyond design criteria. Pliops offers performant, dense, and reliable storage solutions for AI and HPC for cloud service providers. Furthermore, data centers in space will bring distributed intelligence and storage to enable improved satellite network scalability. Non-volatile storage solutions for data gathered in orbit within New Space's mega constellations will address critical gaps.
About the Organizer/Moderator:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.

Wednesday, August 9th
3:30-4:35 PM

Open
BMKT-203-2: CMO Panel (Business Strategies and Memory Markets Track)
Organizer + Chairperson: Jay Kramer, President, Network Storage Advisors

Room: GAMR 2 (Great America Meeting Room 2)
Panel Members:
Panelist: Sue Ryan, VP Marketing, Frore Systems

Panelist: Rose Hiu, VP Global Marketing and PR, Seagate

Panelist: Molly Presley, SVP Marketing, Hammerspace

Panelist: Eric Herzog, Chief Marketing Officer, Infinidat

Panelist: Natasha Beckley, CMO, Quantum Corp.



Session Description:
CMO Panel - Winning Go to Market Strategies Marketing enterprise flash storage is difficult. The technology is complex and fast-changing, and customers are often very confused and ill-informed. How does one develop a clear message that meets the customer’s needs and offers solid ROI? What role does marketing analytics play in gaining a competitive advantage? Has the marketing playbook really changed? What are the winning strategies with the shift to cloud, hyperconverged architecture, and software defined infrastructure? What magic do successful marketers have up their sleeve as they follow the golden rule of “Know Your Customer”? CMOs will provide insights into the changing customer requirements and how to turn these new customer selection criteria into winning go-to-market strategies.
About the Organizer/Moderator:
Jay Kramer is a world recognized technology consultant, industry analyst and delivering marketing services for the data storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by Hitachi Data Systems), Astute Networks, iStor Networks, Infinity I/O, and Creative Design Solutions (acquired by Seagate). He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Wednesday, August 9th
3:30-4:35 PM

Open
CRER-203-1: Career Strategies and DEI (Career Strategies Track)
Organizer + Moderator: Kara Gustafson, Technical Program Manager, Meta

Room: GAMR 1 (Great America Meeting Room 1)
Panel Members:
Panelist: Stephanie Teng, Sr. Strategic Account Manager, Macronix

Panelist: Yan Li, Engineering VP - Memory Technology, Western Digital

Panelist: David Flynn, CEO, Hammerspace

Panelist: Yang Han, Master Engineer, Broadcom



Session Description:
Explore the myriad of career options in the memory and storage industry at this panel, designed for early-career professionals and those considering a career switch. Industry leaders will share their personal experiences, insights, and struggles in executive positions, management, research, engineering, sales, marketing, and start-ups to help guide attendees on their own path to success.
About the Organizer/Moderator:
As a Technical Program Manager for Meta for the last 8 years, Kara has been rooted in Meta’s infrastructure spanning from hard drive solutions, datacenter operations, audio/video calling infra, and more recently AI/ML hardware. Previously, Kara was a Customer Qualification Engineer and Test Engineer at Western Digital supporting OEM, Cloud, and Distribution Channel customers. Kara is a first generation Filipino American, who has been active in various engineering organization such as Tau Beta Pi and Society of Women Engineers.

Wednesday, August 9th
3:30-4:35 PM

PRO
DRAM-203-1: DRAM Technology (DRAM Track)
Organizer + Moderator: Dave Eggleston, Sr Business Development Manager, Microchip Technology

Room: Ballroom E
Paper Presenters:
Die Stacking with Hybrid Bond Interconnect for DRAM
Laura Mirkarimi, SVP- Engineering, Adeia

High Bandwidth Memory (HBM) Evolution
BELINDA DUBE, COST ANALYST, YOLE GROUP

Memory solutions for secure and sustainable server infrastructure
Ju Jin An, STSM, IBM

DRAM Technology and Process 2023: Current and Future
JEONGDONG CHOE, Senior Technical Fellow, TechInsights



Session Description:
DRAM players are scaling down cell architecture to the 14 nm design rule and developing n+1 and n+2 generations. EUVL adoption will allow further scaling down to single digit nm. Next-gen DRAM comes with EUVL masks, and players are discussing the challenges of DRAM technology and process. Meanwhile, HBM's evolution sees front-end technologies scaling to denser DRAM dies and back-end process enhancing interconnection between chips. There's a need for sustainability, with HKMG and FinFET for improving power reduction. Finally, die stacking with hybrid bonding interconnects and TSVs is discussed for enhanced metrology and reliability performance.
About the Organizer/Moderator:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Wednesday, August 9th
3:30-4:35 PM

PRO
DSEC-203-1: Cyber Resiliency and Systems - What You Don't Know Will Hurt You (Data Security and Protection Track)
Organizer: Camberley Bates, VP and Practice Lead, Futurum Group

Chairperson + Speaker: Krista Macomber, Senior Analyst, Evaluator Group

Room: Ballroom A
Paper Presenters:
Efficient ransomware detection with machine learning in storage systems
Roman Pletka, Research Staff Member, IBM Research

Ransomware Resiliency: A Data-Centric Perspective
Krista Macomber, Senior Analyst, Evaluator Group

Reduce Ransomware Exposure with Comprehensive Storage Cyber Resilience
David Nicholson, Field CTO Americas, Infinidat

Back to Basics: Hardware as the foundation of digital trust
Dr. Erik A. Nilsen, PhD, Chief Technology Strategist, Flexxon



Session Description:
As data storage demands continue to skyrocket, companies are facing challenges in preserving and accessing their archives. Hyperscalers are turning to tape technology to back up vast amounts of data, while DNA and optical storage offer potential new solutions. A panel of industry experts will discuss the uses and challenges of archiving, as well as the need for new, more cost-effective storage technologies to manage the explosion of data in the future.
About the Organizer/Moderator:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Krista covers data protection and security for Evaluator Group. She brings over a decade of experience providing research and advisory services and creating thought leadership content, with a focus on IT infrastructure and data management and protection. Her vantage point spans technology and vendor portfolio developments; customer buying behavior trends; and vendor ecosystems, go-to-market positioning, and business models. Her work has appeared in major publications including eWeek, TechTarget and The Register. Prior to joining Evaluator Group, Krista led the data center practice of analyst firm Technology Business Research. She also created articles, product analyses, and blogs on all things storage and data protection and management for analyst firm Storage Switzerland, and led market intelligence initiatives for media company TechTarget. Krista holds a BA degree in English Journalism with a minor in Business Administration from the University of New Hampshire.

Wednesday, August 9th
3:30-4:35 PM

PRO
FMAR-203-1: QLC High Density Storage (Flash Memory Architectures Track)
Organizer + Chairperson: Brian Berg, President, Berg Software Design

Room: Ballroom J
Paper Presenters:
Achieving Near-SLC Performance for QLC & PLC NAND Flash
Ray Tsay, Co-Founder & VP of Engineering, NEO Semiconductor

Why QLC SSDs Are Ready for the Mainstream
Yuyang Sun, Product Marketing Engineer, Solidigm

QLC: Understanding Its Limitations and Its Critical Areas
Akash Shaw, Staff Engineer, Samsung Electronics



Session Description:
Despite their perceived limitations, QLC SSDs are proving to be a strong fit for mainstream and read-intensive workloads due to advancements in performance, capacity, and endurance. This session will showcase the value of QLC SSDs in terms of TCO, scalability, and sustainability, backed up by real-world case studies. For those looking to implement eco-friendly and cost-effective storage solutions, QLC SSDs are definitely worth considering.
About the Organizer/Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Wednesday, August 9th
3:30-4:35 PM

Open
INDA-203-1: 3D DRAM-Overcoming DRAM Architectural Challenges & Future Direct (Industry Applications Track)
Organizer + Moderator: Jim Handy, General Director, Objective Analysis

Room: Ballroom C
Panel Members:
Panelist: Jian Chen, Visiting Scientist, Stanford University

Panelist: Andy Hsu, Founder & CEO, NEO Semiconductor

Panelist: Tanj Bennett, Chief Scientist, Avant-Gray LLC

Panelist: Keith Jangryul Kim, Senior Memory Architect, NVIDIA



Session Description:
3D DRAM is considered a future growth driver for the semiconductor industry. 3D DRAM represents a way to overcome the physical limitations of DRAM micro-processing. Existing DRAM product development focuses on increasing integration by reducing circuit line widths, but as line widths entered the 10 nm range, physical limitations such as capacitor current leaks and interference increased significantly. In order to prevent this, new materials and equipment such as high dielectric constant (high K) deposition materials and extreme ultraviolet (EUV) equipment were introduced. This session will address discussion of DRAM current challenges, DRAM’s ability to address higher performance and higher capacity and ways to overcome limitations of DRAM with new architectures of 3D DRAM.
About the Organizer/Moderator:
Jim Handy is President of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy writes the Chip Talk blog for Forbes online and contributes to two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Wednesday, August 9th
3:30-4:35 PM

PRO
SARC-203-1: CXL Memory Challenges (System Architectures Track)
Session Sponsor: SNIA
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom G
Paper Presenters:
Advantages of optical CXL for disaggregated compute architectures
Ron Swartzentruber, Director of Engineering, Lightelligence

Data Domain-Specific Architecture with CXL: Breaking the Memory Wall
Jin Kim, CEO, MetisX

Introducing the CXL Computing Cell Architecture
Charles Fan, Co-founder & CEO, MemVerge

Challenges of memory diversity in CXL ecosystem
Sanketh Srinivas, Tech staff Applications Eng, Microchip Technology



Session Description:
Data Domain-Specific Architecture with CXL is a solution to the Memory Wall problem faced by data centers. Optical CXL enables disaggregated compute architectures, providing the ability to connect compute arrays to memory coherently, improving AI model training time. The CXL computing cell architecture enables composable and scalable memory for data-intensive applications, which can be easily deployed and scaled. However, diverse memory media in the CXL ecosystem bring about new hardware and software challenges that need to be addressed to enable a composable server comprising of diverse compute and memory elements.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Wednesday, August 9th
3:30-4:35 PM

PRO
SARC-203-2: UCIe and Chiplets (System Architectures Track)
Session Sponsor: UCIe Consortium
Organizer: Jim Pappas, Director, Technology Initiatives, Intel

Organizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel

Room: Ballroom B
Paper Presenters:
UCIe Manageability and Software
Jerome Glisse, Assistant Account Executive, Nereus Worldwide

Chiplets for MPUs? I'll have some of of that!
Feng Zhou, Technical Staff, Microchip Technology

UCIe Protocol Overview
Swadesh Choudhary, Silicon Architecture Engineer, Intel

Explore the usage models for UCIe technology
Manual Mota, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel



Session Description:
Chiplets for MCUs and MPUs are the cost-effective way to scale digital logic while keeping analog, interface, and eFlash IP on foundry platforms. The speaker will share cutting-edge concepts of chiplets and why it's a better approach for the 100 billion MCUs and MPUs that ship annually. UCIe is introducing an interoperable, multi-vendor ecosystem that provides ubiquitous interconnect at the package level. This presentation will also cover usage models and management software of UCIe technology.
About the Organizer/Moderator:
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Wednesday, August 9th
3:30-4:35 PM

PRO
SUST-203-1: Circular Economy of Storage (Sustainability Track)
Chairperson + Speaker: Jonmichael Hands, VP Storage, Chia Network

Organizer: Wayne M. Adams, SNIA Chairman Emeritus, SNIA

Room: Ballroom F
Paper Presenters:
The Industry and Sustainability Opportunity in Circular Storage
Marshall Chase, Director of Sustainability, Micron Technology

From Cradle to Cradle: A Journey Towards a Circular Economy for Data Storage
Jonmichael Hands, VP Storage, Chia Network

Profiting While Doing Good: How to Harness Circular Storage
Arie van der Hoeven, Principal Project Manager, Seagate



Session Description:
Circular storage presents a massive opportunity for profit and sustainability, but it also comes with risks. With improvements in data purge standards, implementing circular storage models that encourage reuse or reselling of storage hardware can benefit both the environment and the bottom line. The Circular Drive Initiative is working towards creating a standardized grading system for used storage devices, while companies must tackle premature drive destruction and allocate greenhouse gas emissions to a drive's use phase in a circular economy.
About the Organizer/Moderator:
Jonmichael Hands partners with the storage vendors for Chia optimized product development, market modeling, and Chia blockchain integration. Jonmichael spent the last ten years at Intel in the Non-Volatile Memory Solutions group working on product line management, strategic planning, and technical marketing for the Intel data center SSDs. In addition, he served as the chair for NVM Express (NVMe), SNIA (Storage Networking Industry Association) SSD special interest group, and Open Compute Project for open storage hardware innovation. Jonmichael started his storage career at Sun Microsystems designing storage arrays (JBODs) and holds an electrical engineering degree from the Colorado School of Mines.

Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.

Wednesday, August 9th
4:00-6:15 PM

Open
SuperWomen in Flash Peer Exchange (Sponsored Sessions Track)
Session Sponsor: Evaluator Group
Room: Hyatt Regency Santa Clara
Panel Members:


Session Description:
Join leaders in the flash memory industry in an innovative SupeWomen in Flash peer exchange event at FMS 2022, sponsored by Intel, Western Digital, and Evaluator Group. SuperWomen in Flash celebrates the success of women in the flash memory industry and encourages more young women to join this dynamic market. The steadily growing organization is supported by a broad group of women and vendors.
About the Organizer/Moderator:
Wednesday, August 9th
6:30 PM-7:00 PM

Open
Best of Show Awards (Special Sessions Track)
Room: FMS Theatre
Paper Presenters:


Session Description:
The Flash Memory Summit Awards industry recognized awards give winners the opportunity to effectively build their brand and image as an innovative leader in the marketplace. Awards are presented in a variety of categories.
About the Organizer/Moderator: