| Tuesday, August 8th |
Tuesday, August 8th
8:30-9:35 AM
Open | | AIML-101-1: AI Design and Performance (Artificial Intelligence Applications Track) | | Organizer + Chairperson: David McIntyre, Director Product Planning, Samsung Electronics | Room: Ballroom C
| Paper Presenters:
| Optimizing AI Systems with SSDs: Best Practices
John Cronise, Technical Business Development Manager, ATP Electronics, IncIndustrial Flash Storage Design for Industrial AI Systems
Chanson Lin, Founder/CEO, Embestor TechnologyAI Storage Performance using MLPerf Storage
Sujit Somandepalli, Principal Storage Solutions Enginee, Micron TechnologyThe Challenges of Memory in Edge AI
Crystal Chang, Senior Manager, ATP Electronics |
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| Session Description:
| In this session experts will discuss key factors, specifications, and optimization strategies targeted towards elevating industrial AI systems performance; how synthetic performance is insufficient to showcase the true capabilities of AI systems; striking a balance in Edge AI, highlighting the similarities and conflicts between thermal management, power consumption, data processing, and low latency requirements; and optimizing AI systems with SSDs.
| | About the Organizer/Moderator: | David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
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Tuesday, August 8th
8:30-9:35 AM
Open | | BMKT-101-1: Memory Trends (Business Strategies and Memory Markets Track) | | Organizer + Moderator: Jean S. Bozman, President, Cloud Architects Advisors | Room: GAMR 1 (Great America Meeting Room 1)
| Paper Presenters:
| Memory & Storage - Resilience & Quality future directions
Jung Yoon, Distinguished Engineer and CTO, Supply Chain, IBMMemory Market Downturn and Recovery Cause and effects
Mark Webb, Analyst, MKW VenturesAligning Storage to emerging CXL Peer to Peer Communication Models
Sam Bradshaw, Storage Solutions Architect (Pathfinding), SolidigmDifferentiated Memory Pooling with CXL
Divya Vijayaraghavan, Technical Lead, Intel Programmable Solutions Group |
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| Session Description:
| Ensuring resilience and quality in memory and storage is crucial for complex AI workloads, big data, energy efficiencies, and security protection. This session discusses key quality requirements for DRAM and Flash-SSD from an end-to-end quality management perspective. It explores the possibility of using NVMe Flash instead of DRAM for lower TCO and examines the impact of CXL memory pooling on system security and isolation. The session also covers the effects of the current memory market downturn and proposes a new roadmap for NAND and DRAM technology introduction and cost changes.
| | About the Organizer/Moderator: | Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
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Tuesday, August 8th
8:30-9:35 AM
Open | | BMKT-101-2: Will All Storage Reside in the Public Cloud? (Business Strategies and Memory Markets Track) | | Organizer + Chairperson: Jay Kramer, President, Network Storage AdvisorsOrganizer + Moderator: Dave Raffo, Senior Analyst, The Futurum Group | Room: GAMR 2 (Great America Meeting Room 2)
| Panel Members:
| Panelist: Cody Hosterman, Director, Pure StoragePanelist: Brian Pawlowski, Chief Development Officer, Quantum Corp.Panelist: Eric Herzog, Chief Marketing Officer, InfinidatPanelist: Gary Lyng, VP Product Marketing, Hitachi Vantara |
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| Session Description:
| The largest data storage vendor today is Amazon. As customers migrate more and more of their data to the public cloud, what opportunities does this create for the data storage vendors? Will everything be in the public cloud or will customers repatriate storage back on-premises to private clouds? Let’s ask the data storage vendors who have innovative cloud strategies what they think about strategies to store, access and protect data now and into the future.
| | About the Organizer/Moderator: | Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.
Before joining the Evaluator Group, Dave spent 25 years as a technology journalist and covered enterprise storage for more than 15 years. He most recently worked for 13 years at TechTarget as Editorial Director and Executive News Editor for storage, data protection and converged infrastructure. In 2020, Dave won an American Society of Business Professional Editors (ASBPE) national award for column writing. His previous jobs covering technology include news editor at Byte and Switch, managing editor of EdTech Magazine, and features and new products editor at Windows Magazine. Before turning to technology, he was an editor and sports reporter for United Press International in New York for 12 years.
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Tuesday, August 8th
8:30-9:35 AM
Open | | CLDS-101-1: Cloud Technologies (Cloud Storage and Applications Track) | | Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMDChairperson: James Borden, Principal Engineer, SSD Industry Standands, SSD BU, KIOXIA | Room: Ballroom B
| Paper Presenters:
| Benchmarking a Cloud scale, Object based STaaS solution on Kubernetes
Swati Chawdhary, Senior Manager, Samsung ElectronicsConsistent Hashing Powering Reliable Distributed Cloud Storage Architecture
Vishwas Saxena, Technologist, Firmware Engineering, Western DigitalSuper-Charging Cloud Native Storage with Zones
Dennis Maisenbacher, Principal Engineer, Western Digital |
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| Session Description:
| Cloud-native storage applications are becoming increasingly popular for their scalability and flexibility in managing data in public and private clouds. However, consistent high performance and cost-effective storage solutions are crucial for maturing workloads. This talk focuses on the benefits of zoned storage within Kubernetes, enabling end-users to access consistent throughput and superior QoS. Additionally, a decentralized cloud storage architecture is presented, featuring consistent hashing that reduces the need for a central server to manage distributed File Objects. Finally, a cloud-scale object-based STaaS solution is discussed, exploring how it improves storage efficiency and enhancing data center performance.
| | About the Organizer/Moderator: | Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
James is Principal Engineer, Standards, at KIOXIA focusing on SSD technologies. James has over 35 years of experience in the storage industry, focusing on engineering and customer requirements, customer adoption, and evangelism with stints at IBM, Microsoft, Western Digital, and Seagate. James has been active in storage standards since 2005 as part of his mission to drive broad industry adoption of innovative storage products from multiple suppliers. James earned a BS in Mathematics from the University of Kentucky, Lexington.
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Tuesday, August 8th
8:30-9:35 AM
Open | | DCTR-101-1: Hyperscale Applications Part 1 (Data Center Applications Track) | | Organizer + Chairperson: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology | Room: Ballroom E
| Paper Presenters:
| Standardized Storage Telemetry for Secure Fleet Monitoring and Debug
Steven Wells, Fellow - Storage Solutions Architecture, Micron TechnologyFlash at Scale
Vineet Parekh, Hardware Systems Engineer, MetaOCP Datacenter NVMe SSD Update
Ross Stenfort, Hardware Systems Engineer, Storage, MetaLee Prewitt,
Principal Hardware Program Manager,
Microsoft
Leveraging Flexible Data Placement (FDP) in Hyperscale Applications
Wei Zhang, Software Engineer, MetaYoung Ahn,
Software Engineer,
Meta
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| Session Description:
| The OCP Datacenter NVMe SSD update provides an overview of upcoming changes and improvements. The discussion on leveraging Flexible Data Placement (FDP) in hyperscale applications focuses on the allocation of flash storage for guaranteed SLAs, and the limitations of classic NVMe SSDs. Flash at Scale covers the design and maintenance of flash devices in a hyperscale environment. Standardized Storage Telemetry for Secure Fleet Monitoring and Debug proposes a new approach for enabling standardized telemetry to be securely shared with storage vendors for vendor deep learning failure analysis and debug.
| | About the Organizer/Moderator: | In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
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Tuesday, August 8th
8:30-9:35 AM
Open | | FMAR-101-1: NVMe Zoned Namespaces (ZNS) (Flash Memory Architectures Track) | | Organizer + Chairperson: Brian Berg, President, Berg Software Design | Room: Ballroom A
| Paper Presenters:
| Flexible ZNS Configurations for Optimizing QLC-Based Applications
David Wang, Director, Enterprise SSD Firmware, Silicon MotionZNS SSDs: Achieving Large-Scale Deployment
Matias Bjorling, Distinguished Engineer and Country Manager, R&D Engineering, Western DigitalZoned Storage for UFS on Smartphones
Bart Van Assche, Software Engineer, Google |
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| Session Description:
| In this session on NVMe Zoned Namespaces (ZNS), experts will discuss a flexible write data path for optimal performance and durability in up to 128 zones with varying sizes for different storage applications; Zoned Storage for UFS on Smartphones; and ZNS SSDs' progress, adoption, and software ecosystem across filesystems, databases, and cloud orchestration platforms for large-scale deployment.
| | About the Organizer/Moderator: | Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
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Tuesday, August 8th
8:30-9:35 AM
Open | | INDA-101-1: Automotive Panel Part 1 (Industry Applications Track) | | Organizer: Andy Marken, President, Marken CommunicationsModerator: Greg Basich, Associate Director, Automotive Infotainment and Telematics, Technology Insights | Room: Ballroom J
| Panel Members:
| Panelist: Roger D. Melen, , Toyota ResearchSpeaker: Joseph OHare, Marketing Director, EverspinSpeaker: Steve Shih, Project Manager, Silicon MotionSpeaker: Adrian Cosoroaba, Technical Marketing Manager, Winbond Electronics |
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| Session Description:
| Trending for Automotive SSDs is the implementation of new architecture and technologies to support the evolution towards autonomous vehicles. The key features for the future include the use of SRIOV by SSDs to create a centralized/zonal architecture that saves costs and improves overall design. Additionally, securing and protecting critical data stored in these devices is crucial for the safety of vehicles. The implementation of MRAM and other persistent memory features will ensure reliable and trustworthy performance even in challenging conditions.
| | About the Organizer/Moderator: | Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.
Greg is Associate Director with Strategy Analytics’ Automotive Infotainment & Telematics service and the company’s Automotive Connected Mobility service. He has been with Strategy Analytics for more than 5 years after a previous 13-year career as a business-to-business automotive journalist. At Strategy Analytics, Greg focuses on a number of topics, including connected car technologies and business models, automotive infotainment, mobility services such as car sharing and ride hailing, and automotive cyber security.
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Tuesday, August 8th
8:30-9:35 AM
Open | | NVME-101-1: NVM Express State of the Union and Upcoming Technical Proposals (NVMe Track) | | Session Sponsor: NVM Express | | Chairperson + Speaker: Amber Huffman, Principal Engineer, Google | Room: Ballroom F
| Paper Presenters:
| NVM Express State of the Union: The Language of Storage
Amber Huffman, Principal Engineer, GoogleWhat's New in NVMe Technology:Ratified Technical Proposals
Mike Allison, Account Coordinator, Nereus |
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| Session Description:
| NVM Express State of the Union: The Language of Storage: NVM Express (NVMe) technology has become synonymous with high-performance storage seeing widespread adoption in client, cloud, and enterprise applications. Since the release of the NVMe 2.0 family of specifications, the NVM Express organization has released a number of new features to allow for faster and simpler development of NVMe solutions in order to support increasingly diverse environments. This presentation provides an overview of the latest NVMe technologies, summarizes the NVMe technology roadmap, and describes new NVMe standardization initiatives. What’s New in NVMe Technology: Ratified Technical Proposals: In this presentation, attendees will get an overview of several of the new technical proposals (TP) ratified after FMS 2022 and not contained in the NVMe 2.0 specifications. Included in the presentation is the new NVM Express® Boot Specification, copying user data between namespaces, virtualization of NVMe over Fabrics (NVMe-oF) NVM subsystems, measuring and reporting Rx Phy eye opening, Flexible Data Placement, and more. Join us to find out how these new features will aid NVMe technology development and propel us into the future of storage.
| | About the Organizer/Moderator: | Amber Huffman is a Principal Engineer in Google Cloud responsible for leading industry engagement efforts in the data center ecosystem across servers, storage, networking, accelerators, power, cooling, security, and more. Prior to joining Google, she spent 25 years at Intel serving as an Intel Fellow and VP. Amber is the President of NVM Express, on the Board of Directors for the Universal Chiplet Express Interconnect, and the co-chair of the Open Compute Foundation Storage Project. She has led numerous industry standards to successful adoption, including NVM Express, Open NAND Flash Interface, and Serial ATA. Amber earned a bachelor’s degree in computer engineering from the University of Michigan and a master’s degree in electrical engineering from Stanford University. She has been granted more than 20 patents in storage architecture. Amber is known as an inclusive leader and passionate mentor for technologists, including a track record of sponsoring numerous men and women to senior technologist positions.
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Tuesday, August 8th
8:30-9:35 AM
Open | | SARC-101-1: CXL 3.X (System Architectures Track) | | Session Sponsor: SNIA | | Organizer + Chairperson: Debendra Das Sharma, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel | Room: Ballroom G
| Paper Presenters:
| Making a Case of CXL Native Memory
San Chang, Director of Engineering, WolleyCompute Express Link (CXL) 3.0: Enhancements to memory pooling and sharing
Mahesh Wagh, Senior Fellow, AMDInnovations in CXL 3.x - Novel Device Types, Capabilities, and Interconnects
Danny Moore, Senior Manager, Product Managment and Strategy, Rambus |
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| Session Description:
| This session delves into the latest developments in Compute Express Link (CXL) 3.x, showcasing the introduction of novel device types, capabilities, and interconnects. Attendees will learn about CXL Multi-Headed Devices, the new CXL Dynamic Capacity Device (DCD) capability, and CXL Fabrics- a new multi-level switch architecture. The presentation will provide a comprehensive overview of each aspect and their potential use cases.
| | About the Organizer/Moderator: | Dr. Debendra Das Sharma is an Intel Senior Fellow and Director of I/O Technology and Standards Group. He is an expert in I/O subsystem and interface architecture, delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), coherency, multichip package interconnect, SoC, and rack scale architecture. He has been a lead contributor to multiple generations of PCI Express since its inception, a board member and leader of the PHY Logical group in PCI-SIG, and is the Chair of UCIe. Debendra joined Intel in 2001 from HP. He has a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst and a Bachelor of Technology (Hons) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur. He holds 99 U.S. patents and currently lives in Saratoga, Calif. with his wife and two sons. He enjoys reading and participating in various outdoor and volunteer activities with his family.
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Tuesday, August 8th
8:30-9:35 AM
Open | | SSDS-101-1: Controller Capabilities (SSD Technology Track) | | Organizer: Erich Haratsch, Senior Director Architecture, Marvell | Room: Ballroom D
| Paper Presenters:
| Throughput and Endurance Improvement with Online Read Level Tracking
Cloud Zeng, Technical Supervisor, PhisonSmart Debugging capabilities in SSD Controllers
Phillip Arellano, Sr. Applications Engineer, DCS, Microchip TechnologyImpact of 16k Indirection Unit on real-world workloads
Luca Bert, DMTS, SSD Architecture, Micron TechnologyArm-Enabled Controllers for Storage and CXL-Connected Devices
Matt Bromage, Storage Segment Mgr, Arm |
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| Session Description:
| Experts in this session discuss a variety of controller capabilities. Online Read Level Tracking is a feature for Enterprise SSD that enhances read performance and extends endurance by assigning appropriate read offsets to every read command. Even with a long tracking period, our error recovery flow can detect inaccuracies and minimize recovery latency. Real drive test results show a greatly reduced retry trigger rate with this feature. The impact of a 16k Indirection Unit on real-world workloads is analyzed, dispelling the assumption that larger IU results in unacceptable WAF growth. Real-life configurations and industry benchmarks are used for measurement. Debugging high-speed interfaces like PCIe and Flash is challenging, necessitating built-in diagnostic capabilities in SSD controllers. This presentation highlights the challenges associated with high-speed interfaces and gives examples of smart debug and diagnostic capabilities in an SSD controller architecture.Using Arm Cortex CPUs allows for dedicated computation capabilities in storage controllers, single-cycle access to custom RTL accelerators, and interconnects to connect Flash, Memory, and SCM to CXL. This presentation reviews the approach to Arm-enabled controllers for storage and CXL-connected devices.
| | About the Organizer/Moderator: | Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).
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Tuesday, August 8th
9:45-10:50 AM
PRO | | AIML-102-1: Artificial Intelligence/Machine Learning (Artificial Intelligence Applications Track) | | Organizer + Chairperson: David McIntyre, Director Product Planning, Samsung Electronics | Room: Ballroom C
| Paper Presenters:
| Uniform Machine Learning Framework for Intent Based Semantic Image Retrieval
Vishwas Saxena, Technologist, Firmware Engineering, Western DigitalAnalog eFlash drives edge AI/ML acceleration
Dave Eggleston, Sr Business Development Manager, Microchip TechnologyArtificial Intelligence Applications: Machine Learning
Ram Edupuganti, Staff Applications Engineer, Microchip Technology |
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| Session Description:
| This session will capture a variety of artificial intelligence and machine learning applications. Analog eFlash drives offer breakthrough cost, power, and performance for AI/ML inference at the edge, impacting billions of products with unparalleled audio and video processing speed. Learn how to design a uniform machine learning framework for intent-based semantic image retrieval and how innovative solutions using AI can improve smart NAND management algorithms. Additionally, creating trustworthy AI environments can defend against daily adversarial AI/ML attacks, implementing principles like security and privacy outlined in the National AI Initiative
| | About the Organizer/Moderator: | David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
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Tuesday, August 8th
9:45-10:50 AM
Open | | ASIA-102-1: Memory and Storage Trends in Asia Part 1 (Memory and Storage Trends in Asia Track) | | Organizer + Chairperson: Jianguo Yang, Associate Professor, Institute of Microelectronics of the Chinese Academy of SciencesOrganizer: Harry Fu, , Sage MicroelectronicsChairperson: Chris Tsu, CEO, Sage Microelectronics | Room: GAMR 2 (Great America Meeting Room 2)
| Paper Presenters:
| Challenge and Opportunity for PCIe 5.0 SSD
Xiang Chen, Vice President of Engineering, DapuStorTiered Hashing: Revamping Hash Indexing under a Unified Memory-Storage Hierarchy
Jian Zhou, Associate Professor, Huazhong University of Science and TechnologyResistive Switching Memory, From Device To Applications
Jianguo Yang, Associate Professor, Institute of Microelectronics of the Chinese Academy of SciencesTechnical innovation in designing next generation PCIe Gen5 Client SSD
Yuan-Shun Cheng, Senior Project Manager, Silicon MotionDiscussion on the Differences in Chinese Enterprise-level SSD Demand
Kang Lei, VP, Product planning, Dera Storage |
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| Session Description:
| A novel approach, called WA-OPShare, has been proposed to allocate limited storage resources across multiple tenants in China's non-volatile storage sector. The workload-adaptive OPS allocation solution identifies underutilized storage space and predicts the OPS-induced performance benefit of each tenant to maximize tenant benefit. Experimental results show up to 40.3% improvement in performance and 17.5% reduction in write amplification. In another development, Tiered Hashing is being proposed to revamp hash indexing under a unified memory-storage hierarchy, which can notably reduce tail-latencies and improve garbage collection (GC) efficiency. Finally, researchers are investigating the reliability and different applications of resistive random access memory (RRAM), a promising embedded nonvolatile memory under advanced process nodes.
| | About the Organizer/Moderator: | Jianguo Yang earned his Ph.D. from Fudan University (Shanghai, China). His research interests include circuit designs for volatile and nonvolatile memory, hardware security, memory-centric computing and memristor logics. He has authored or co-authored several technical papers such as JSSC, Symposium on VLSI, IEDM, TVLSI, ASSCC, ISCAS, ESSCIRC & ESSDERC etc.. Some of his recognitions include two Best Paper Awards from the IEEE International Conference on ASIC on high performance memory circuit design.
Harry Fu is Director of R&D at Sage Microelectronics, Dallas Center. He holds a BS in Electronic Engineering from Tsinghua University and a MS in Electrical Engineering from University of Nevada, Las Vegas.
Chris Tsu has over 30 years of engineering and management experience in mass storage, video processing, networking and telecommunications. He spent more than 10 years with Quantum and IBM as hard drive servo and DSP engineer/manager. and as major designer for multimedia and Fiber optical communication ASIC with Oak, Divio and Sytera, founded of Baleen System in 2002, as an industrial pioneer in NAND Flash and SSD ASIC, Chris has more than 20 patents. Chris holds an MS in Electrical Engineering from San Jose State University. He also holds another MS degree in Automatic Control and Machine Intelligence from Stanford University
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Tuesday, August 8th
9:45-10:50 AM
Open | | BMKT-102-1: Market Trends (Business Strategies and Memory Markets Track) | | Organizer + Moderator: Jean S. Bozman, President, Cloud Architects Advisors | Room: GAMR 1 (Great America Meeting Room 1)
| Paper Presenters:
| Market Trends and Risks in the NAND Flash Memory Industry
Bryan Ao, Research Manager, TrendForce Corp.All-Flash Technology Getting the Advantage of Software Defined Storage
Eric Herzog, Chief Marketing Officer, InfinidatFlash & Memory Market Annual Update
Jim Handy, General Director, Objective Analysis |
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| Session Description:
| This session gives an in-depth analysis of the latest trends in the flash and memory market, including the impact of emerging technologies and geopolitical factors on the market cycle. It provides insights into the dynamics driving the market, including new market influences like CXL, UCIe, and DDR5, as well as lessons learned from the failure of Optane. Attendees will leave with a keen understanding of what to expect in the memory market over the next year.
| | About the Organizer/Moderator: | Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | CLDS-102-1: Cloud Scaling (Cloud Storage and Applications Track) | | Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMDChairperson: John Geldman, Director of SSD Industry Standards, KIOXIA | Room: Ballroom B
| Paper Presenters:
| A File System Optimized for Objects
Douglas Dumitru, CTO, WildFire StorageAchieving Exadata-Class Performance in the Public Cloud
Behnam Eliyahu, Director, Solutions Architecture, ZadaraSoftware-Hardware Co-Design for High Performance Storage System on ZNS SSD
Wei Tang, Senior Software Architect, ByteDance, Inc |
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| Session Description:
| In this session, experts will discuss a variety of cloud scaling solutions, including achievinge exadata-class performance in the public cloud; a file system optimized for objects: software-hardware co-design for high performance storage system on ZNS SSD: Zoned namespace (ZNS); and why Storage-as-a-Service (STaaS) is important for a sustained data center:
| | About the Organizer/Moderator: | Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
John Geldman is a Director of SSD Industry Standards at KIOXIA. John is also a Member of the Board of Directors of NVM Express. John is currently an active contributor to NVM Express, INCITS T10, INCITS T13, JEDEC, OCP, PCI-SIG, SATA IO, SNIA, and IEEE SISWG. John has had corporate leadership responsibility for standards for multi-billion dollar storage vendors since 2011. He has been involved in storage standards since 1992, with an early introduction to standards that included the transition from X3T9 to T13 (ATA) and T10 (SCSI), as well as the transition from PCMCIA to CardBus. John has been an active FMS CAB member for at least 10 years.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | DCTR-102-1: Hyperscale Applications Part 2 (Data Center Applications Track) | | Chairperson: Steven Wells, Fellow - Storage Solutions Architecture, Micron TechnologyOrganizer: Jonathan Hinkle, Distinguished Member of Technical Staff, Micron Technology | Room: Ballroom E
| Paper Presenters:
| Design a Flash-Centric Storage Architecture for an Optimized Cloud Data Center
Sam Bhattarai, Director, Product Line Manager, Data Center SSDs, KIOXIAReducing Data Movement and Speeding Up Analytics for the Hyperscale Era
Krishna Maheshwari, Chief Product Officer, Neuroblade |
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| Session Description:
| This session will discuss the importance of designing a flash-centric storage architecture for an optimized cloud data center. By optimizing for high density, massive scale, energy efficiency, balanced performance, and robust reliability, data centers can maximize the value of flash memory and provide higher TCO. HIghlghted will be a flash-centric storage approach and use cases to illustrate the benefits of this approach for hyperscalers, data centers and other high-density applications.
| | About the Organizer/Moderator: | Steven is a 36-year veteran with most of that time focused on flash memory component and SSD design. He currently is a Fellow of Storage Solutions Architecture at Micron Technology. He currently holds 60+ patents covering flash memory and security. Recipient of 2017 FMS Most Innovative Memory Technology - Data Center.
In Micron's Storage Business Unit, Jonathan investigates new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | FMAR-102-1: 3D Flash Technology (Flash Memory Architectures Track) | | Organizer + Chairperson: Brian Berg, President, Berg Software Design | Room: Ballroom A
| Paper Presenters:
| 3D NAND Process Technology: 2023 and Beyond
JEONGDONG CHOE, Senior Technical Fellow, TechInsightsAchieving Robust Reliability Design in High Bit-Density 3D Flash
JIEZHI CHEN, Professor, Shandong University |
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| Session Description:
| 3D NAND process technology continues to advance as manufacturers race to increase the number of vertical gates in their devices. Despite challenges, companies like Samsung, Micron, and SK Hynix are leading the way in SSD and mobile storage applications. Meanwhile, reliability design is crucial in achieving optimal performance in high-density 3D Flash storage, with new strategies emerging for enhancing endurance and data retention. Finally, chip area optimization involves innovative periphery circuit positioning, with manufacturers adopting different designs and architectures to optimize density and reduce cost.
| | About the Organizer/Moderator: | Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | INDA-102-1: Automotive Panel Part 2 (Industry Applications Track) | | Organizer: Andy Marken, President, Marken CommunicationsChairperson: T Kim Parnell, Principal, Parnell Engineering & Consulting | Room: Ballroom J
| Panel Members:
| Panelist: Nicolas Leng, Assistant Manager, Product Management, ATP ElectronicsPanelist: Fen Chen, Principal Engineer, Cruise LLCPanelist: Bernd Niedermeier, Head of Automotive business develop, TuxeraPanelist: Kevin Hsu, Applications Engineer Manager, KIOXIA |
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| Session Description:
| In this session panelists from KIOXIA, Cruise LLC, and ATP Electronics will discuss and take your questions on how UFS 4.0 benefits mobile and automotive applications, on flash memory reliability for emerging AV applications, and how to ensure robust embedded memory solutions in automotive applications.
| | About the Organizer/Moderator: | Andy Marken is the president of Marken Communications, a marketing consulting and communications agency. For over 25 years, he has worked with leading national and international content development, information, and storage firms. Andy has written over 200 articles on management, marketing, and communications. He is also a widely quoted and recognized insider commentator and interpreter of personal computer/consumer electronics (PC/CE) industry trends and activities.
T.Kim Parnell, PhD, PE is President of Parnell Engineering & Consulting. Kim is a Stanford PhD in Mechanical Engineering and a Licensed Professional Engineer. Dr. Parnell is active as a Consultant and Litigation Expert Witness in areas such as Patents, Automotive, Crash, Medical Devices, Safety/Reliability. He is an ASME Fellow, an IEEE Life Senior Member, and a Member of SAE and ASM. Kim brings a multi-disciplinary perspective that is critical in vehicle of all types where Mechanical, Electrical, and Computer disciplines all must interact and work together. Within IEEE, Kim is Past-Chair of the IEEE SCV-ExCom (SCV is the largest IEEE Section in the world), Past-Chair of the IEEE-CNSV (Consultants' Network of Silicon Valley), and IEEE-VTS (Vehicular Technology Society).
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Tuesday, August 8th
9:45-10:50 AM
Open | | NVME-102-1: Timberland Boot Specification and Host Controlled Live Migration (NVM Express Track) | | Chairperson: Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA | Room: Ballroom F
| Paper Presenters:
| Timberland Update: Booting over an NVMe/TCP Transport
Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIAHost Controlled Live Migration
Mike Allison, Account Coordinator, NereusLee Prewitt,
Principal Hardware Program Manager,
Microsoft
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| Session Description:
| Timberland Update: Booting over an NVMe/TCP Transport: As large deployments become more common, our industry needs a standardized, multi-vendor solution to boot computer systems from OS images stored on NVMe® devices across a network. The newly published NVM Express® Boot Specification and ecosystem partnership with UEFI and ACPI enables this by leveraging the NVMe over Fabrics (NVMe-oF™) standard. This talk is a dive into the details of the new specification and the design of an open-source prototype for booting over an NVMe/TCP transport using a UEFI implementation. Host Controlled Live Migration: To minimize any downtime in virtualized and cloud environments, a seamless migration of the Virtual Machine (VM) and associated resources needs to be completed without affecting the user experience in the case of any system failures or system maintenance. When a VM is migrated from one node to another node, the namespaces that the VM has access to also need to be seamlessly migrated. This presentation is an overview of capabilities being investigated by NVM Express to support a host controlling the migration of a VM and the namespaces used by that VM to a different controller where that controller may exist in a different NVM subsystem. This includes: o Showing how the migration of the controller and namespaces are transparent to the VM being migrated. o Identifying how a controller logs all live changes to the namespaces as the host migrates the allocated logical blocks of those namespaces. o The ability to migrate the controller Head/Tail information on all queues after quiescing the controller operations. o Restoring operations on the migrated controller such that commands not fetched prior to the migration are processed after the migration.
| | About the Organizer/Moderator: | Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | SARC-102-1: CXL Pooling (System Architectures Track) | | Session Sponsor: SNIA | | Organizer + Moderator: Willie Nelson, Technology Enabling Architect, IntelOrganizer: Jim Pappas, Director, Technology Initiatives, Intel | Room: Ballroom G
| Paper Presenters:
| A Scalable CXL Memory Pooling Solution with use of CXL Swtich
Jianping Jiang, VP, Xconn TechnologiesMemory Pooling & Memory Sharing with CXL 3.x
Vince Hache, Director of Systems Architecture, RambusComposable architectures in the box, in the rack, and rack-to-rack
George Apostol, Founder and CEO, Elastics.cloudMemory Sharing and Pooling in CXL Ecosystem
Chetana Kaushik, Senior Applications Engineer, Microchip TechnologyTam Do,
Manager,
Microchip Technology
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| Session Description:
| Memory Pooling and Sharing with CXL 3.x provides technical insight into multi-logical and multi-headed devices, and the Dynamic Capacity Device framework. The solution enables memory sharing across multiple systems, improving memory utilization, reducing power consumption and costs. The presentation explains how CXL maintains multi-host coherency, and the benefits of pooling memory to improve performance and reduce latency. Other presentations cover scalable memory pooling, and the use of CXL to deliver composable architectures with significant benefits for big data workloads.
| | About the Organizer/Moderator: | Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.
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Tuesday, August 8th
9:45-10:50 AM
PRO | | SSDS-102-1: Controllers for the Data Center (SSD Technology Track) | | Organizer: Erich Haratsch, Senior Director Architecture, Marvell | Room: Ballroom D
| Paper Presenters:
| Shaping NVMe SSD IO Performance in Multi-Virtual Host Environments
Gary Adams, Associate VP of Enterprise Marketing, SMIDesigning Storage ATC using real life workload
Luca Bert, DMTS, SSD Architecture, Micron TechnologyInnovations in SSD Controller Architecture for next generation Data Center SSDs
Adam Jachniewicz, Principal, Applications Engineer, DCS, Microchip TechnologyNVMe Metadata and Protection Information
Niels Reimers, Strategic Planner, Solidigm |
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| Session Description:
| This session will explore how MonTitan's PerformaShape technology utilizes a shaping engine to maximize IO performance in multi-virtual host environments. We will demonstrate how the shaping engine regulates performance to multiple users while isolating noise, and how designing storage ATCs using real-life workloads can help set parameters for new technology. Additionally, we will discuss NVMe metadata and protection information as well as innovations in SSD controller architecture for next-gen data center SSDs.
| | About the Organizer/Moderator: | Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).
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Tuesday, August 8th
3:20-4:25 PM
PRO | | ASIA-103-1: Memory and Storage Trends in Asia Part 2 (Memory and Storage Trends in Asia Track) | | Organizer: Harry Fu, , Sage MicroelectronicsChairperson: Chris Tsu, CEO, Sage Microelectronics | Room: GAMR 1 (Great America Meeting Room 1)
| Paper Presenters:
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| Session Description:
| TThis session will continue the topic of Memory and Storage in Asia begun in Session ASIA-102-1. There will be a presentation that focuses on the evolution of NAND flash technology, particularly the adoption of QLC and its increasing importance in datacenter applications. Then the speakers from ASIA-102-1 will join the speaker in this session for a panel discussion on the presented topics
| | About the Organizer/Moderator: | Harry Fu is Director of R&D at Sage Microelectronics, Dallas Center. He holds a BS in Electronic Engineering from Tsinghua University and a MS in Electrical Engineering from University of Nevada, Las Vegas.
Chris Tsu has over 30 years of engineering and management experience in mass storage, video processing, networking and telecommunications. He spent more than 10 years with Quantum and IBM as hard drive servo and DSP engineer/manager. and as major designer for multimedia and Fiber optical communication ASIC with Oak, Divio and Sytera, founded of Baleen System in 2002, as an industrial pioneer in NAND Flash and SSD ASIC, Chris has more than 20 patents. Chris holds an MS in Electrical Engineering from San Jose State University. He also holds another MS degree in Automatic Control and Machine Intelligence from Stanford University
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Tuesday, August 8th
3:20-4:25 PM
Open | | BMKT-103-1: Perpetual Upgrades,Managed Services & Other Modern Storage Consumpt (Business Strategies and Memory Markets Track) | | Organizer + Chairperson: Jay Kramer, President, Network Storage AdvisorsOrganizer + Moderator: Dave Raffo, Senior Analyst, Evaluator Group, The Futurum Group | Room: GAMR 2 (Great America Meeting Room 2)
| Panel Members:
| Panelist: Marc Staimer, President, Dragon Slayer ConsultingPanelist: Eric Herzog, Chief Marketing Officer, InfinidatPanelist: Rupin Mohan, DIrector R&D/CTO (SAN), HPEPanelist: Taruna Gandhi, VP Product Marketing, Digital Experience, Pure Storage |
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| Session Description:
| Storage as a Service has become a buzzword in recent years as all major vendors strive to deliver a cloud-like buying experience while shifting purchasing model from Capex to Opex. Vendors are also adding perpetual upgrade programs, giving customers with service contracts free upgrades every 3 years or when new technology becomes available. Some of these programs include energy efficiency guarantees. Flash being an enabler to longer life spans, energy efficiency, changes in accounting and other buying factors, this panel session with industry insiders will look at these new programs, analyze who they best serve and include feedback on what customers think of them and want from their storage vendors.
| | About the Organizer/Moderator: | Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.
Dave Raffo has been covering enterprise storage as a reporter and analyst for more than 20 years. He currently focuses on storage consumption models, hyperconverged infrastructure, cloud storage and container storage at The Futurum Group. Before joining Evaluator Group, Dave spent 13 years at TechTarget as Editorial Director and Executive News Editor for its storage, data protection and converged infrastructure sites. In 2020, His previous jobs covering technology include news editor at Byte and Switch and managing editor of EdTech Magazine. Dave has moderated panels at Flash Memory Summit for the past 4 years, and has spoken at Networld Interop and other tech conferences.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | CLDS-103-1: Flash in the Cloud (Cloud Storage and Applications Track) | | Organizer: Leah Schoeb, Sr. Developer Relations Manager, AMDChairperson: Scott Shadley, Strategic Planner, Solidigm | Room: Ballroom B
| Paper Presenters:
| Future of Flash for Cloud Storage
Swapna Yasarapu, Azure Storage Architecture, MicrosoftAn OCP reference system for CXL-enabled compute disaggregation
Siamak Tavallaei, CXL™ Consortium President, CXL ConsortiumIntroduction of multicore architecture of Crimson
Chunmei Liu, Senior Engineer, IntelDesigning for Flash-Accelerated Low Latency Cloud Applications
Suman Gumudavelli, Hardware Systems Engineer, Meta |
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| Session Description:
| In this session, experts will introduce the next-gen Ceph, Crimson, with a multicore architecture based on Seastar framework; an OCP project which brings together technology leaders to create a reference system for compute disaggregation enabled by CXL; and provide Microsoft's perspective on flash needsto meet the storage requirements of new applications.
| | About the Organizer/Moderator: | Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | FMAR-103-1: NVMe Flexible Data Placement (FDP (Flash Memory Architectures Track) | | Organizer + Chairperson: Brian Berg, President, Berg Software Design | Room: Ballroom A
| Paper Presenters:
| NVMe's Flexible Data Placement (FDP): Best Practices
Daniel Helmick, NVMe SSD Interface Architect, Samsung ElectronicsFDP and ZNS for NAND Data Placement: Landscape, Trade-Offs, and Direction
Javier Gonzalez, Principal Software Engineer, Samsung ElectronicsFDP: Flexible Methods for the Benefit of Conventional Applications
Luca Bert, DMTS, SSD Architecture, Micron Technology |
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| Session Description:
| FDP and ZNS are innovative NAND memory technologies used for data placement. In this talk, we will detail the differences between FDP and ZNS in terms of read/write model, WAF reduction, and ecosystem complexity. We will also examine viable SSD designs that implement FDP for legacy applications and virtualized environments, and provide best practices for Hosts that support FDP to optimize SSD performance and endurance.
| | About the Organizer/Moderator: | Brian's duties as Technical Chair for Flash Memory Summit include chairing the Architectures track, which has addressed topics including the evolution of the Flash Translation Layer (FTL) since he originated this track in 2009. He also organizes the Software and Artificial Intelligence tracks and the Invited Talks, is a member of the Lifetime Achievement Awards (LAA) committee, and has played an active role in many other aspects of the conference since 2007. Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB, and he works extensively with intellectual property and patents. He has participated in over 80 conferences as a speaker, session chair and conference chair. Brian is also active as an IEEE officer and volunteer, and has received IEEE awards for Outstanding Leadership and service. He has initiated and organized the dedications of over a dozen IEEE Milestones, including one for the Floating Gate EEPROM and its importance for the success of flash memory. He holds a Bachelors in Mathematics, and was in the Computer Engineering graduate program at Stanford University before forming a startup company with some associates.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | OMEM-103-1: RRAM (Other Memory Technologies Track) | | Organizer: Dave Eggleston, Sr Business Development Manager, Microchip Technology | Room: Ballroom E
| Paper Presenters:
| Perspectives on Developing 3D Resistance Memory with Multi-level Capability
Steve Chung, NYCU Chair Professor/UMC Chair Professor, National Yang Ming Chiao Tung UniversityEmerging Non-Volatile Memory – A 2023 Market Update
Simone Bertolazzi, Technology and Market Analyst, Yole IntelligenceIn-memory computing with 11-bits/cell multilevel resistive switching devices
Glenn Ge, CEO, TetraMem Inc.ReRAM: The Next NVM is Here
Amir Regev, CTO, Weebit-nano |
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| Session Description:
| This session discusses the development of 3D resistance memory with multi-level capability. Proposed is a gate-type 1T1R structure that allows for multi-level cell capability, ultra-low power usage, and no sneak path issue. This technology has great potential for embedded applications and can compete with floating-gate NAND. Other topics include emerging non-volatile memory markets and technologies, ReRAM technology, and in-memory computing with multilevel resistive switching devices.
| | About the Organizer/Moderator: | Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | SARC-103-1: CXL Fabrics (System Architectures Track) | | Session Sponsor: SNIA | | Organizer: Jim Pappas, Director, Technology Initiatives, IntelOrganizer + Moderator: Willie Nelson, Technology Enabling Architect, Intel | Room: Ballroom G
| Paper Presenters:
| CXL Performance Optimization & Validation SW Development Kit
Steven Frank, Consultant - Avery Design Systems, Avery Design SystemsCXL Fabric Manager Architecture
Viacheslav Dubeyko, Linux kernel engineer, ByteDanceIntroduction to CXL Fabrics in 3.x
Vince Hache, Director of Systems Architecture, Rambus |
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| Session Description:
| CXL Fabric Manager is responsible for system composition and allocation of resources in CXL devices and can be embedded in firmware, on a host, or run on a BMC. The architecture could include a configuration tool, daemon, and QEMU emulation for scalability. CXL Fabrics offer multi-level switch architecture for 4,096 nodes. The CXL Performance Development Kit is a Linux software environment for benchmarking and validating fine-grained performance, scalability, and extensibility. The architecture and capabilities of the kit will be presented alongside benchmarks.
| | About the Organizer/Moderator: | Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.
Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | SARC-103-2: Memory and Storage (System Architectures Track) | | Session Sponsor: SNIA | | Organizer + Moderator: Willie Nelson, Technology Enabling Architect, IntelOrganizer: Jim Pappas, Director, Technology Initiatives, Intel | Room: Ballroom J
| Paper Presenters:
| Benchmarking a New Paradigm: Analysis of a Real Processing-in-Memory System
Juan Gomez Luna, , ETH Zurich and Carnegie Mellon UniversityStandardizing Memory to Memory Data Movement with SDXI v1.0
Shyam Iyer, Distinguished Member of TS, DellIs the Time Finally Right for In Memory Computing?
Jim Handy, General Director, Objective AnalysisLinux Foundation Managed Open Source, Software-defined Flash Solution Benefits
Sean Stead, Manager, KIOXIA |
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| Session Description:
| Is the Time Finally Right for In Memory Computing? This session explores why previous attempts at utilizing the parallelism of memory chips failed and what needs to change for success. It also highlights the benefits of In-Memory Computing and examines practicalities that have prevented its adoption in the past. The Linux Foundation's open-source software-defined flash technology is discussed for data centers to extract more value from their flash deployments. A comprehensive analysis of the Processing-in-Memory System is provided in the first publicly-available PIM architecture. Finally, the SNIA Smart Data Accelerator Interface Specification v1.0 is introduced, which sets standards for memory-to-memory data movement and acceleration interfaces.
| | About the Organizer/Moderator: | Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.
Jim Pappas is the Director of Technology Initiatives for Intel’s Data Center Group. He is responsible for establishing broad industry ecosystems that comply with new technologies in Enterprise I/O, Energy Efficient Computing, and Solid State Storage. Jim has played a major role in the PCI Special Interest Group, InfiniBand Trade Association and Open Fabrics Alliance. Jim currently is Vice Chair of the SNIA Board of Directors and Co-Chair of the SNIA Solid State Storage Initiative. Jim has 30 years of experience in the computer industry, holds eight US patents and has spoken at major industry events. He earned a BSEE from the University of Massachusetts Amherst.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | SARC-103-3 What is the Difference Between a Memory Chip and a Memory Chiplet? (System Architectures Track) | | Organizer + Moderator: Charles Sobey, Chief Scientist, ChannelScience | Room: Ballroom F
| Panel Members:
| Panelist: Danny Sabour, VP of Marketing, Avalanche TechnologyPanelist: Balint Fleisher, Sr Director - Near Data Computing, Micron TechnologyPanelist: Joe O'Hare, Marketing Director, EverspinPanelist: Debendra Das Sharma, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel |
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| Session Description:
| Intel's 3D XPoint Optane memory was a promising new nonvolatile memory. However, even their manufacturing and marketing strength could not overcome the business issues it faced. How can any other emerging memory technology developer hope to create a market for their product? Maybe chiplets is the answer! This panel will explore the differences between a standalone memory chip and a memory chiplet, and how their architectures may be affected by different interfaces. There will be a discussion of the current "memory chiplet," high bandwidth memory (HBM), and an examination of how chiplets impact memory tiering.
| | About the Organizer/Moderator: | Chuck Sobey is General Chair of Flash Memory Summit (FMS), the number one independent storage event. He leads a team of industry veterans to organize FMS annually, identifying key trends, topics, and speakers. Chuck is a respected memory and storage technology executive, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging technologies and maximizing their reliability and performance. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording and archiving, on which practically all of the hyperscale and cloud services rely. Chuck is also the co-founder of SmartNICs Summit, as well as Chiplet Summit, which is supporting the development of the heterogeneous chiplet ecosystem. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.
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Tuesday, August 8th
3:20-4:25 PM
Open | | SPEC-103-1: CHIPS Act Panel (Special Sessions Track) | | Organizer + Moderator: Camberley Bates, VP and Practice Lead, Futurum Group | Room: Ballroom C
| Panel Members:
| Panelist: Russell Harrison, Managing Director, IEEEPanelist: Daniel Armbrust, Co-Founder and Director, Silicon CatalystPanelist: Jay Chittoran, Semiconductor Government Affairs, SAMSUNG ELECTRONICS (SSIR)Panelist: Steve Pawlowski, CVP, Advanced Memory Systems, Micron Technology |
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| Session Description:
| This panel session, composed of experts in the technology and government sectors, will discuss the various aspects of the CHIPS Act.
| | About the Organizer/Moderator: | Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.
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Tuesday, August 8th
3:20-4:25 PM
PRO | | SSDS-103-1: Error Correction Capabilities (SSD Technology Track) | | Organizer: Erich Haratsch, Senior Director Architecture, Marvell | Room: Ballroom D
| Paper Presenters:
| 2.5X endurance extended by a 3-Dimensional DSP
Wei Lin, System Architect, Phison ElectronicsAdvanced Error Correction Capabilities for newer NAND
Peter Graumann, Technical Fellow, Microchip TechnologyEnterprise LDPC Arch. for Soft-Error Detection and Noise Immunity Reduction
Jeff Yang, Director, Silicon Motion |
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| Session Description:
| This session focuses on the Enterprise LDPC architecture for Soft-Error Detection and Noise Immunity Reduction, which is necessary for the next generation of Enterprise and Automotive applications. The session also covers the Dynamic Read Retry Method and Advanced Error Correction Capabilities for newer NAND, which improve I/O performance stability and error correction efficiency respectively. Finally, a 3-Dimensional DSP is discussed, which can extend the endurance and reduce error bits for 3-D NAND Flash memories.
| | About the Organizer/Moderator: | Erich Haratsch is Senior Director Architecture in the Storage Business Unit of Marvell Semiconductor, where he is focused on data storage architectures and controller technologies. He was previously Managing Technologist at Seagate Technology, where he led a senior R&D team that developed new hardware architectures and firmware algorithms for solid state disks that successfully went into mass production. Earlier in his career, he developed signal processing and error correction technologies for hard disk drive controllers at LSI Corporation and Agere Systems, which shipped in hundreds of millions of devices. He started his engineering career at Bell Labs Research, where he invented new chip architectures for Gigabit Ethernet over copper and optical communications. He is a frequent speaker at leading industry events, is the author of over 60 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He earned his M.S. and Ph.D. degrees in electrical engineering from the Technical University of Munich (Germany).
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Tuesday, August 8th
7:30-9:30 PM
Open | | FMS 2023 Chat with the Experts (Chat with the Experts Track) | | Room: Ballroom A-D
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| Session Description:
| This popular annual session at Flash Memory Summit is your chance to network in person with industry leaders in the major technology segments of the Flash industry. Come prepared with your questions, grab some food and beverage, and find a table or tables that meet your interests!
| | About the Organizer/Moderator: | |
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