Paper Title: Chiplet Testing Basics

Paper Abstract: Chiplet testing requires a continuing emphasis on design for test and its inclusion throughout the design process. Without this emphasis, test will surely take a long time and incur heavy costs. Tne problem is obvious – testing of chiplet-based designs requires testing of each chiplet separately, along with testing of the interconnect and the entire device. That’s a lot of testing – and it increases as the number of chiplets rise (as it surely will if designers try to take full advantage of modularity). Obviously, testing must start early and progress along with the rest of the design to keep design costs under control.

Paper Author: Arun Kumar, Sr Staff R&D Engineer, Synopsys

Author Bio: Arun Kumar is a Sr Staff R&D Engineer at Synopsys, where he currently works on creating a hierearchical test network in large SoCs. He is a DFT architect with a focus on testing memories, PHYs, and logic devices. He previously worked at LSI Logic and Texas Instruments. He holds a patent and has co-authored testing papers at the VLSI Test Symposium (VTS) and the Interenational Test Confernce (ITC). He earned an MSECE at the University of Florida.