Paper Title: UCIe: A Progress Report for 2024

Paper Abstract: UCIe (Universal Chiplet Interconnect Express) offers a customizable, package-level integration combining die-to-die interconnect and protocol connections. It thus establishes the basis for an interoperable, multi-vendor ecosystem. UCIe provides the physical layer, protocol stack, software model, and compliance testing. The specification leverages the established PCI Express® (PCI-SIG®) and Compute Express Link™ (CXL™) industry standards. It will enable end users to easily mix and match chiplets from a multi-vendor ecosystem for SoCs. UCIe’s new 1.1 specification addresses automotive chiplets, interoperability, lower-cost packaging options, and streaming protocols.

Paper Author: Gerald Pasdast, Sr Principal Engineer, Intel

Author Bio: Gerald Pasdast is a Senior Principal Engineer with Intel, where he works on die-to-die I/O architecture and technology. He has also worked on advanced packaging such as EMIB and Foveros for servers, HPC, and client CPUs. He is a co-author of the UCIe 1.0 specification, has over 30 granted patents with 20 others pending, and has five publications on processors and design in publications such as the IEEE Transactions on Components, Packaging, and Manufacturing Technology, and at conferences such as EEDM, ISSCEE, Hot Chips, and ECTC. He earned a BSEE at San Jose State University. He is the Chair of the UCIe Consortium Form Factor and Compliance Working Group.