Paper Title: Protecting Against ESD in Die-to-Die Interfaces

Paper Abstract: Designers sometimes drop electrostatic discharge (ESD) protection clamps completely for die-to-die interfaces. Once sealed in the package, nothing can touch the pads so danger is unlikely. However, experts recommend some ESD protection to ensure the chiplet assembly process has enough yield. How much is enough? Industry experts recently settled on standards and robustness levels for chiplets. However, some designers still prefer to reduce robustness levels to allow smaller ESD diodes. This approach could cause problems as the interfaces use sensitive thin oxide transistors. Recent discussions focus on ESD events relevant to chiplets, industry proposals for ESD protection, and example solutions used in several applications. Special die-to-die ESD solutions have been used on a wide range of TSMC technologies.

Paper Author: Bart Keppens, Chief Business Development, Sofics

Author Bio: Bart Keppens is Chief Business Development at Sofics, a provider of IP for ESD protection. He focuses on worldwide channel development and on advancing ESD protection at meetings and conferences. He has authored over 40 peer-reviewed published articles at such meetings as International EOS/ESD Symposium on Design and System (IEDS), IEEE International Symposium on Circuits and Systems (ISCAS), and the Custom Integrated Circuits Conference (CICC), and in journals such as IEEE Transactions on Device and Materials Reliability. Before joining Sofics, he worked at imec. He earned an engineering degree from Groep T – International Hogeschool Leuven (Belgium).