Paper Title: Controlling Production Test Costs for Chiplet-Based Design

Paper Abstract: Chiplet-based design complicates production testing. Tests must cover individual chiplets, their interconnections (die-to-die interfaces such as UCIe), and the entire package. Testing can increase time-to-market greatly, and developers must limit such effects. They must stress automation, and consider new techniques such as agent-based monitoring. A thorough integration of test with the entire development process is essential. Manufacturing test flows must be altered for optimal coverage. System Level Test (SLT) will play a vital role, and content re-distribution may be necessary in each step.

Paper Author: Vineet Pancholi, Sr Director Test Technology, Amkor

Author Bio: Vineet Pancholi is Sr Director Test Technology at Amkor, where he leads the development of RF and high-speed digital production test methodologies. Before joining Amkor, Vineet worked in test development at Microchip and Intel. He holds a patent on semiconductor device testers and earned master’s degrees in physics and electrical engineering from Arizona State University. He has written articles for Semiconductor Engineering, MEPTEC Report, and 3D InCites and has presented at such conferences as IEEE VLSI Test Symposium, MEPTEC Road to Chiplets, and the Technology Unites Global Summit.