Paper Title: New Approach to Die-to-Die Memory Chiplet Interconnect

Paper Abstract: Generative AI, with its huge demand for top performance, requires chiplets containing banks of high-speed memory close to processors. This architecture is essential to breaking through the so-called memory wall (limitations on memory bandwidth and capacity). However, the typical silicon interposer is not large enough to accommodate all the memory that today’s packages could hold. A new approach, called Universal Memory Interface (UMI), provides high-bandwidth D2D connectivity between compute and memory chiplets. It works with standard packaging (no interposer) to implement both high-speed transfers and in-memory computing.

Paper Author: Ramin Farjad, CEO, Eliyan

Author Bio: Ramin Farjad is CEO of Eliyan, a company focused on next generation chiplet-based system-in-package (SiP) solutions. He was previously the CTO/VP Networking/Automotive PHYs at Marvell, in charge of developing connectivity technologies for autonomous vehicles, hyperscale data centers, and heterogenous SiP Integration. Before that, he was Co-Founder/VP Technology of Aquantia, where he focused on Ethernet PHY technologies. Ramin has pioneered several signaling schemes adopted as international standards, such as PAM4 SerDes (IEEE 802.3cd), Multi-Gig Automotive Ethernet (IEEE 802.3ch), Enterprise Ethernet (IEEE 802.3bz), and the BoW die-to-die connectivity scheme at OCP. He is the author of over 130 granted/pending patents. He earned a PhD in electrical engineering from Stanford University.