Paper Title: Extending Chiplet-Based Solutions from 2.5D to 3D

Paper Abstract: Chiplet-based architectures are now common in CPU, GPU, AI and networking applications. They typically involve 2.5D (CoWoS) and 3D (SoIC) advanced packaging technologies, enabling high density, high bandwidth, low power and latency interfaces. New chiplet bridges for intra-chip buses such as AXI and CHI have been developed using UCIe Streaming Protocol. They are optimized for high traffic density, low power, low data transfer latency, and efficient end to end flow control, facilitating seamless transition from single chip NoC to chiplet architecture. 3D packaging removes the restriction of chiplet interface location from die edges, making the interconnect low latency, low power and very dense. New 3D interface IP achieves much higher bandwidth and lower latency and much lower power than a 2.5D interface. 3D technology allows systems combining huge processing power and vast memory, with each component created in the most efficient process node.

Paper Author: Igor Elkanovich, CTO, Global Unichip (GUC)

Author Bio: Igor Elkanovich is GUC's CTO, responsible for driving IP and methodology development using advanced silicon process and packaging technology, and supervising definition and execution of large-scale projects. He focuses on applications in AI, HPC, xPU and networking. Under his leadership, GUC has developed chiplet and HBM interface IP products that have won Best IP EE Awards for three consecutive years. He has over 30 years of state-of-the-art technical management experience with such companies as Broadlight, Infineon, and Freescale. He earned an MSEE from Baku University (USSR) and holds over 25 patents.