Paper Title: Using a System-Level Model to Evaluate Heterogeneous Chiplet Architectures

Paper Abstract: Today’s complex chip designs at leading-edge nodes generally consist of multiple dies (or chiplets). The approach allows for dies from different manufacturers or processes, as well as reusable IP. Designers need a system-level model to evaluate different implementations of such complex situations. An example system consists of an I/O chiplet, low power core chiplet, high-performance core chiplet, audio-video chiplet, and analog chiplet, interconnected using the Universal Chiplet Interconnect Express (UCIe) standard. Our team considered several scenarios and configurations including advanced and standard packages, varied traffic profiles and resources, and a retimer to extend the reach and evaluate events on timeout. Identifying the strengths and weaknesses of the UCIe interconnect for mission applications helped us obtain the optimal configuration for each subsystem to meet performance, power, and functional requirements.

Paper Author: Deepak Shankar, Vice President Technology, MIRABILIS DESIGN

Author Bio: Deepak Shankar is the Founder and Chief Technologist at Mirabilis Design, an EDA company. He has worked with customers on architecture exploration for over 150 semiconductor designs. He has presented at 50+ conferences on semiconductors, electronics, embedded systems, networks, and real-time software. His projects include AI processors, FPGAs, data center connectivity, automotive autonomous driving systems, and network switches. He has designed AI workloads, software benchmarks, and traces that provide a complete evaluation of the system. He created the first system modeling and simulation software that integrates model-based systems engineering with product development flow. He earned an MSEE from Clemson University (South Carolina).