Paper Title: Choosing the Right Package for Your Chiplet Application

Paper Abstract: Packaging choices abound for chiplet-based designs. For AI applications, the leading choices are silicon interposers and molded embedded bridge interposers. For partitioning of processors and SoCs, they are fan-out and package-on-package. For flash and analog disaggregation in microcontrollers, innovative panel-level fan-out options for BGA and QFN are the leaders, along with conventional substrates or lead frames. An analysis shows that molded embedded bridge interposers, package-on-package, and panel-level fan-out options for QFN are the best choices.

Paper Author: Craig Bishop, Senior Engineer, Deca Technologies

Author Bio: Craig Bishop is CTO at Deca Technologies, where he works on the Adaptive Patterning technology, EDA development, intellectual property, and R&D. He is the architect of Adaptive Patterning, having developed the relevant technology and design methodologies. This approach has been implemented in high-volume production, today producing more than 5 million devices per day. Bishop earned a BSEE from the University of Arizona with specialization in analog IC design. He holds over two dozen patents related to fan-out and electronic interconnect. He has also described adaptive patterning at many conferences including IEEE Electronic Components and Technology Conference (ECTC).