Paper Title: Evaluating Technical Approaches to Heterogeneous Integration

Paper Abstract: Designing with chiplets requires a new step called heterogeneous integration, in which dies are integrated into a package and interconnected via a substrate. High bandwidth and low latency communications are essential to minimize performance losses compared to a monolithic approach. There are three common ways to integrate the chiplets: silicon interposers, Re-Distributing Layer (RDL) with integrated silicon bridges, and RDL interposers. The integrated silicon bridge option costs less than the silicon interposer approach. Although silicon interposers/bridges provide fine-pitch interconnects, new high-resolution polymers allow the routing of high-density interconnects directly on the RDL interposer. An example uses a 500nm line width/spacing RDL technology with pitch scaling on the number of routing layers. This approach is an excellent alternative to silicon interposers and bridges.

Paper Author: Nicolas Pantano, Principal MTS, imec

Author Bio: Nicolas Pantano is a Principal Member of Technical Staff at imec, where he works on high-bandwidth electrical and optical interconnects for 2.5D/3D integrated systems. He has 21 publications, including an article in the Journal of Lightwave Technology and conference presentations at ECTC, ECOC, EOS/ESD Symposium, and the IEEE Symposium on VLSI Technology. He earned a PhD in electrical engineering from KU Leuven (Belgium), comparing electrical versus optical communication for high bandwidth in-package communications.