Paper Title: Taking Full Advantage of UCIe in Chiplet Design

Paper Abstract: The Universal Chiplet Interconnect express (UCIe) standard enables seamless interoperability and connectivity between dies without reducing performance. It also delivers benefits such as lower power consumption, fault tolerance, and software interoperability. Design and verification engineers must approach UCIe cautiously because of its many advances over previous interfaces. Among the features likely to be new to designers is a complete stack including physical layer, die-to-die adapter layer, and protocol layer. Another major one is the use of clock forwarding and single-ended, low voltage, DDR signaling to improve power efficiency. Key design decisions include retry buffer sizing, fault tolerance, and latency considerations, as well as bandwidth and power.

Paper Author: Luis E. Rodriguez, Solutions Architect, Siemens EDA

Author Bio: Luis E. Rodriguez is a Solutions Architect/UCIe Verification IP Architect at Siemens EDA. He currently works on architecture and development of UCIe Verification IP and finding synergies between it and other Siemens tools. He has previously developed verification IP for PCIe, CXL, and NVMe. He earned an MS in computer science from the National Taiwan University.