Paper Title: Efficient Transport in Chiplet-Based AI/ML Applications

Paper Abstract: Yield issues for chips at leading-edge nodes are causing a design transition from SoCs to chiplets. AI/ML applications are a key driver because of their complexity and the scalability of their computing architectures. The protocol layer with network-on-chip (NoC) protocols such as AMBA AXI and CHI is a key ingredient in creating interoperable chiplets and “Super-NoCs” that coordinate data transport. With computing throughput growing faster than memory bandwidth, data transport architecture is critical for successful AI/ML applications. Requirements from AI/ML inferencing and generative AI applications provide a basis for evaluating chiplet-based architectures. NoCs must help optimize performance, power, and cost. Example designs from ADAS and AI/ML applications illustrate new efficient NoC IP that allows for early architecture optimization and physically-aware connections to industry-leading digital implementation flows.

Paper Author: Frank Schirrmeister, CEO, Arteris IP
Guillaume Boillet, Sr Director Product Management, Arteris IP

Author Bio: Frank Schirrmeister is VP Solutions/Business Development at Arteris IP, where he leads activities in automotive, enterprise computing, consumer, communications, and industrial applications and in artificial intelligence, machine learning, and safety technologies. A well-known leader in the EDA industry, he has played a key role at many major conferences, including being the Engineering Track Chair for the 2024 Design Automation Conference (DAC). He has also written many technical articles in media such as Semiconductor Engineering, EDACafe, and Design&Reuse. Before joining Arteris IP, Frank held management positions at Cadence Design Systems and Synopsys, focusing on product marketing and management, solutions, strategic ecosystem partner initiatives, and customer engagement. He earned a BSEE equivalent from the Technical University of Berlin (Germany).

Author 2 Bio: Guillaume Boillet is Sr Director Product Management/Strategic Marketing at Arteris, where he works on a wide range of semiconductor IP products. Before joining Arteris, he held management and marketing positions at Synopsys and Mentor Graphics. He has written articles in media such as Semiconductor Engineering, EDN, and Design&Reuse and has given presentations at industry events such as the Linley Fall Processor Conference. He earned MSEEs from CentraleSupec (France) and École Polytechnique de Montreal (Canada) and an MBA from Grenoble Ecole de Management (France).