Wednesday, February 7th
4:30-5:30 PM
A-103: Design - 2 (Design/Security Track)
Paper Title: Reducing Upfront Costs to Accelerate Chiplet Adoption

Paper Abstract: Chiplets are getting a lot of attention, but major barriers still hinder usage. Development often costs millions of dollars and takes years to complete. Off-the-shelf chiplets aren’t currently available and, even if they were, would still require custom packaging, integration, and test. What is needed is a simple platform with a programmable controller (typically an FPGA), a high-speed die-to-die interface, and a family of basic pre-packaged chiplets such as processor, memory, AI acceleration, networking, and I/O. It would include a set of design, debug, and test tools. Designers could then build their chips from combinations of basic pre-packaged chiplets known to be fully-tested, compatible, and highly secure. They could also add other functionality as needed to work with the controller. Upfront costs are minimal, adoption is frictionless, and time-to-market is a few months.

Paper Author: Kash Johal, CEO, YorChip

Author Bio: Kash Johal is the CEO of YorChip developing Chiplets for Mass Markets. Previous worked at multiple IP and ASIC startups for past 35 years with multiple exits.