Paper Title: Wafer Level Technologies for Heterogeneous Chiplet Integration

Paper Abstract: Heterogeneous integration is a key technology for making electronic systems more efficient, smaller, and more functional. It combines different types of devices and materials into a single package. Several approaches are currently in use, including 2.5D interposer, 3D wafer-level integration (W2W and D2W), and sequential 3D integration. Today, there is a growing need to implement heterogenous integration for chiplets in applications ranging from advanced 3D SoC to photonics and quantum computing. CEA has developed a variety of heterogeneous integration technologies enabling higher performance, reduced size, and lower power consumption. The technologies have successfully produced known good dies and achieved high throughput and yield.

Paper Author: Sylvie Joly, Partnerships Manager 3D Integration and Packaging, CEA-List

Author Bio: Sylvie Joly is 3-D Integration and Marketing Partnerships Manager at CEA-LETI, where she works on such topics as wafer-to-wafer and die-to-wafer bonding, chiplets, interposers, and TSV technology. Before joining CEA, she was an R&D engineer and sales engineer at several companies including Hewlett Packard and Ericsson. She has given presentations at Photonics West and Leti Innovation Days. Sylvie earned an MS in Microelectronics from ISEP (Institut Supérieur d'Electronique de Paris) and a Master’s in Marketing and Innovation from the Grenoble Ecole de Management (GEM).