Paper Title: Early Predictive Mechanical Analysis Workflow for Chiplet-Based Designs

Paper Abstract: The emergence of chiplets has led to new challenges in ensuring mechanical reliability. Now systems may include chiplets with varied material properties, thermal coefficients, and mechanical behavior. Existing mechanical simulation packages cannot handle such situations. A new package has been developed that allows for regions with differing characteristics. It provides special transition areas that connect the regions and produce fully validated results. Representative examples show how the new package works in practice.

Paper Author: Subramanian Lalgudi, , Siemens EDA

Author Bio: Subramanian Lalgudi is a multi-physics solutions architect at Siemens EDA where he focuses on emerging areas such as 3-D ICs and power electronics. A leader in engineering simulation, he previously managed circuit simulation R&D at Ansys. He has participated in many conferences such as the International Integrated Reliability Workshop and the Conference on Electrical Performance of Electronic Packaging (EPEPS) and has 11 publications including an article in IEEE Transactions on Components, Packaging, and Manufacturing Technology. He earned a PhD in electrical engineering from Georgia Institute of Technology. About the Co-Authors; Lihong Cao is Sr Director Marketing/Engineering at ASE Group, where she is responsible for advanced packaging technology development for chiplets. She also works on heterogeneous integration, strategic planning, and business engagement. She led engineering operations for advanced SiP and Fanout Embedded Si Bridge technology. She was previously a Sr Manager at AMD, where she was a key contributor to TSV 2.5D/3D solutions. She holds several US patents, has published more than 70 technical papers, and has presented at many international conferences such as the Wafer-Level Packaging Symposium and the International Conference on Device Packaging. She earned a PhD in materials science and engineering. David Ratchkov is the CEO of Thrace Systems, a startup developing tools to handle early chiplet architecture exploration and design needs, such as 3DIC physical planning, netlist design, power, and thermal. An experienced hardware and software developer, he was previously a Principal Engineer at Broadcom, where he developed power analysis tools. He also leads the Chiplet Design Exchange (CDX) workstream under Open Compute Platform's Open Domain-Specific Architecture (ODSA) sub-project. He earned a master’s degree in mathematics and computer science from the University of Plovdiv (Bulgaria).