Paper Title: Early Predictive Power Integrity Analysis for Chiplet-Based Designs

Paper Abstract: Advanced packaging can greatly influence the power integrity (PI) requirements of chiplets and SiPs. The evaluation of PI thus must begin in the early development stages. Due to inherent limitations in the information available then, predictive, non-layout-based simulations are the best way to identify early PI concerns. However, existing workflows for PI simulation were developed primarily for monolithic designs, and thus are not readily applicable to chiplets. For example, chiplets may uitilize different process nodes (such as 16 nm for transceivers and 5nm or below for logic), thus having different power-supply voltages leading to different noise budgets as well. A new predictive PI analysis workflow can handle chiplet-based designs. Typical examples illustrate the approach and show the results of predictive PI simulations.

Paper Author: Subramanian Lalgudi, , Siemens EDA

Author Bio: Subramanian Lalgudi is a multi-physics solutions architect at Siemens EDA where he focuses on emerging areas such as 3-D ICs and power electronics. A leader in engineering simulations, he previously managed circuit simulation R&D at Ansys. He has presented at many conferences including the International Integrated Reliability Workshop and the Conference on Electrical Performance of Electronic Packaging (EPEPS) and has 11 publications including an article in IEEE Transactions on Components, Packaging, and Manufacturing Technology. He earned a PhD in electrical engineering from Georgia Institute of Technology. Co-Author Information: John Caka is a Signal Integrity Field Application Engineer at Siemens EDA. Before joining Siemens, he was a signal integrity engineer at Micron. John earned a BSEE from the University of Utah. Jawad Nasrullah is CEO of Palo Alto Electron, a startup focused on heterogeneous integrated circuits and 3D-ICs for performance computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a PhD in electrical engineering at Stanford, has 6 publications, and holds 14 patents.