Paper Title: Integrating Chiplets into Large SiP Systems

Paper Abstract: IC design scaling has been done mostly through technology scaling, a process called design-technology co-optimization (DTCO). As the pace of IC technology scaling has slowed recently, a new process called system technology co-optimization (STCO) is extending design scaling. STCO enables early architectural and technology tradeoffs to achieve high-performance, cost-effective solutions quickly. Predictive analysis is a basic component of STCO that leverages high-level modeling and analysis during planning. Another new issue in the chiplet age is the need for designers to be more aware of requirements such as substrates, materials, and assembly. As soon as architecture-level discussions begin, the design team must decide how the chiplets will be put together. Issues include the choice of a substrate and an interposer, assembly methods and compatibility problems, and design-for-manufacturing approaches that will control costs and meet foundry requirements.

Paper Author: David Ratchkov, CEO, Thrace Systems

Author Bio: David Ratchkov is the CEO of Thrace Systems, a startup that has developed tools to aid in early chiplet architecture exploration and design stages, such as 3DIC physical planning, netlist design, power, and thermal. An experienced hardware and software developer, he was previously a Principal Engineer at Broadcom, where he developed power analysis tools. He earned a masters degree in mathematics and computer science from the University of Plovdiv (Bulgaria). He also leads the Chiplet Design Exchange (CDX) workstream under Open Compute Platform's Open Domain-Specific Architecture (ODSA) sub-project.