Paper Title: Functional Simulation and Verification Workflow for Chiplet-Based Systems

Paper Abstract: As chiplet-based designs become commonplace for high-performance chips, establishing robust connectivity among chiplets is critical to optimizing system performance and functionality. Standards such as JEDEC JEP 30 and CDXML help address the need. JEP 30 targets 3D stacking and advanced packaging, providing specifications for key interfaces such as UCIe and BoW. OCP’s CDX group is currently developing a functional simulation and verification workflow for system integration. It will describe the simulation environment and tools used to verify system-level functionality and performance of the interface protocols. Test strategies, functional coverage closure, and performance simulations help in validating the interoperability and targets of JEP 30 in a system implementation. The description includes efforts to integrate UCIe and BoW bump interfaces into the JEP 30 workflow for functional simulation and post-silicon validation. Future plans include verification of multi-chiplet system bring-up and using generative AI with the standard format to automate repetitive tasks such as creating test cases.

Paper Author: James Wong, CTO, Palo Alto Electron
Jawad Nasrullah, CEO, Palo Alto Electron

Author Bio: James Wong is CTO at startup Palo Alto Electron, where he develops high-performance chiplets and chiplet design tools. He previously worked at zGlue, Oracle, Cisco, and Intel. James has made significant contributions to chiplet design and standardization projects such as the OCP CDXML, OCP chiplet models/integration workflow, and JEDEC JEP 30. He holds dual master's degrees in Computer Science and Electrical Engineering from the University of Michigan and the National University of Singapore, and has authored several influential industry publications.

Author 2 Bio: Jawad Nasrullah is CEO of Palo Alto Electron, a startup focused on doing research on heterogeneous integrated circuits and developing 3D-ICs for performance computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a PhD in EE at Stanford, has 6 publications, and holds 14 patents.