Tuesday, February 6th
8:30 AM-12:00 PM
Pre-Conference Tutorial D: Interfaces (Section 1) (Pre-Conference Tutorials Track)
Organizer: James Wong, CTO, Palo Alto Electron

Paper Title: Efficient Monitoring, Test, and Repair of UCIe Links for Multi-Die Systems

Paper Abstract: Reliable die-to-die connectivity is critical as designers adopt multi-die systems as the solution for large chips at the latest process nodes. UCIe is a popular standard, offering support for all packaging options and a complete protocol stack. However, designers must ensure the system’s and the link’s health and reliability throughout the product lifecycle. UCIe monitoring, test, and repair features expand test coverage of both individual dies and the entire multi-die system. The early results from an application implemented in two configurations illustrate the requirements. The first option leverages a UCIe-based die-to-die interface with monitoring, test, and repair capabilities, while the second leverages a standard GPIO interface with the IEEE 1838 test access infrastructure to allow intra-die lane testing.

Paper Author: Yervant Zorian, Chief Architect/Fellow, Synopsys
Sandeep Goel, Academician/Director, TSMC

Author Bio: Yervant Zorian is a Chief Architect and Fellow at Synopsys, where he works on IC testing and test standards. He has received many awards for his work in testing, including the IEEE Distinguished Services Award, the IEEE Circuit and Systems Society Industrial Pioneer Award, and the IEEE Hans Karlsson Standards Award. Before joining Synopsys, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He holds 35 US patents and has published over 350 refereed papers and authored four books. He earned a PhD in electrical engineering from McGill University (Canada).

Author 2 Bio: Sandeep Goel is an Academician/Director with TSMC where he works on design, content planning, and solving testing/verification/defect diagnosis challenges for advanced process test chips and test solutions for packaging. He has co-authored multiple book chapters, published over 90 conference papers, and holds over 90 US patents. He has also served on many conference committees at such events as DAC, ITC, and DATE. He earned a PhD in electrical and computer engineering from the University of Twente (Netherlands).