Paper Title: Chiplet Markets Are Rising: Where and When?

Paper Abstract: All major chipmakers have adopted chiplets as their approach for smaller design nodes. However, the advantages of chiplets over monolithic designs depend on many factors and are difficult to evaluate. Factors include front-end wafer cost, silicon area used up by overhead (such as interconnect and power distribution), disaggregation and integration costs, and more complex packaging and test processes. A new model simulates the cost differences between monolithic and chiplet approaches. It predicts which SoCs will benefit most from chiplets. Analysts can use the model to identify applications where chiplets offer the largest gains and designers are most likely to turn to them.

Paper Author: Tom Hackenberg, Principal Analyst, Yole Group
Ying-Wu Liu, Technology/Cost Analyst, Yole SystemPlus

Author Bio: Tom Hackenberg is a Principal Analyst for Computing and Software at Yole Group. He is an industry leading market reporter for semiconductor processors (including GPUs and DPUs), FPGAs, and configurable processors. He also covers related technology trends including AI and edge computing, IoT, heterogeneous processing, and chiplets, as well as key markets such as automotive, high-performance computing, and telecommunications. Tom has presented at many important events such as the OCP ODAS Workshop on Chiplets, System-on-Chip Conference, Vision and AI Summit, and Xilinx Adapt. He has also been quoted or referenced in such publications as Cision, Computerworld, Design and Reuse, EE Times, Fierce Electronics, Semiconductor Engineering, and VentureBeat. Tom has worked with market-leading processor suppliers developing both syndicated and custom research. He earned a BSEE/BSECE from the University of Texas at Austin specializing in processors and FPGAs.

Author 2 Bio: Ying-Wu Liu is a Technology/Cost Analyst at Yole System Plus, where she develops reverse engineering and costing reports. She has set up analyses of innovative IC chips and has provided research on patterning methods and ADAS systems. Previously she was an R&D engineer at Vanguard International Semiconductor, a foundry services company closely linked to TSMC. She earned an MS in physics from the National Tsinghua University (Taiwan) and a master’s In Integration, Security, and Trust in Embedded Systems from the Grenoble INP, ESISAR (France).