Paper Title: Developing Low Cost Chiplet Packages

Paper Abstract: Chiplets, small IC dies with specialized functions that designers can combine to form complex chips, are an attractive solution for advanced silicon process nodes. However, packaging them at a reasonable cost leads to many challenges. Several approaches are widely available, including fine line and space standard substrate, Si interposer, redistribution layer (RDL) interposer, and embedded bridge die in RDL interposer. An analysis of the processes and technologies shows that the RDL interposer currently offers the best cost-performance tradeoffs.

Paper Author: Nokibul Islam, Director Group Technology Strategy, JCET Group

Author Bio: Nokibul Islam is currently Sr Director WorldWide Field Applications Engineering at JCET, where he leads business development for network, computing, communications, and automotive products. Before joining JCET, he was a staff engineer at Amkor, where he led work on advanced packaging. Islam has authored 50+ published papers and articles on electronic packaging, manufacturing, and reliability. He has received many best paper awards and certifications from ECTC (IEEE), IMAPS, and other organizations. He earned a PhD in mechanical engineering from Auburn University (AL).