Thursday, June 15th
|A-201: Network Acceleration 2 - High-Performance Systems (Networking Track)
Paper Title: FPGA-Based SmartNICs Process Packets at 400 Gbps+
Paper Abstract: With networks moving to much higher speeds, FPGA-based SmartNICs have become a popular way to accelerate packet processing. However, developing applications for 400 Gbps wire-speed and higher presents major challenges, including limited resources and the need for specialized knowledge of both FPGA and network programming. An example solution, based on a general-purpose FPGA accelerated SmartNIC and the DPDK toolkit, can do wire-speed packet processing at 400 Gbps and beyond. A performance evaluation utilizing real hardware shows the benefits of FPGA acceleration for various use cases. The solution is flexible, and designers can customize and adapt it for a wide range of network applications on varied hardware platforms.
Paper Author: Lukas Kekely, CTO, BrnoLogic
Author Bio: Lukas Kekely is the CTO of BrnoLogic, an FPGA design house. He leads a team of developers creating an innovative FPGA product that helps software developers working on high-speed network applications. Lukas has over ten years experience managing research and application projects in FPGA acceleration technology. Before joining BrnoLogic, he was a design architect at CESNET, where he led R&D teams creating FPGA-based solutions for network perimeter security and accelerated lawful interception devices. He has received several prestigious awards, including the Werner von Siemens Award for technical sciences and the Czech Republic Minister of the Interior Award for security research. He has published 16 conference papers at such important venues as the International Conference on Field-Programmable Technology (ICFPT), the Euromicro Conference on Digital System Design (DSD), and IEEE Infocom. He earned a PhD in information technology at the Brno Institute of Technology (Czech Republic) and has been a professor there.