Paper Title: Removing the Tail from SmartNIC Latency

Paper Abstract: Software-based systems often suffer from occasional long processing delays (so-called tail latency). Such delays can lead to lost packets, data corruption, and even system shutdown due to long-lasting recovery procedures. Regardless of whether the software runs on a host processor or an offload engine, packets may run into delays caused by a cold cache, busy bus, or contention in accessing a shared resource. The solution is to offload time-critical packet processing functions to completely separate logic such as a SmartNIC. Dedicated packet processing circuits and parallel memories allow packets to move through pipelines with deterministic latency. Several example SmartNIC applications illustrate the offloading of time-critical functions to logic to avoid application delays. .

Paper Author: John Lockwood, CEO, Algo-Logic

Author Bio: John Lockwood is the CEO/founder of Algo-Logic, a developer of low-latency networking for financial applications, data center networks, in-memory databases, and real-time systems. The company’s customers include international banks, trading firms, and exchanges. Before founding Algo-Logic, he managed the NetFPGA project at Stanford and was a professor at Washington University in St. Louis. He has also been a consultant to SAIC on FPGA-accelerated networks. He has published over 100 papers and patents on topics related to networking with FPGAs and served as served as principal investigator on dozens of federal and corporate grants. He earned a PhD in Electrical and Computer Engineering from the University of Illinois at Urbana/Champaign and has spoken at many important conferences