Paper Title: Using SmartNICs in 5G Networks

Paper Abstract: 5G networks must handle multiple services and protocols at the edge with low latency (to avoid packet drops) and high performance. Both services and protocols may vary with both time and location to allow for rapid rollout of services and customization for local needs and network evolution. FPGA-based SmartNICs offer an efficient solution, providing low latency, high throughput, and considerable flexibility. They can address the requirements of 5G xHaul and access networks, including acceleration and termination of multiple services. Hard and soft acceleration IPs and corresponding programming tools (such as the P4 switch programming language) allow efficient development with short turnaround times. The use cases for adaptable FPGA-based SmartNICs include acceleration of RAN functionality in 4G/5G basestations including both distributed and centralized units, implementation of security acceleration functions such as L3-VPN and virtual firewalls, and custom packet processing.

Paper Author: Awanish Verma, Director/Principal Architect, AMD

Author Bio: Awanish Verma is Director/Principal Architect at AMD, where he develops solutions for next generation wired, wireless, and data center networks. His focus is on networking system design with FPGAs and ASICs. Before joining AMD/Xilinx, he worked at Netronome and Cisco. He earned a Bachelor of Technology degree in electrical, electronics, and communications engineering from HBTI Kanpur (India). He has over 25 years experience in the communications, networking, and FPGA areas. He has spoken at several conferences including OFC and FPGA Conference Europe, and was a keynoter for the Network for Data-Intensive Science (INDIS) Workshop at the Supercomputing (SC) Conference.