Paper Title: Performance and Reliability Monitoring of Die-to-Die Interfaces

Paper Abstract: Heterogenous integration of chiplets requires a high-performance die-to-die interface. Such interfaces are subject to many issues, including latent defects in the underlying interposer. Once the dies are assembled, there is no practical way to assure that all the connections are fully functional. A new monitoring solution for heterogeneous packaging, based on chip telemetry, combines deep data with machine learning algorithms. It uses data analytics on the cloud and at the edge, where the data is processed to provide actionable insight. The approach provides per-lane grading, advanced outlier detection, and spare lane swapping during characterization and test, allowing service providers to monitor the interconnects in the field. Initial results and conclusions from a commercial chip that has integrated the technology show excellent results.

Paper Author: Nir Sever, Sr. Director, Business Development at proteanTecs, proteanTecs

Author Bio: Nir Sever is Sr Director Business Development at proteanTecs, the leading provider of deep data analytics for advanced electronics monitoring. He focuses on finding innovative approaches to product development and marketing. Before joining proteanTecs, he was Chief Operating Officer at Tehuti Networks, a developer of high-speed networking chips. He has also been Sr Director of VLSI Design and Technologies at Zoran, where he was responsible for driving silicon technologies and delivering over 10 new silicon products annually. He has extensive experience with VLSI design with specialties in design methodologies, EDA tools, and physical design. He chairs the Technical Committee of Synopsys Users Group (SNUG) Israel, and has been a member of the Technical Committee for several EDA user group conferences. He earned a BSEE from The Israel Institute of Technology, Technion.