Wednesday, January 25th
03:15-4:15 PM
A-102: Applications (Design/Packaging/Interfaces/Applications Track)
Paper Title: Chiplet-Based Switch SoC for CXL Resource Pooling

Paper Abstract: The new CXL interface standard will eventually be the best way to create composable infrastructures that allocate compute, networking, storage, and accelerators to workloads as needed. The result will be a tremendous return-on-investment and great flexibility and efficiency in managing resources. However, CXL currently lacks the required features for resources other than memory. A new switch SoC (SSoC) can provide the features immediately. A proposed architecture based on chiplets offers an efficient way to implement the SSoC. Large data centers and clouds can thus enjoy the advantage of composable infrastructure now without having to utilize lower-speed buses and accept other limitations that reduce both ROI and performance at scale.

Paper Author: Shreyas Shah, Founder, CTO and Chief Scientist,

Author Bio: Shreyas Shah is the Founder/CTO of, a startup that is creating composable infrastructures based on CXL that serve the needs of enterprises, clouds, and edge data centers. Before founding, Shre was a Principal Engineer at Intel designing packet processing pipelines for Ethernet switches. He has also been a Cloud FPGA Architect at Xilinx. Shre holds 16 patents with 5 more pending and is a member of the Open Networking Foundation (ONF) Chip Advisory Board. He earned a Master of Technology in signal processing and communications at IIT Bombay.