Paper Title: Bringing Persistent Memory to Chiplets

Paper Abstract: Adding high performance persistent memory such as Nantero’s NRAM to a chiplet solution allows SoC providers to avoid the data checkpointing required by ordinary DRAM. On-chip persistent main memory has many benefits, including automatic data storage immune from power loss risks, high levels of security, low power, and enhanced system performance. Consistency between CXL solutions and UCIe ones allows solution providers to use a common design for system and chiplet-level implementations bringing large amounts of DRAM-class persistent memory to new designs.

Paper Author: Bill Gervasi, Principal Systems Architect, Nantero

Author Bio: Bill Gervasi is Principal Systems Architect at Nantero, a developer of carbon-nanotube memory. He has been a chairman of the JEDEC international standards organization working on memory and storage standards for over 25 years. Best known for his key role in the widely used DDR memory standards (DDR3, DDR4, and DDR5), he received the JEDEC Award of Excellence for his dedication to standards development work. He has also been an expert witness and an instructor in memory design. He has presented at many conferences, including Hot Chips, Storage Developer Conference, Flash Memory Summit, International SoC Conference, and the Salishan Conference on High-Speed Computing. He is often quoted in the trade and technical press, including EE Times and other media. He holds 10 patents in memory design. He studied computer science and computer engineering at the University of Portland and the Oregon Graduate Research Center.