Paper Title: Designing for Power, Performance, and Area (PPA) for Multi-Die and 3D ICs

Paper Abstract: The semiconductor industry's ability to coax ever more performance out of computer chips has produced the most significant innovations of our modern era. But we are beginning to test the limits of how much we can squeeze into a single piece of silicon. Multi-die design and 3D stacking offer higher performance with increased density and energy efficiency in a smaller physical form factor. Transitioning from single to multi-die design and technology options requires the discovery of optimal solutions for PPA among multiple chiplets and 3D ICs.

Paper Author: Kenneth Larsen, Director Product Marketing, Synopsys

Author Bio: