Paper Title: State of Chiplets Today

Paper Abstract: Chiplets promise lower costs and shorter time-to-market for big chips at today’s smallest nodes. Designers must divide the chip into pieces and later put them back together in a package with a high-speed interface connecting them. This approach results in chiplets that are small, easy to manufacture, and less likely to have defects. The new steps are die disaggregation (dividing the chip into chiplets) and heterogeneous integration (combining chiplets that differ in size, technology, and origin). They require extra time and new design tools. Test and manufacturing may also drag, and more use of design-for-test and design-for-manufacturing is necessary. To actually drop in chiplets from older technologies, IP, or third-party sources involves new standards and marketplaces.

Paper Author: Jawad Nasrullah, CEO, Palo Alto Electron

Author Bio: Jawad Nasrullah is CEO of Palo Alto Electron, a startup focused on doing research on heterogeneous integrated circuits and developing 3D-ICs for performance computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a PhD in EE at Stanford, has 6 publications, and holds 14 patents.