Tuesday, January 24th
08:30-Noon
Pre-Conference Tutorial C: Advanced Packaging Methods (Pre-Conference Tutorials Track)
Organizer: Lihong Cao, Director Engineering, ASE Group

Paper Title: Practitioner's View of Chiplet Packaging

Paper Abstract: Overview of chiplet packaging from a practitioner who has taped out almost 1,000 packages with an over 99% first-time tape-our success rate.

Paper Author: Larry Zu, President, Sarcina Technology

Author Bio: Larry Zu is the founder/CEO of Sarcina Technology, where he designs advanced semiconductor packages to achieve first tape-out success through rigorous chip-package-board co-design and co-simulation. He also specializes in product engineering for wafer and assembly yield enhancement, Q&R, and supply chain management. Before founding Sarcina Technology, he worked on processor projects at Bell Labs, DEC, Intel, and TSMC. He has taped out almost 1,000 packages with an over 99% first-time tape-our success rate. He earned a PhD in electrical engineering from Rutgers University (NJ). He has many refereed IEEE publications and holds multiple patents used in leading US companies’ key products.