Tuesday, January 24th
01:00-5:00 PM
Pre-Conference Tutorial F: Power and Thermal (Pre-Conference Tutorials Track)
Organizer: Andras Vass-Varnai, Portfolio Development Executive, Siemens EDA

Paper Title: Large System Design of a 6-Chiplet Based Architecture

Paper Abstract: Chiplets have rapidly become the mainstay approach to very large chips at very small dimensions. All the major chip companies are now using them to achieve lower cost, shorter time-to-market, and easier scaling and upgrades. An example offers a detailed overview of a large system design of a 6-chiplet based 96-core architecture. It focuses on the design methodology, disaggregation, and power management, interconnect, and DFT blocks.

Paper Author: Pascal Vivet, Scientific Director, CEA-List

Author Bio: Pascal Vivet is Scientific Director of the Digital Systems and Integrated Circuits Division of CEA-LIST and co-director of the IRT Nanoelectronics Smart Imager program. His research interests include wide aspects of circuit and system level design, such as system integration, multi-core architecture, Network-on-Chip, energy efficient design, and related CAD design aspects. He focuses on advanced technologies such as 3D integration, nonvolatile memories, and photonics. He has been a project leader for 3D circuit design and integration. He is an active participant in many conferences such as ASYNC, DATE, 3DIC, and ISLPED. He was an organizing committee member for the 3D workshops series at DATE, the D43D workshops, and the 3DIC conference. He has authored and co-authored more than 120 papers and holds several patents in digital design. He earned a PhD at the University of Grenoble Alpes (France).