Paper Title: Simplifying Chiplet Interconnect Development with Interface IP

Paper Abstract: Chiplet-based design of large chips has many advantages, but it also adds a difficult integration stage to the process. A key new issue is the need for a die-to-die interface to interconnect the chiplets. This interface requires a completely new approach, typically based on the emerging UCIe or BoW standards. Both are very complex, and are in their early development. Obviously, designers end up in the difficult position of creating an interface with little to go on. The easy solution is to use commercially available IP. Now the designers can take advantage of a proven source of IP created by engineers who have been fully involved with the technology since its beginning. The designers can then focus on the areas that are their core competencies and leave interface development largely to specialists.

Paper Author: Manmeet Walia, Director Product Marketing, Synopsys

Author Bio: Manmeet Walia is Director of Product Marketing for Mixed-Signal PHY IP at Synopsys. He has over 20 years of experience in product marketing, product management, and system engineering covering ASSP, ASIC, and IP products for a broad range of applications. Manmeet earned an MSEE from the University of Toledo (OH), and an MBA from San Diego State University. He has written technical articles for journals such as Embedded System Design and Semiconductor Engineering and has presented at conferences such as IP-SoC Days, the International SoC Conference, Synopsys User Group (SNUG), and DesignCon.