Paper Title: Annual Update on Test of Multi-Die Designs

Paper Abstract: With the growth of heterogeneous integration and advanced packaging for multi-die designs, the test and repair of 2.5D and 3D designs has become a key driver in new product development. Factors to consider for test and repair of multi-die designs include access for testing and repair, known good dies and assemblies, test costs, and Silicon Lifecycle Management (SLM) and analytics. Test challenges for chiplets and multi-die designs include interfaces for improved test access bandwidth, die-to-die interface test and repair, growing use of in-system sensors and in-field monitoring, SLM analytics, and SLT (System Level Test) to address Known-Good-x (KGx) and SDCs (Silent Data Corruption).

Paper Author: Mike Ricchetti, SoC/DFT Architect, Synopsys
Yervant Zorian, Chief Architect/Fellow, Synopsys Inc

Author Bio:

Author 2 Bio: Yervant Zorian is Fellow/Chief Architect at Synopsys, where he focuses on technology roadmaps. He has over 30 years of experience in test technology including stints at Virage Logic, LogicVision, and Bell Labs. A world-leading authority on self-repairing systems, he has been the President of the IEEE Test Technology Technical Council, chair of the IEEE 1500 Standardization Working Group (Design for Testability of Embedded Cores), Editor-in-Chief of IEEE Design and Test of Computers magazine, Vice-President of IEEE Computer Society, General Chair of the 50th Annual Design Automation Conference (DAC) and General Chair of the 50th Annual International Test Conference. He holds 45 patents, has authored five books, and has published over 400 refereed papers and received many best paper awards. He is a Fellow of the IEEE, the recipient of the Industrial Pioneer Award for contributions to built-in self-test (BIST), and the recipient of IEEE’s Distinguished Services Award and Meritorious Award. He earned a PhD in electrical engineering from McGill University (Canada).