Wednesday, January 25th
03:15-4:15 PM
B-102: Test (Partitioning/Integration/Test Track)
Paper Title: DFT Architecture for Chiplet-based Systems in Package

Paper Abstract: Testing of IC design and functionality is important since it consumes 40% of their cost. Design for Testability (DFT) is a set of structured techniques developed to increase test quality and reduce cost. The complexity of chiplet-based package testing makes it essential that individual dies are very well tested (becoming so-called KGD or Known Good Dies). However, the interconnections between the dies also must be tested and guaranteed for both hard and performance related defects. The DFT architecture must be developed hierarchically. One such approach uses IEEE standards 1838 (Test Architecture for 3D ICs) and 1687 (Internal JTAG)

Paper Author: Rajesh Pendurkar, Director, Capgemini

Author Bio: Rajesh Pendurkar is a Technical Director at Capgemini, a world leader in engineering services, where he drives customer and technology development of silicon solutions for chiplet based turnkey products. He is also a founder of the technology consulting firm TriSquare Sense. He was previously DFT lead at Broadcom where he managed and drove design and productization of processors and complex SoCs for digital video. Rajesh earned a PhD from Georgia Institute of Technology and an MBA from University of Southern California. He is a senior member of IEEE, a member of the IEEE 1687 test technology standards committee workgroup, and an adjunct instructor at UCSC Silicon Valley Extension’s VLSI Engineering department.