Thursday, January 26th
02:00-3:20 PM
C-202: Highlights from University Research on Chiplets (Academic Track)
Paper Title: A New Heterogeneous Chiplet-Based Architecture for AI Computing

Paper Abstract: Demands on bandwidth, latency, and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2.5D interconnect, promise a scalable platform to meet such needs. A pathfinding study applies chiplets to implementing AI algorithms, taking advantage of in-memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. Simulations on representative algorithms (DNNs, transformers, and GCNs) provide a scaling roadmap for heterogeneous integration. A particularly promising approach is a big-little chiplet architecture that takes advantage of the non-uniform nature of AI algorithms and achieves >100X performance improvement over homogeneous design.

Paper Author: Yu Cao, Professor, Arizona State University

Author Bio: Yu Cao is a Professor of Electrical Engineering at Arizona State University, where he focuses on neural-inspired computing, hardware design for on-chip learning, and reliable integration of microelectronics. He has published many articles and two books on nano-CMOS modeling and physical design. Dr. Cao is a Distinguished Lecturer of the IEEE Circuits and Systems Society and an IEEE Fellow. He has received many awards, including five Best Paper awards and the 2020 Intel Outstanding Researcher Award. He earned a PhD in electrical engineering from the University of California Berkeley.