Paper Title: Using AI to Speed up Power Analysis for Chiplet Based Designs

Paper Abstract: DC power integrity analysis can take a long time in chiplet-based designs due to the need to include many separate units plus interconnects. One way to shorten the process is to run the power integrity tools during design to resolve problems before turning things over to the power integrity specialists. However, the PI tools are hard to use because they require the development of source and sink models as well as the running of simulations. Our “Big Rock” approach is an addition to our design tool that uses AI to create the models and run the batch simulations. Designers can then run the enhanced design tool and display the results without knowing anything about the PI tools.

Paper Author: Kendall Hiles, Sr Product Specialist High Density Packaging, Siemens EDA

Author Bio: Kendall Hines is a Sr Product Specialist for High-Density Advanced Packaging at Siemens Digital Industries Software. He focuses on customizing EDA tools and flows to add functionality, introduce new technology, and support manufacturing. He has worked recently on creating test vehicles for situations such as chiplet-based design involving many different components and methods of interconnections. He has presented approaches to such problems at the Mentor User2User Event. He has over 35 years experience in design and test engineering and has worked on ASIC, CPU, and memory designs.