Wednesday, January 25th
|B-103: Integration - 2 (Partitioning/Integration/Test Track)|
Paper Title: Using Predictive SI Analysis to Ensure Successful Chiplet Integration
Paper Abstract: As monolithic ICs exceed reticle size limits, manufacturing them becomes very expensive. Breaking a monolithic IC into smaller dies integrated in a common package is becoming the only way to make chip manufacturing economical in advanced process nodes. Each die could be designed and manufactured by a different company. For the integration to succeed, standardization of die-to-die interfaces is essential. Designing the physical interface (PHY) between dies and ensuring its signal integrity is necessary. Given how greatly the PHY choice affects the rest of the IC design, it is important to analyze the signal integrity of various system-in-package (SiP) scenarios. A new methodology for a predictive SI simulation for D2D PHY interfaces is necessary and can be based on the prior art for chip-to-chip interfaces on the PCB. Representative examples demonstrating the methodology and the results of the simulation show the approach's value in identifying signal integrity issues in SiPs.
Paper Author: Subramanian (Lal) Lalgudi, Analysis/Verification Product Specialist, Siemens EDA
Author Bio: Subramanian Lalgudi is a multi-physics solutions architect at Siemens EDA where he focuses on emerging areas such as 3-D ICs and power electronics. A leader in engineering simulations, he managed circuit simulation R&D at industry leader Ansys for many years. He earned a PhD in electrical engineering from Georgia Institute of Technology. He has participated in many conferences such as the International Integrated Reliability Workshop and the Conference on Electrical Performance of Electronic Packaging (EPEPS) and has 11 publications including an article in IEEE Transactions on Components, Packaging, and Manufacturing Technology. John Caka is a Signal Integrity Field Application Engineer at Siemens EDA. Before joining Siemens, he was a signal integrity engineer at Micron. John earned a BSEE from the University of Utah. Jawad Nasrullah is CEO of Palo Alto Electron, a startup focused on doing research on heterogeneous integrated circuits and developing 3D-ICs for performance computing. He was previously President, CTO, and Co-Founder of ZGlue, the creator of a platform for developing chiplets as well as a marketplace for distributing them. Before co-founding ZGlue, he was an engineer at Samsung Electronics, Intel, and Sun Microsystems. He earned a PhD in EE at Stanford, has 6 publications, and holds 14 patents.