Tuesday, January 24th
01:00-5:00 PM
Pre-Conference Tutorial G: Test and Integration (Pre-Conference Tutorials Track)
Organizer: Joshua Rubin, Sr Engineer, IBM Research

Paper Title: Hybrid Bonding Technology for Chiplet Integration

Paper Abstract: Hybrid bonding is an enabling technology that revolutionizes chip integration. Its major advantage is the scalable, all Cu interconnect that forms at low temperatures (~300C). The hybrid bond interconnect is well suited to chiplet integration. In that process, disaggregation of circuit function allows for optimized wafer fabrication which is integrated into a module through assembly. Recent research has developed reliable hybrid bond interconnect configurations, handling small die and reducing the thermal budget for final anneal temperature. Assembly of 1, 4, and 8 die stacks with direct bond interconnect has been achieved. Die sizes ranging from 0.4 to 28 mm were bonded with high yield. Our work has also explored the design flexibility of the hybrid interconnect with respect to die edge proximity, pitch, and pad size. Cu grain engineering studies allowed thermal budget reduction to ~ 200C. Finally, the interconnect’s reliability was tested to JEDEC standards for single die and multi-die stack configurations, demonstrating the performance of the hybrid bond to hybrid bond pad as well as the hybrid bond to TSV (through silicon via) interconnect.

Paper Author: Laura Mirkarimi, VP 3D Technologies, Adeia

Author Bio: Laura Mirkarimi is VP Engineering 3D Portfolio and Bonding Technology at Adeia, an independent IP licensing company recently spun off from Xperi/Invensas. She heads Adeia’s technology development team, which focuses on electronic package development and semiconductor materials process integration. Before joining Xperi, she developed electronic devices including ferroelectric memory, transparent conductors, and photonic crystal resonators at Hewlett Packard Laboratories. She holds more than 55 patents and has 48 publications at such events as IEEE Electronics Components and Technology Conference (ECTC) and International Wafer-Level Packaging Conference (IWLPC). She earned a PhD in materials science and engineering at Northwestern University.